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arm64: dts: ls1046a-qds: add mmio based mdio-mux nodes for FPGA

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There is mmio based mdio mux function in the FPGA device on ls1046a-qds
board.  Add the mmio based mdio-mux nodes to ls1043a-qds boards and
add simple-mfd as a compatbile for the FPGA node to reflect the
multi-function nature of it.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Li Yang 2022-09-15 18:34:31 -05:00 committed by Shawn Guo
parent 0f62994a55
commit 63c396414b
1 changed files with 153 additions and 2 deletions
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155
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
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@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
* Copyright 2018-2019 NXP
*
* Shaohui Xie <Shaohui.Xie@nxp.com>
*/
@ -17,14 +17,26 @@
compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
aliases {
emi1-slot1 = &ls1046mdio_s1;
emi1-slot2 = &ls1046mdio_s2;
emi1-slot4 = &ls1046mdio_s4;
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
serial0 = &duart0;
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
sgmii-s1-p1 = &sgmii_phy_s1_p1;
sgmii-s1-p2 = &sgmii_phy_s1_p2;
sgmii-s1-p3 = &sgmii_phy_s1_p3;
sgmii-s1-p4 = &sgmii_phy_s1_p4;
sgmii-s4-p1 = &sgmii_phy_s4_p1;
};
chosen {
@ -153,8 +165,9 @@
};
fpga: board-control@2,0 {
compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
reg = <0x2 0x0 0x0000100>;
ranges = <0 2 0 0x100>;
};
};
@ -177,3 +190,141 @@
};
#include "fsl-ls1046-post.dtsi"
&fman0 {
ethernet@e0000 {
phy-handle = <&qsgmii_phy_s2_p1>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&sgmii_phy_s4_p1>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&sgmii_phy_s1_p3>;
phy-connection-type = "sgmii";
};
ethernet@ea000 {
phy-handle = <&sgmii_phy_s1_p4>;
phy-connection-type = "sgmii";
};
ethernet@f0000 { /* DTSEC9/10GEC1 */
phy-handle = <&sgmii_phy_s1_p1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 { /* DTSEC10/10GEC2 */
phy-handle = <&sgmii_phy_s1_p2>;
phy-connection-type = "xgmii";
};
};
&fpga {
#address-cells = <1>;
#size-cells = <1>;
mdio-mux-emi1 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x54 1>; /* BRDCFG4 */
mux-mask = <0xe0>; /* EMI1 */
/* On-board RGMII1 PHY */
ls1046mdio0: mdio@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
rgmii_phy1: ethernet-phy@1 { /* MAC3 */
reg = <0x1>;
};
};
/* On-board RGMII2 PHY */
ls1046mdio1: mdio@1 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
rgmii_phy2: ethernet-phy@2 { /* MAC4 */
reg = <0x2>;
};
};
/* Slot 1 */
ls1046mdio_s1: mdio@2 {
reg = <0x40>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sgmii_phy_s1_p1: ethernet-phy@1c {
reg = <0x1c>;
};
sgmii_phy_s1_p2: ethernet-phy@1d {
reg = <0x1d>;
};
sgmii_phy_s1_p3: ethernet-phy@1e {
reg = <0x1e>;
};
sgmii_phy_s1_p4: ethernet-phy@1f {
reg = <0x1f>;
};
};
/* Slot 2 */
ls1046mdio_s2: mdio@3 {
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
qsgmii_phy_s2_p1: ethernet-phy@8 {
reg = <0x8>;
};
qsgmii_phy_s2_p2: ethernet-phy@9 {
reg = <0x9>;
};
qsgmii_phy_s2_p3: ethernet-phy@a {
reg = <0xa>;
};
qsgmii_phy_s2_p4: ethernet-phy@b {
reg = <0xb>;
};
};
/* Slot 4 */
ls1046mdio_s4: mdio@5 {
reg = <0x80>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sgmii_phy_s4_p1: ethernet-phy@1c {
reg = <0x1c>;
};
};
};
};