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Merge branch 'net-phy-cleanups'

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Weihang Li says:

====================
net: phy: fix some coding-style issues

Make some cleanups according to the coding style of kernel.

Changes since v1:
- Update commit description of #1 and #3.
- Avoid changing the indentation in #2.
- Change a group of if-else statement into switch from #4 and put it into
  a single patch.
- Put '|' at the end of line in #5 and #7.
- Avoid deleting spaces in definition of 'settings' in #5.
- Drop #8 from the series which needs more discussion with David.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2021-06-16 12:34:08 -07:00
commit 63e96bc4e3
21 changed files with 78 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/phy/bcm87xx.c
View File

@ -54,9 +54,9 @@ static int bcm87xx_of_reg_init(struct phy_device *phydev)
u16 reg = be32_to_cpup(paddr++);
u16 mask = be32_to_cpup(paddr++);
u16 val_bits = be32_to_cpup(paddr++);
int val;
u32 regnum = mdiobus_c45_addr(devid, reg);
val = 0;
int val = 0;
if (mask) {
val = phy_read(phydev, regnum);
if (val < 0) {

6
drivers/net/phy/davicom.c
View File

@ -43,10 +43,10 @@
#define MII_DM9161_INTR_DPLX_CHANGE 0x0010
#define MII_DM9161_INTR_SPD_CHANGE 0x0008
#define MII_DM9161_INTR_LINK_CHANGE 0x0004
#define MII_DM9161_INTR_INIT 0x0000
#define MII_DM9161_INTR_INIT 0x0000
#define MII_DM9161_INTR_STOP \
(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
| MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK | \
MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
#define MII_DM9161_INTR_CHANGE \
(MII_DM9161_INTR_DPLX_CHANGE | \
MII_DM9161_INTR_SPD_CHANGE | \

5
drivers/net/phy/dp83640.c
View File

@ -170,9 +170,9 @@ static ushort gpio_tab[GPIO_TABLE_SIZE] = {
module_param(chosen_phy, int, 0444);
module_param_array(gpio_tab, ushort, NULL, 0444);
MODULE_PARM_DESC(chosen_phy, \
MODULE_PARM_DESC(chosen_phy,
"The address of the PHY to use for the ancillary clock features");
MODULE_PARM_DESC(gpio_tab, \
MODULE_PARM_DESC(gpio_tab,
"Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
@ -615,6 +615,7 @@ static void prune_rx_ts(struct dp83640_private *dp83640)
static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
{
int val;
phy_write(phydev, PAGESEL, 0);
val = phy_read(phydev, PHYCR2);
if (on)

15
drivers/net/phy/et1011c.c
View File

@ -46,8 +46,8 @@ MODULE_LICENSE("GPL");
static int et1011c_config_aneg(struct phy_device *phydev)
{
int ctl = 0;
ctl = phy_read(phydev, MII_BMCR);
int ctl = phy_read(phydev, MII_BMCR);
if (ctl < 0)
return ctl;
ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 |
@ -60,9 +60,10 @@ static int et1011c_config_aneg(struct phy_device *phydev)
static int et1011c_read_status(struct phy_device *phydev)
{
static int speed;
int ret;
u32 val;
static int speed;
ret = genphy_read_status(phydev);
if (speed != phydev->speed) {
@ -72,10 +73,10 @@ static int et1011c_read_status(struct phy_device *phydev)
ET1011C_GIGABIT_SPEED) {
val = phy_read(phydev, ET1011C_CONFIG_REG);
val &= ~ET1011C_TX_FIFO_MASK;
phy_write(phydev, ET1011C_CONFIG_REG, val\
| ET1011C_GMII_INTERFACE\
| ET1011C_SYS_CLK_EN\
| ET1011C_TX_FIFO_DEPTH_16);
phy_write(phydev, ET1011C_CONFIG_REG, val |
ET1011C_GMII_INTERFACE |
ET1011C_SYS_CLK_EN |
ET1011C_TX_FIFO_DEPTH_16);
}
}

4
drivers/net/phy/fixed_phy.c
View File

@ -161,8 +161,8 @@ static int fixed_phy_add_gpiod(unsigned int irq, int phy_addr,
}
int fixed_phy_add(unsigned int irq, int phy_addr,
struct fixed_phy_status *status) {
struct fixed_phy_status *status)
{
return fixed_phy_add_gpiod(irq, phy_addr, status, NULL);
}
EXPORT_SYMBOL_GPL(fixed_phy_add);

4
drivers/net/phy/lxt.c
View File

@ -242,8 +242,8 @@ static int lxt973a2_read_status(struct phy_device *phydev)
return lpa;
/* If both registers are equal, it is suspect but not
* impossible, hence a new try
*/
* impossible, hence a new try
*/
} while (lpa == adv && retry--);
mii_lpa_to_linkmode_lpa_t(phydev->lp_advertising, lpa);

13
drivers/net/phy/marvell.c
View File

@ -809,14 +809,19 @@ static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
{
int delay;
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
switch (phydev->interface) {
case PHY_INTERFACE_MODE_RGMII_ID:
delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
break;
case PHY_INTERFACE_MODE_RGMII_RXID:
delay = MII_M1111_RGMII_RX_DELAY;
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
break;
case PHY_INTERFACE_MODE_RGMII_TXID:
delay = MII_M1111_RGMII_TX_DELAY;
} else {
break;
default:
delay = 0;
break;
}
return phy_modify(phydev, MII_M1111_PHY_EXT_CR,

1
drivers/net/phy/mdio_bus.c
View File

@ -175,6 +175,7 @@ EXPORT_SYMBOL(mdiobus_alloc_size);
static void mdiobus_release(struct device *d)
{
struct mii_bus *bus = to_mii_bus(d);
BUG_ON(bus->state != MDIOBUS_RELEASED &&
/* for compatibility with error handling in drivers */
bus->state != MDIOBUS_ALLOCATED);

4
drivers/net/phy/mdio_device.c
View File

@ -77,7 +77,7 @@ int mdio_device_register(struct mdio_device *mdiodev)
{
int err;
dev_dbg(&mdiodev->dev, "mdio_device_register\n");
dev_dbg(&mdiodev->dev, "%s\n", __func__);
err = mdiobus_register_device(mdiodev);
if (err)
@ -188,7 +188,7 @@ int mdio_driver_register(struct mdio_driver *drv)
struct mdio_driver_common *mdiodrv = &drv->mdiodrv;
int retval;
pr_debug("mdio_driver_register: %s\n", mdiodrv->driver.name);
pr_debug("%s: %s\n", __func__, mdiodrv->driver.name);
mdiodrv->driver.bus = &mdio_bus_type;
mdiodrv->driver.probe = mdio_probe;

6
drivers/net/phy/national.c
View File

@ -68,7 +68,8 @@ static int ns_ack_interrupt(struct phy_device *phydev)
return ret;
/* Clear the interrupt status bit by writing a “1”
* to the corresponding bit in INT_CLEAR (2:0 are reserved) */
* to the corresponding bit in INT_CLEAR (2:0 are reserved)
*/
ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
return ret;
@ -150,7 +151,8 @@ static int ns_config_init(struct phy_device *phydev)
{
ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
/* In the latest MAC or switches design, the 10 Mbps loopback
is desired to be turned off. */
* is desired to be turned off.
*/
ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
return ns_ack_interrupt(phydev);
}

2
drivers/net/phy/phy-c45.c
View File

@ -172,7 +172,7 @@ EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
* @phydev: target phy_device struct
*
* Disable auto-negotiation in the Clause 45 PHY. The link parameters
* parameters are controlled through the PMA/PMD MMD registers.
* are controlled through the PMA/PMD MMD registers.
*
* Returns zero on success, negative errno code on failure.
*/

3
drivers/net/phy/phy-core.c
View File

@ -76,7 +76,8 @@ EXPORT_SYMBOL_GPL(phy_duplex_to_str);
/* A mapping of all SUPPORTED settings to speed/duplex. This table
* must be grouped by speed and sorted in descending match priority
* - iow, descending speed. */
* - iow, descending speed.
*/
#define PHY_SETTING(s, d, b) { .speed = SPEED_ ## s, .duplex = DUPLEX_ ## d, \
.bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}

3
drivers/net/phy/phy.c
View File

@ -380,8 +380,7 @@ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
else if (val & BMCR_SPEED100)
phydev->speed = SPEED_100;
else phydev->speed = SPEED_10;
}
else {
} else {
if (phydev->autoneg == AUTONEG_DISABLE)
change_autoneg = true;
phydev->autoneg = AUTONEG_ENABLE;

9
drivers/net/phy/phy_device.c
View File

@ -3021,15 +3021,14 @@ static int phy_probe(struct device *dev)
* a controller will attach, and may modify one
* or both of these values
*/
if (phydrv->features) {
if (phydrv->features)
linkmode_copy(phydev->supported, phydrv->features);
} else if (phydrv->get_features) {
else if (phydrv->get_features)
err = phydrv->get_features(phydev);
} else if (phydev->is_c45) {
else if (phydev->is_c45)
err = genphy_c45_pma_read_abilities(phydev);
} else {
else
err = genphy_read_abilities(phydev);
}
if (err)
goto out;

14
drivers/net/phy/phylink.c
View File

@ -182,7 +182,8 @@ static int phylink_parse_fixedlink(struct phylink *pl,
pl->link_config.duplex = DUPLEX_FULL;
/* We treat the "pause" and "asym-pause" terminology as
* defining the link partner's ability. */
* defining the link partner's ability.
*/
if (fwnode_property_read_bool(fixed_node, "pause"))
__set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
pl->link_config.lp_advertising);
@ -685,7 +686,8 @@ static void phylink_resolve(struct work_struct *w)
phylink_mac_pcs_get_state(pl, &link_state);
/* If we have a phy, the "up" state is the union of
* both the PHY and the MAC */
* both the PHY and the MAC
*/
if (pl->phydev)
link_state.link &= pl->phy_state.link;
@ -694,7 +696,8 @@ static void phylink_resolve(struct work_struct *w)
link_state.interface = pl->phy_state.interface;
/* If we have a PHY, we need to update with
* the PHY flow control bits. */
* the PHY flow control bits.
*/
link_state.pause = pl->phy_state.pause;
mac_config = true;
}
@ -1380,11 +1383,10 @@ int phylink_ethtool_ksettings_get(struct phylink *pl,
ASSERT_RTNL();
if (pl->phydev) {
if (pl->phydev)
phy_ethtool_ksettings_get(pl->phydev, kset);
} else {
else
kset->base.port = pl->link_port;
}
linkmode_copy(kset->link_modes.supported, pl->supported);

1
drivers/net/phy/qsemi.c
View File

@ -100,6 +100,7 @@ static int qs6612_ack_interrupt(struct phy_device *phydev)
static int qs6612_config_intr(struct phy_device *phydev)
{
int err;
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
/* clear any interrupts before enabling them */
err = qs6612_ack_interrupt(phydev);

28
drivers/net/phy/sfp-bus.c
View File

@ -629,14 +629,14 @@ static void sfp_upstream_clear(struct sfp_bus *bus)
* be put via sfp_bus_put() when done.
*
* Returns:
* - on success, a pointer to the sfp_bus structure,
* - %NULL if no SFP is specified,
* - on failure, an error pointer value:
* - on success, a pointer to the sfp_bus structure,
* - %NULL if no SFP is specified,
* - on failure, an error pointer value:
*
* - corresponding to the errors detailed for
* fwnode_property_get_reference_args().
* - %-ENOMEM if we failed to allocate the bus.
* - an error from the upstream's connect_phy() method.
* - corresponding to the errors detailed for
* fwnode_property_get_reference_args().
* - %-ENOMEM if we failed to allocate the bus.
* - an error from the upstream's connect_phy() method.
*/
struct sfp_bus *sfp_bus_find_fwnode(struct fwnode_handle *fwnode)
{
@ -671,14 +671,14 @@ EXPORT_SYMBOL_GPL(sfp_bus_find_fwnode);
* bus, so it is safe to put the bus after this call.
*
* Returns:
* - on success, a pointer to the sfp_bus structure,
* - %NULL if no SFP is specified,
* - on failure, an error pointer value:
* - on success, a pointer to the sfp_bus structure,
* - %NULL if no SFP is specified,
* - on failure, an error pointer value:
*
* - corresponding to the errors detailed for
* fwnode_property_get_reference_args().
* - %-ENOMEM if we failed to allocate the bus.
* - an error from the upstream's connect_phy() method.
* - corresponding to the errors detailed for
* fwnode_property_get_reference_args().
* - %-ENOMEM if we failed to allocate the bus.
* - an error from the upstream's connect_phy() method.
*/
int sfp_bus_add_upstream(struct sfp_bus *bus, void *upstream,
const struct sfp_upstream_ops *ops)

2
drivers/net/phy/sfp.c
View File

@ -2153,7 +2153,7 @@ static void sfp_sm_main(struct sfp *sfp, unsigned int event)
case SFP_S_INIT:
if (event == SFP_E_TIMEOUT && sfp->state & SFP_F_TX_FAULT) {
/* TX_FAULT is still asserted after t_init or
/* TX_FAULT is still asserted after t_init
* or t_start_up, so assume there is a fault.
*/
sfp_sm_fault(sfp, SFP_S_INIT_TX_FAULT,

10
drivers/net/phy/spi_ks8995.c
View File

@ -160,11 +160,11 @@ static const struct spi_device_id ks8995_id[] = {
MODULE_DEVICE_TABLE(spi, ks8995_id);
static const struct of_device_id ks8895_spi_of_match[] = {
{ .compatible = "micrel,ks8995" },
{ .compatible = "micrel,ksz8864" },
{ .compatible = "micrel,ksz8795" },
{ },
};
{ .compatible = "micrel,ks8995" },
{ .compatible = "micrel,ksz8864" },
{ .compatible = "micrel,ksz8795" },
{ },
};
MODULE_DEVICE_TABLE(of, ks8895_spi_of_match);
static inline u8 get_chip_id(u8 val)

6
drivers/net/phy/ste10Xp.c
View File

@ -20,12 +20,12 @@
#include <linux/mii.h>
#include <linux/phy.h>
#define MII_XCIIS 0x11 /* Configuration Info IRQ & Status Reg */
#define MII_XIE 0x12 /* Interrupt Enable Register */
#define MII_XCIIS 0x11 /* Configuration Info IRQ & Status Reg */
#define MII_XIE 0x12 /* Interrupt Enable Register */
#define MII_XIE_DEFAULT_MASK 0x0070 /* ANE complete, Remote Fault, Link Down */
#define STE101P_PHY_ID 0x00061c50
#define STE100P_PHY_ID 0x1c040011
#define STE100P_PHY_ID 0x1c040011
static int ste10Xp_config_init(struct phy_device *phydev)
{

3
drivers/net/phy/vitesse.c
View File

@ -249,7 +249,8 @@ static int vsc73xx_config_aneg(struct phy_device *phydev)
/* This adds a skew for both TX and RX clocks, so the skew should only be
* applied to "rgmii-id" interfaces. It may not work as expected
* on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. */
* on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces.
*/
static int vsc8601_add_skew(struct phy_device *phydev)
{
int ret;