perf vendors events arm64: Arm Cortex-A73
Add PMU events for Arm Cortex-A73 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a73.json which is based on PMU event descriptions from the Arm Cortex-A73 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-7-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Nick Forrington
Arnaldo Carvalho de Melo
parent
6951dee812
commit
64a091c67a
11
tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json
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11
tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json
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@ -0,0 +1,11 @@
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[
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{
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"ArchStdEvent": "BR_MIS_PRED"
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},
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{
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"ArchStdEvent": "BR_PRED"
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},
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{
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"ArchStdEvent": "BR_INDIRECT_SPEC"
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}
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]
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23
tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json
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23
tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json
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@ -0,0 +1,23 @@
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[
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{
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"ArchStdEvent": "CPU_CYCLES"
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},
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{
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"ArchStdEvent": "BUS_ACCESS"
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},
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{
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"ArchStdEvent": "BUS_CYCLES"
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},
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{
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"ArchStdEvent": "BUS_ACCESS_SHARED"
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},
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{
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"ArchStdEvent": "BUS_ACCESS_NOT_SHARED"
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},
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{
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"ArchStdEvent": "BUS_ACCESS_NORMAL"
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},
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{
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"ArchStdEvent": "BUS_ACCESS_PERIPH"
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}
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]
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107
tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json
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107
tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json
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@ -0,0 +1,107 @@
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[
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{
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"ArchStdEvent": "L1I_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1I_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1I_CACHE"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB"
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},
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{
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"ArchStdEvent": "L2D_CACHE"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB"
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},
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{
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"ArchStdEvent": "L1D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
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},
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{
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"ArchStdEvent": "L2D_CACHE_INVAL"
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},
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{
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"PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
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"EventCode": "0xC2",
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"EventName": "I_TAG_RAM_RD",
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"BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
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},
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{
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"PublicDescription": "Number of ways read in the instruction cache - Data RAM",
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"EventCode": "0xC3",
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"EventName": "I_DATA_RAM_RD",
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"BriefDescription": "Number of ways read in the instruction cache - Data RAM"
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},
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{
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"PublicDescription": "Number of ways read in the instruction BTAC RAM",
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"EventCode": "0xC4",
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"EventName": "I_BTAC_RAM_RD",
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"BriefDescription": "Number of ways read in the instruction BTAC RAM"
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},
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{
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"PublicDescription": "Level 1 PLD TLB refill",
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"EventCode": "0xE7",
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"EventName": "PLD_UTLB_REFILL",
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"BriefDescription": "Level 1 PLD TLB refill"
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},
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{
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"PublicDescription": "Level 1 CP15 TLB refill",
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"EventCode": "0xE8",
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"EventName": "CP15_UTLB_REFILL",
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"BriefDescription": "Level 1 CP15 TLB refill"
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},
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{
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"PublicDescription": "Level 1 TLB flush",
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"EventCode": "0xE9",
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"EventName": "UTLB_FLUSH",
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"BriefDescription": "Level 1 TLB flush"
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},
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{
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"PublicDescription": "Level 2 TLB access",
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"EventCode": "0xEA",
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"EventName": "TLB_ACCESS",
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"BriefDescription": "Level 2 TLB access"
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},
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{
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"PublicDescription": "Level 2 TLB miss",
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"EventCode": "0xEB",
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"EventName": "TLB_MISS",
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"BriefDescription": "Level 2 TLB miss"
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},
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{
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"PublicDescription": "Data cache hit in itself due to VIPT aliasing",
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"EventCode": "0xEC",
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"EventName": "DCACHE_SELF_HIT_VIPT",
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"BriefDescription": "Data cache hit in itself due to VIPT aliasing"
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}
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]
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14
tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json
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14
tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json
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[
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{
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"PublicDescription": "ETM trace unit output 0",
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"EventCode": "0xDE",
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"EventName": "ETM_EXT_OUT0",
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"BriefDescription": "ETM trace unit output 0"
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},
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{
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"PublicDescription": "ETM trace unit output 1",
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"EventCode": "0xDF",
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"EventName": "ETM_EXT_OUT1",
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"BriefDescription": "ETM trace unit output 1"
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}
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]
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@ -0,0 +1,14 @@
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[
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{
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"ArchStdEvent": "EXC_TAKEN"
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},
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{
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"ArchStdEvent": "EXC_HVC"
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},
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{
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"PublicDescription": "Number of Traps to hypervisor",
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"EventCode": "0xDC",
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"EventName": "EXC_TRAP_HYP",
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"BriefDescription": "Number of Traps to hypervisor"
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}
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]
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@ -0,0 +1,65 @@
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[
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{
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"ArchStdEvent": "SW_INCR"
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},
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{
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"ArchStdEvent": "INST_RETIRED"
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},
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{
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"ArchStdEvent": "EXC_RETURN"
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},
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{
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"ArchStdEvent": "CID_WRITE_RETIRED"
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},
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{
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"ArchStdEvent": "PC_WRITE_RETIRED"
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},
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{
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"ArchStdEvent": "BR_IMMED_RETIRED"
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},
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{
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"ArchStdEvent": "BR_RETURN_RETIRED"
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},
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{
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"ArchStdEvent": "INST_SPEC"
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},
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{
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"ArchStdEvent": "TTBR_WRITE_RETIRED"
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},
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{
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"ArchStdEvent": "LDREX_SPEC"
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},
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{
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"ArchStdEvent": "STREX_FAIL_SPEC"
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},
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{
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"ArchStdEvent": "LD_SPEC"
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},
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{
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"ArchStdEvent": "ST_SPEC"
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},
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{
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"ArchStdEvent": "LDST_SPEC"
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},
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{
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"ArchStdEvent": "DP_SPEC"
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},
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{
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"ArchStdEvent": "ASE_SPEC"
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},
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{
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"ArchStdEvent": "VFP_SPEC"
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},
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{
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"ArchStdEvent": "CRYPTO_SPEC"
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},
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{
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"ArchStdEvent": "ISB_SPEC"
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},
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{
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"ArchStdEvent": "DSB_SPEC"
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},
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{
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"ArchStdEvent": "DMB_SPEC"
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}
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]
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14
tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.json
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14
tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.json
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@ -0,0 +1,14 @@
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[
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{
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"ArchStdEvent": "MEM_ACCESS"
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},
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{
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"ArchStdEvent": "MEM_ACCESS_RD"
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},
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{
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"ArchStdEvent": "MEM_ACCESS_WR"
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},
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{
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"ArchStdEvent": "UNALIGNED_LDST_SPEC"
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}
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]
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44
tools/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json
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44
tools/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json
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[
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{
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"PublicDescription": "Duration of a translation table walk handled by the MMU",
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"EventCode": "0xE0",
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"EventName": "MMU_PTW",
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"BriefDescription": "Duration of a translation table walk handled by the MMU"
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},
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{
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"PublicDescription": "Duration of a Stage 1 translation table walk handled by the MMU",
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"EventCode": "0xE1",
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"EventName": "MMU_PTW_ST1",
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"BriefDescription": "Duration of a Stage 1 translation table walk handled by the MMU"
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},
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{
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"PublicDescription": "Duration of a Stage 2 translation table walk handled by the MMU",
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"EventCode": "0xE2",
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"EventName": "MMU_PTW_ST2",
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"BriefDescription": "Duration of a Stage 2 translation table walk handled by the MMU"
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},
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{
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"PublicDescription": "Duration of a translation table walk requested by the LSU",
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"EventCode": "0xE3",
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"EventName": "MMU_PTW_LSU",
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"BriefDescription": "Duration of a translation table walk requested by the LSU"
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},
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{
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"PublicDescription": "Duration of a translation table walk requested by the Instruction Side",
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"EventCode": "0xE4",
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"EventName": "MMU_PTW_ISIDE",
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"BriefDescription": "Duration of a translation table walk requested by the Instruction Side"
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},
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{
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"PublicDescription": "Duration of a translation table walk requested by a Preload instruction or Prefetch request",
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"EventCode": "0xE5",
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"EventName": "MMU_PTW_PLD",
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"BriefDescription": "Duration of a translation table walk requested by a Preload instruction or Prefetch request"
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},
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{
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"PublicDescription": "Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA to PA operations)",
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"EventCode": "0xE6",
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"EventName": "MMU_PTW_CP15",
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"BriefDescription": "Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA to PA operations)"
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}
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]
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@ -0,0 +1,38 @@
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[
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{
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"PublicDescription": "A linefill caused an instruction side stall",
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"EventCode": "0xC0",
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"EventName": "LF_STALL",
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"BriefDescription": "A linefill caused an instruction side stall"
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},
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{
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"PublicDescription": "A translation table walk caused an instruction side stall",
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"EventCode": "0xC1",
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"EventName": "PTW_STALL",
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"BriefDescription": "A translation table walk caused an instruction side stall"
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},
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{
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"PublicDescription": "Duration for which all slots in the Load-Store Unit are busy",
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"EventCode": "0xD3",
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"EventName": "D_LSU_SLOT_FULL",
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"BriefDescription": "Duration for which all slots in the Load-Store Unit are busy"
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},
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{
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"PublicDescription": "Duration for which all slots in the load-store issue queue are busy",
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"EventCode": "0xD8",
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"EventName": "LS_IQ_FULL",
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"BriefDescription": "Duration for which all slots in the load-store issue queue are busy"
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},
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{
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"PublicDescription": "Duration for which all slots in the data processing issue queue are busy",
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"EventCode": "0xD9",
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"EventName": "DP_IQ_FULL",
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"BriefDescription": "Duration for which all slots in the data processing issue queue are busy"
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},
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{
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"PublicDescription": "Duration for which all slots in the Data Engine issue queue are busy",
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"EventCode": "0xDA",
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"EventName": "DE_IQ_FULL",
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"BriefDescription": "Duration for which all slots in the Data Engine issue queue are busy"
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}
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]
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@ -20,6 +20,7 @@
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0x00000000410fd060,v1,arm/cortex-a65,core
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0x00000000410fd070,v1,arm/cortex-a57-a72,core
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0x00000000410fd080,v1,arm/cortex-a57-a72,core
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0x00000000410fd090,v1,arm/cortex-a73,core
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0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
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0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
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0x00000000410fd400,v1,arm/neoverse-v1,core
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