phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver
Add support for Exynos 5250. This driver is to replace the old USB 2.0 PHY driver. Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Kamil Debski
Kishon Vijay Abraham I
parent
06fb01373c
commit
64bf2b2369
@ -28,6 +28,7 @@ Required properties:
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- compatible : should be one of the listed compatibles:
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- "samsung,exynos4210-usb2-phy"
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- "samsung,exynos4x12-usb2-phy"
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- "samsung,exynos5250-usb2-phy"
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- reg : a list of registers used by phy driver
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- first and obligatory is the location of phy modules registers
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- samsung,sysreg-phandle - handle to syscon used to control the system registers
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@ -136,4 +136,15 @@ config PHY_EXYNOS4X12_USB2
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Samsung USB 2.0 PHY driver is enabled and means that support for this
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particular SoC is compiled in the driver. In case of Exynos 4x12 four
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phys are available - device, host, HSIC0 and HSIC1.
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config PHY_EXYNOS5250_USB2
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bool "Support for Exynos 5250"
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depends on PHY_SAMSUNG_USB2
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depends on SOC_EXYNOS5250
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help
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Enable USB PHY support for Exynos 5250. This option requires that
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Samsung USB 2.0 PHY driver is enabled and means that support for this
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particular SoC is compiled in the driver. In case of Exynos 5250 four
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phys are available - device, host, HSIC0 and HSIC.
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endmenu
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@ -15,3 +15,4 @@ obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o
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obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-samsung-usb2.o
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obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
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obj-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
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obj-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
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404
drivers/phy/phy-exynos5250-usb2.c
Normal file
404
drivers/phy/phy-exynos5250-usb2.c
Normal file
@ -0,0 +1,404 @@
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/*
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* Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* Author: Kamil Debski <k.debski@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include "phy-samsung-usb2.h"
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/* Exynos USB PHY registers */
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#define EXYNOS_5250_REFCLKSEL_CRYSTAL 0x0
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#define EXYNOS_5250_REFCLKSEL_XO 0x1
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#define EXYNOS_5250_REFCLKSEL_CLKCORE 0x2
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#define EXYNOS_5250_FSEL_9MHZ6 0x0
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#define EXYNOS_5250_FSEL_10MHZ 0x1
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#define EXYNOS_5250_FSEL_12MHZ 0x2
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#define EXYNOS_5250_FSEL_19MHZ2 0x3
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#define EXYNOS_5250_FSEL_20MHZ 0x4
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#define EXYNOS_5250_FSEL_24MHZ 0x5
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#define EXYNOS_5250_FSEL_50MHZ 0x7
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/* Normal host */
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#define EXYNOS_5250_HOSTPHYCTRL0 0x0
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#define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL BIT(31)
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#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT 19
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#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_MASK \
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(0x3 << EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT)
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#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT 16
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#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK \
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(0x7 << EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT)
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#define EXYNOS_5250_HOSTPHYCTRL0_TESTBURNIN BIT(11)
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#define EXYNOS_5250_HOSTPHYCTRL0_RETENABLE BIT(10)
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#define EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N BIT(9)
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#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_MASK (0x3 << 7)
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#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_DUAL (0x0 << 7)
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#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ID0 (0x1 << 7)
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#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ANALOGTEST (0x2 << 7)
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#define EXYNOS_5250_HOSTPHYCTRL0_SIDDQ BIT(6)
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#define EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP BIT(5)
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#define EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND BIT(4)
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#define EXYNOS_5250_HOSTPHYCTRL0_WORDINTERFACE BIT(3)
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#define EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST BIT(2)
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#define EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST BIT(1)
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#define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST BIT(0)
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/* HSIC0 & HSIC1 */
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#define EXYNOS_5250_HSICPHYCTRL1 0x10
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#define EXYNOS_5250_HSICPHYCTRL2 0x20
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#define EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_MASK (0x3 << 23)
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#define EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_DEFAULT (0x2 << 23)
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#define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_MASK (0x7f << 16)
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#define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_12 (0x24 << 16)
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#define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_15 (0x1c << 16)
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#define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_16 (0x1a << 16)
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#define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_19_2 (0x15 << 16)
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#define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_20 (0x14 << 16)
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#define EXYNOS_5250_HSICPHYCTRLX_SIDDQ BIT(6)
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#define EXYNOS_5250_HSICPHYCTRLX_FORCESLEEP BIT(5)
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#define EXYNOS_5250_HSICPHYCTRLX_FORCESUSPEND BIT(4)
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#define EXYNOS_5250_HSICPHYCTRLX_WORDINTERFACE BIT(3)
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#define EXYNOS_5250_HSICPHYCTRLX_UTMISWRST BIT(2)
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#define EXYNOS_5250_HSICPHYCTRLX_PHYSWRST BIT(0)
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/* EHCI control */
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#define EXYNOS_5250_HOSTEHCICTRL 0x30
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#define EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN BIT(29)
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#define EXYNOS_5250_HOSTEHCICTRL_ENAINCR4 BIT(28)
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#define EXYNOS_5250_HOSTEHCICTRL_ENAINCR8 BIT(27)
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#define EXYNOS_5250_HOSTEHCICTRL_ENAINCR16 BIT(26)
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#define EXYNOS_5250_HOSTEHCICTRL_AUTOPPDONOVRCUREN BIT(25)
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#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT 19
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#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_MASK \
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(0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT)
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#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_SHIFT 13
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#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_MASK \
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(0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_SHIFT)
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#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL2_SHIFT 7
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#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_MASK \
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(0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT)
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#define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT 1
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#define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_MASK \
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(0x1 << EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT)
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#define EXYNOS_5250_HOSTEHCICTRL_SIMULATIONMODE BIT(0)
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/* OHCI control */
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#define EXYNOS_5250_HOSTOHCICTRL 0x34
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#define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_SHIFT 1
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#define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_MASK \
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(0x3ff << EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_SHIFT)
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#define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVALEN BIT(0)
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/* USBOTG */
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#define EXYNOS_5250_USBOTGSYS 0x38
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#define EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET BIT(14)
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#define EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG BIT(13)
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#define EXYNOS_5250_USBOTGSYS_PHY_SW_RST BIT(12)
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#define EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT 9
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#define EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK \
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(0x3 << EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT)
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#define EXYNOS_5250_USBOTGSYS_ID_PULLUP BIT(8)
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#define EXYNOS_5250_USBOTGSYS_COMMON_ON BIT(7)
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#define EXYNOS_5250_USBOTGSYS_FSEL_SHIFT 4
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#define EXYNOS_5250_USBOTGSYS_FSEL_MASK \
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(0x3 << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT)
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#define EXYNOS_5250_USBOTGSYS_FORCE_SLEEP BIT(3)
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#define EXYNOS_5250_USBOTGSYS_OTGDISABLE BIT(2)
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#define EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG BIT(1)
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#define EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND BIT(0)
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/* Isolation, configured in the power management unit */
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#define EXYNOS_5250_USB_ISOL_OTG_OFFSET 0x704
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#define EXYNOS_5250_USB_ISOL_OTG BIT(0)
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#define EXYNOS_5250_USB_ISOL_HOST_OFFSET 0x708
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#define EXYNOS_5250_USB_ISOL_HOST BIT(0)
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/* Mode swtich register */
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#define EXYNOS_5250_MODE_SWITCH_OFFSET 0x230
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#define EXYNOS_5250_MODE_SWITCH_MASK 1
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#define EXYNOS_5250_MODE_SWITCH_DEVICE 0
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#define EXYNOS_5250_MODE_SWITCH_HOST 1
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enum exynos4x12_phy_id {
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EXYNOS5250_DEVICE,
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EXYNOS5250_HOST,
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EXYNOS5250_HSIC0,
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EXYNOS5250_HSIC1,
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EXYNOS5250_NUM_PHYS,
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};
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/*
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* exynos5250_rate_to_clk() converts the supplied clock rate to the value that
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* can be written to the phy register.
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*/
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static int exynos5250_rate_to_clk(unsigned long rate, u32 *reg)
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{
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/* EXYNOS_5250_FSEL_MASK */
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switch (rate) {
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case 9600 * KHZ:
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*reg = EXYNOS_5250_FSEL_9MHZ6;
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break;
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case 10 * MHZ:
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*reg = EXYNOS_5250_FSEL_10MHZ;
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break;
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case 12 * MHZ:
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*reg = EXYNOS_5250_FSEL_12MHZ;
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break;
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case 19200 * KHZ:
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*reg = EXYNOS_5250_FSEL_19MHZ2;
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break;
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case 20 * MHZ:
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*reg = EXYNOS_5250_FSEL_20MHZ;
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break;
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case 24 * MHZ:
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*reg = EXYNOS_5250_FSEL_24MHZ;
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break;
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case 50 * MHZ:
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*reg = EXYNOS_5250_FSEL_50MHZ;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void exynos5250_isol(struct samsung_usb2_phy_instance *inst, bool on)
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{
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struct samsung_usb2_phy_driver *drv = inst->drv;
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u32 offset;
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u32 mask;
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switch (inst->cfg->id) {
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case EXYNOS5250_DEVICE:
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offset = EXYNOS_5250_USB_ISOL_OTG_OFFSET;
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mask = EXYNOS_5250_USB_ISOL_OTG;
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break;
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case EXYNOS5250_HOST:
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offset = EXYNOS_5250_USB_ISOL_HOST_OFFSET;
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mask = EXYNOS_5250_USB_ISOL_HOST;
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break;
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default:
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return;
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};
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regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
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}
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static int exynos5250_power_on(struct samsung_usb2_phy_instance *inst)
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{
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struct samsung_usb2_phy_driver *drv = inst->drv;
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u32 ctrl0;
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u32 otg;
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u32 ehci;
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u32 ohci;
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u32 hsic;
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switch (inst->cfg->id) {
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case EXYNOS5250_DEVICE:
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regmap_update_bits(drv->reg_sys,
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EXYNOS_5250_MODE_SWITCH_OFFSET,
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EXYNOS_5250_MODE_SWITCH_MASK,
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EXYNOS_5250_MODE_SWITCH_DEVICE);
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/* OTG configuration */
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otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
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/* The clock */
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otg &= ~EXYNOS_5250_USBOTGSYS_FSEL_MASK;
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otg |= drv->ref_reg_val << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT;
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/* Reset */
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otg &= ~(EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
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EXYNOS_5250_USBOTGSYS_FORCE_SLEEP |
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EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG);
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otg |= EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
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EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET |
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EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
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EXYNOS_5250_USBOTGSYS_OTGDISABLE;
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/* Ref clock */
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otg &= ~EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK;
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otg |= EXYNOS_5250_REFCLKSEL_CLKCORE <<
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EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT;
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writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
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udelay(100);
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otg &= ~(EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
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EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
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EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET |
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EXYNOS_5250_USBOTGSYS_OTGDISABLE);
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writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
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break;
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case EXYNOS5250_HOST:
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case EXYNOS5250_HSIC0:
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case EXYNOS5250_HSIC1:
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/* Host registers configuration */
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ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
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/* The clock */
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ctrl0 &= ~EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK;
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ctrl0 |= drv->ref_reg_val <<
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EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT;
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/* Reset */
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ctrl0 &= ~(EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST |
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EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL |
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EXYNOS_5250_HOSTPHYCTRL0_SIDDQ |
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EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND |
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EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP);
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ctrl0 |= EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST |
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EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST |
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EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N;
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writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
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udelay(10);
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ctrl0 &= ~(EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST |
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EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST);
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writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
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/* OTG configuration */
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otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
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/* The clock */
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otg &= ~EXYNOS_5250_USBOTGSYS_FSEL_MASK;
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otg |= drv->ref_reg_val << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT;
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/* Reset */
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otg &= ~(EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
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EXYNOS_5250_USBOTGSYS_FORCE_SLEEP |
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EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG);
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otg |= EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
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EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET |
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EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
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EXYNOS_5250_USBOTGSYS_OTGDISABLE;
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/* Ref clock */
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otg &= ~EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK;
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otg |= EXYNOS_5250_REFCLKSEL_CLKCORE <<
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EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT;
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writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
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udelay(10);
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otg &= ~(EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
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EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
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EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET);
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/* HSIC phy configuration */
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hsic = (EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_12 |
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EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_DEFAULT |
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EXYNOS_5250_HSICPHYCTRLX_PHYSWRST);
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writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
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writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
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udelay(10);
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hsic &= ~EXYNOS_5250_HSICPHYCTRLX_PHYSWRST;
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writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
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writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
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/* The following delay is necessary for the reset sequence to be
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* completed */
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udelay(80);
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/* Enable EHCI DMA burst */
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ehci = readl(drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL);
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ehci |= EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN |
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EXYNOS_5250_HOSTEHCICTRL_ENAINCR4 |
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EXYNOS_5250_HOSTEHCICTRL_ENAINCR8 |
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EXYNOS_5250_HOSTEHCICTRL_ENAINCR16;
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writel(ehci, drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL);
|
||||
|
||||
/* OHCI settings */
|
||||
ohci = readl(drv->reg_phy + EXYNOS_5250_HOSTOHCICTRL);
|
||||
/* Following code is based on the old driver */
|
||||
ohci |= 0x1 << 3;
|
||||
writel(ohci, drv->reg_phy + EXYNOS_5250_HOSTOHCICTRL);
|
||||
|
||||
break;
|
||||
}
|
||||
inst->enabled = 1;
|
||||
exynos5250_isol(inst, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int exynos5250_power_off(struct samsung_usb2_phy_instance *inst)
|
||||
{
|
||||
struct samsung_usb2_phy_driver *drv = inst->drv;
|
||||
u32 ctrl0;
|
||||
u32 otg;
|
||||
u32 hsic;
|
||||
|
||||
inst->enabled = 0;
|
||||
exynos5250_isol(inst, 1);
|
||||
|
||||
switch (inst->cfg->id) {
|
||||
case EXYNOS5250_DEVICE:
|
||||
otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
|
||||
otg |= (EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
|
||||
EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG |
|
||||
EXYNOS_5250_USBOTGSYS_FORCE_SLEEP);
|
||||
writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
|
||||
break;
|
||||
case EXYNOS5250_HOST:
|
||||
ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
|
||||
ctrl0 |= (EXYNOS_5250_HOSTPHYCTRL0_SIDDQ |
|
||||
EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND |
|
||||
EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP |
|
||||
EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST |
|
||||
EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL);
|
||||
writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
|
||||
break;
|
||||
case EXYNOS5250_HSIC0:
|
||||
case EXYNOS5250_HSIC1:
|
||||
hsic = (EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_12 |
|
||||
EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_DEFAULT |
|
||||
EXYNOS_5250_HSICPHYCTRLX_SIDDQ |
|
||||
EXYNOS_5250_HSICPHYCTRLX_FORCESLEEP |
|
||||
EXYNOS_5250_HSICPHYCTRLX_FORCESUSPEND
|
||||
);
|
||||
writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
|
||||
writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static const struct samsung_usb2_common_phy exynos5250_phys[] = {
|
||||
{
|
||||
.label = "device",
|
||||
.id = EXYNOS5250_DEVICE,
|
||||
.power_on = exynos5250_power_on,
|
||||
.power_off = exynos5250_power_off,
|
||||
},
|
||||
{
|
||||
.label = "host",
|
||||
.id = EXYNOS5250_HOST,
|
||||
.power_on = exynos5250_power_on,
|
||||
.power_off = exynos5250_power_off,
|
||||
},
|
||||
{
|
||||
.label = "hsic0",
|
||||
.id = EXYNOS5250_HSIC0,
|
||||
.power_on = exynos5250_power_on,
|
||||
.power_off = exynos5250_power_off,
|
||||
},
|
||||
{
|
||||
.label = "hsic1",
|
||||
.id = EXYNOS5250_HSIC1,
|
||||
.power_on = exynos5250_power_on,
|
||||
.power_off = exynos5250_power_off,
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
const struct samsung_usb2_phy_config exynos5250_usb2_phy_config = {
|
||||
.has_mode_switch = 1,
|
||||
.num_phys = EXYNOS5250_NUM_PHYS,
|
||||
.phys = exynos5250_phys,
|
||||
.rate_to_clk = exynos5250_rate_to_clk,
|
||||
};
|
||||
@ -98,6 +98,12 @@ static const struct of_device_id samsung_usb2_phy_of_match[] = {
|
||||
.compatible = "samsung,exynos4x12-usb2-phy",
|
||||
.data = &exynos4x12_usb2_phy_config,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PHY_EXYNOS5250_USB2
|
||||
{
|
||||
.compatible = "samsung,exynos5250-usb2-phy",
|
||||
.data = &exynos5250_usb2_phy_config,
|
||||
},
|
||||
#endif
|
||||
{ },
|
||||
};
|
||||
|
||||
@ -63,4 +63,5 @@ struct samsung_usb2_phy_config {
|
||||
|
||||
extern const struct samsung_usb2_phy_config exynos4210_usb2_phy_config;
|
||||
extern const struct samsung_usb2_phy_config exynos4x12_usb2_phy_config;
|
||||
extern const struct samsung_usb2_phy_config exynos5250_usb2_phy_config;
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user