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Merge drm/drm-next into drm-misc-next

Browse Source 
4.19 is out, Lyude asked for a backmerge, and it's been a while. All
very good reasons on their own :-)

Signed-off-by: Sean Paul <seanpaul@chromium.org>
This commit is contained in:
Sean Paul
2018-10-24 14:26:04 -04:00
parent 2b02a05bdc f2bfc71aee
commit 6542e9adc0
629 changed files with 13840 additions and 9844 deletions
Download Patch File Download Diff File Expand all files Collapse all files

178
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -338,14 +338,6 @@ static int dm_set_powergating_state(void *handle,
/* Prototypes of private functions */
static int dm_early_init(void* handle);
static void hotplug_notify_work_func(struct work_struct *work)
{
struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
struct drm_device *dev = dm->ddev;
drm_kms_helper_hotplug_event(dev);
}
/* Allocate memory for FBC compressed data */
static void amdgpu_dm_fbc_init(struct drm_connector *connector)
{
@ -447,8 +439,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
goto error;
}
INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
if (!adev->dm.freesync_module) {
DRM_ERROR(
@ -728,6 +718,87 @@ amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
return NULL;
}
static void emulated_link_detect(struct dc_link *link)
{
struct dc_sink_init_data sink_init_data = { 0 };
struct display_sink_capability sink_caps = { 0 };
enum dc_edid_status edid_status;
struct dc_context *dc_ctx = link->ctx;
struct dc_sink *sink = NULL;
struct dc_sink *prev_sink = NULL;
link->type = dc_connection_none;
prev_sink = link->local_sink;
if (prev_sink != NULL)
dc_sink_retain(prev_sink);
switch (link->connector_signal) {
case SIGNAL_TYPE_HDMI_TYPE_A: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
break;
}
case SIGNAL_TYPE_DVI_SINGLE_LINK: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
break;
}
case SIGNAL_TYPE_DVI_DUAL_LINK: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
break;
}
case SIGNAL_TYPE_LVDS: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_LVDS;
break;
}
case SIGNAL_TYPE_EDP: {
sink_caps.transaction_type =
DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
sink_caps.signal = SIGNAL_TYPE_EDP;
break;
}
case SIGNAL_TYPE_DISPLAY_PORT: {
sink_caps.transaction_type =
DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
break;
}
default:
DC_ERROR("Invalid connector type! signal:%d\n",
link->connector_signal);
return;
}
sink_init_data.link = link;
sink_init_data.sink_signal = sink_caps.signal;
sink = dc_sink_create(&sink_init_data);
if (!sink) {
DC_ERROR("Failed to create sink!\n");
return;
}
link->local_sink = sink;
edid_status = dm_helpers_read_local_edid(
link->ctx,
link,
sink);
if (edid_status != EDID_OK)
DC_ERROR("Failed to read EDID");
}
static int dm_resume(void *handle)
{
struct amdgpu_device *adev = handle;
@ -741,6 +812,7 @@ static int dm_resume(void *handle)
struct drm_plane *plane;
struct drm_plane_state *new_plane_state;
struct dm_plane_state *dm_new_plane_state;
enum dc_connection_type new_connection_type = dc_connection_none;
int ret;
int i;
@ -771,7 +843,13 @@ static int dm_resume(void *handle)
continue;
mutex_lock(&aconnector->hpd_lock);
dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
DRM_ERROR("KMS: Failed to detect connector\n");
if (aconnector->base.force && new_connection_type == dc_connection_none)
emulated_link_detect(aconnector->dc_link);
else
dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
if (aconnector->fake_enable && aconnector->dc_link->local_sink)
aconnector->fake_enable = false;
@ -1020,6 +1098,7 @@ static void handle_hpd_irq(void *param)
struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
struct drm_connector *connector = &aconnector->base;
struct drm_device *dev = connector->dev;
enum dc_connection_type new_connection_type = dc_connection_none;
/*
* In case of failure or MST no need to update connector status or notify the OS
@ -1030,7 +1109,21 @@ static void handle_hpd_irq(void *param)
if (aconnector->fake_enable)
aconnector->fake_enable = false;
if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
DRM_ERROR("KMS: Failed to detect connector\n");
if (aconnector->base.force && new_connection_type == dc_connection_none) {
emulated_link_detect(aconnector->dc_link);
drm_modeset_lock_all(dev);
dm_restore_drm_connector_state(dev, connector);
drm_modeset_unlock_all(dev);
if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
drm_kms_helper_hotplug_event(dev);
} else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
amdgpu_dm_update_connector_after_detect(aconnector);
@ -1130,6 +1223,7 @@ static void handle_hpd_rx_irq(void *param)
struct drm_device *dev = connector->dev;
struct dc_link *dc_link = aconnector->dc_link;
bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
enum dc_connection_type new_connection_type = dc_connection_none;
/*
* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
@ -1142,7 +1236,24 @@ static void handle_hpd_rx_irq(void *param)
if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
!is_mst_root_connector) {
/* Downstream Port status changed. */
if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
if (!dc_link_detect_sink(dc_link, &new_connection_type))
DRM_ERROR("KMS: Failed to detect connector\n");
if (aconnector->base.force && new_connection_type == dc_connection_none) {
emulated_link_detect(dc_link);
if (aconnector->fake_enable)
aconnector->fake_enable = false;
amdgpu_dm_update_connector_after_detect(aconnector);
drm_modeset_lock_all(dev);
dm_restore_drm_connector_state(dev, connector);
drm_modeset_unlock_all(dev);
drm_kms_helper_hotplug_event(dev);
} else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
if (aconnector->fake_enable)
aconnector->fake_enable = false;
@ -1214,7 +1325,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
struct dc_interrupt_params int_params = {0};
int r;
int i;
unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
if (adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA12 ||
@ -1539,6 +1650,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
struct amdgpu_mode_info *mode_info = &adev->mode_info;
uint32_t link_cnt;
int32_t total_overlay_planes, total_primary_planes;
enum dc_connection_type new_connection_type = dc_connection_none;
link_cnt = dm->dc->caps.max_links;
if (amdgpu_dm_mode_config_init(dm->adev)) {
@ -1605,7 +1717,14 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
link = dc_get_link_at_index(dm->dc, i);
if (dc_link_detect(link, DETECT_REASON_BOOT)) {
if (!dc_link_detect_sink(link, &new_connection_type))
DRM_ERROR("KMS: Failed to detect connector\n");
if (aconnector->base.force && new_connection_type == dc_connection_none) {
emulated_link_detect(link);
amdgpu_dm_update_connector_after_detect(aconnector);
} else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
amdgpu_dm_update_connector_after_detect(aconnector);
register_backlight_device(dm, link);
}
@ -2648,7 +2767,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
if (dm_state && dm_state->freesync_capable)
stream->ignore_msa_timing_param = true;
finish:
if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL)
if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL && aconnector->base.force != DRM_FORCE_ON)
dc_sink_release(sink);
return stream;
@ -4079,6 +4198,7 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
/* TODO eliminate or rename surface_update */
struct dc_surface_update surface_updates[1] = { {0} };
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
struct dc_stream_status *stream_status;
/* Prepare wait for target vblank early - before the fence-waits */
@ -4134,7 +4254,19 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
stream_status = dc_stream_get_status(acrtc_state->stream);
if (!stream_status) {
DRM_ERROR("No stream status for CRTC: id=%d\n",
acrtc->crtc_id);
return;
}
surface_updates->surface = stream_status->plane_states[0];
if (!surface_updates->surface) {
DRM_ERROR("No surface for CRTC: id=%d\n",
acrtc->crtc_id);
return;
}
surface_updates->flip_addr = &addr;
dc_commit_updates_for_stream(adev->dm.dc,
@ -4608,12 +4740,18 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
}
spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
/* Signal HW programming completion */
drm_atomic_helper_commit_hw_done(state);
if (wait_for_vblank)
drm_atomic_helper_wait_for_flip_done(dev, state);
/*
* FIXME:
* Delay hw_done() until flip_done() is signaled. This is to block
* another commit from freeing the CRTC state while we're still
* waiting on flip_done.
*/
drm_atomic_helper_commit_hw_done(state);
drm_atomic_helper_cleanup_planes(dev, state);
/*
@ -4797,6 +4935,8 @@ void set_freesync_on_stream(struct amdgpu_display_manager *dm,
mod_freesync_build_vrr_infopacket(dm->freesync_module,
new_stream,
&vrr,
packet_type_fs1,
NULL,
&vrr_infopacket);
new_crtc_state->adjust = vrr.adjust;

2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
View File

@ -108,8 +108,6 @@ struct amdgpu_display_manager {
const struct dc_link *backlight_link;
struct work_struct mst_hotplug_work;
struct mod_freesync *freesync_module;
/**

3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
View File

@ -705,7 +705,8 @@ int connector_debugfs_init(struct amdgpu_dm_connector *connector)
int i;
struct dentry *ent, *dir = connector->base.debugfs_entry;
if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
ent = debugfs_create_file(dp_debugfs_entries[i].name,
0644,

37
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
View File

@ -36,17 +36,13 @@
* Private declarations.
*****************************************************************************/
struct handler_common_data {
struct amdgpu_dm_irq_handler_data {
struct list_head list;
interrupt_handler handler;
void *handler_arg;
/* DM which this handler belongs to */
struct amdgpu_display_manager *dm;
};
struct amdgpu_dm_irq_handler_data {
struct handler_common_data hcd;
/* DAL irq source which registered for this interrupt. */
enum dc_irq_source irq_source;
};
@ -61,7 +57,7 @@ struct amdgpu_dm_irq_handler_data {
* Private functions.
*****************************************************************************/
static void init_handler_common_data(struct handler_common_data *hcd,
static void init_handler_common_data(struct amdgpu_dm_irq_handler_data *hcd,
void (*ih)(void *),
void *args,
struct amdgpu_display_manager *dm)
@ -85,11 +81,9 @@ static void dm_irq_work_func(struct work_struct *work)
struct amdgpu_dm_irq_handler_data *handler_data;
list_for_each(entry, handler_list) {
handler_data =
list_entry(
entry,
struct amdgpu_dm_irq_handler_data,
hcd.list);
handler_data = list_entry(entry,
struct amdgpu_dm_irq_handler_data,
list);
DRM_DEBUG_KMS("DM_IRQ: work_func: for dal_src=%d\n",
handler_data->irq_source);
@ -97,7 +91,7 @@ static void dm_irq_work_func(struct work_struct *work)
DRM_DEBUG_KMS("DM_IRQ: schedule_work: for dal_src=%d\n",
handler_data->irq_source);
handler_data->hcd.handler(handler_data->hcd.handler_arg);
handler_data->handler(handler_data->handler_arg);
}
/* Call a DAL subcomponent which registered for interrupt notification
@ -137,11 +131,11 @@ static struct list_head *remove_irq_handler(struct amdgpu_device *adev,
list_for_each_safe(entry, tmp, hnd_list) {
handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
hcd.list);
list);
if (ih == handler) {
/* Found our handler. Remove it from the list. */
list_del(&handler->hcd.list);
list_del(&handler->list);
handler_removed = true;
break;
}
@ -230,8 +224,7 @@ void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
memset(handler_data, 0, sizeof(*handler_data));
init_handler_common_data(&handler_data->hcd, ih, handler_args,
&adev->dm);
init_handler_common_data(handler_data, ih, handler_args, &adev->dm);
irq_source = int_params->irq_source;
@ -250,7 +243,7 @@ void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
break;
}
list_add_tail(&handler_data->hcd.list, hnd_list);
list_add_tail(&handler_data->list, hnd_list);
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
@ -462,15 +455,13 @@ static void amdgpu_dm_irq_immediate_work(struct amdgpu_device *adev,
entry,
&adev->dm.irq_handler_list_high_tab[irq_source]) {
handler_data =
list_entry(
entry,
struct amdgpu_dm_irq_handler_data,
hcd.list);
handler_data = list_entry(entry,
struct amdgpu_dm_irq_handler_data,
list);
/* Call a subcomponent which registered for immediate
* interrupt notification */
handler_data->hcd.handler(handler_data->hcd.handler_arg);
handler_data->handler(handler_data->handler_arg);
}
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);

2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
View File

@ -105,6 +105,8 @@ bool dm_pp_apply_display_requirements(
adev->powerplay.pp_funcs->display_configuration_change(
adev->powerplay.pp_handle,
&adev->pm.pm_display_cfg);
amdgpu_pm_compute_clocks(adev);
}
return true;

8
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
View File

@ -1625,11 +1625,11 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan
else {
v->dsty_after_scaler = 0.0;
}
v->v_update_offset_pix =dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
v->v_update_offset_pix[k] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk);
v->v_update_width_pix = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k];
v->v_ready_offset_pix =dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sleep + 10.0 / v->dppclk) * v->pixel_clock[k];
v->t_setup = (v->v_update_offset_pix + v->v_update_width_pix + v->v_ready_offset_pix) / v->pixel_clock[k];
v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k];
v->v_ready_offset_pix[k] = dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sleep + 10.0 / v->dppclk) * v->pixel_clock[k];
v->t_setup = (v->v_update_offset_pix[k] + v->v_update_width_pix[k] + v->v_ready_offset_pix[k]) / v->pixel_clock[k];
v->v_startup[k] =dcn_bw_min2(v->v_startup_lines, v->max_vstartup_lines[k]);
if (v->prefetch_mode == 0.0) {
v->t_wait =dcn_bw_max3(v->dram_clock_change_latency + v->urgent_latency, v->sr_enter_plus_exit_time, v->urgent_latency);

12
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
View File

@ -1096,9 +1096,9 @@ bool dcn_validate_bandwidth(
if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
continue;
pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
@ -1137,9 +1137,9 @@ bool dcn_validate_bandwidth(
TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
/* update previously split pipe */
hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;

87
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -60,6 +60,7 @@
#define DC_LOGGER \
dc->ctx->logger
const static char DC_BUILD_ID[] = "production-build";
/*******************************************************************************
* Private functions
@ -460,9 +461,25 @@ void dc_link_set_preferred_link_settings(struct dc *dc,
struct dc_link_settings *link_setting,
struct dc_link *link)
{
int i;
struct pipe_ctx *pipe;
struct dc_stream_state *link_stream;
struct dc_link_settings store_settings = *link_setting;
struct dc_stream_state *link_stream =
link->dc->current_state->res_ctx.pipe_ctx[0].stream;
for (i = 0; i < MAX_PIPES; i++) {
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream && pipe->stream->sink
&& pipe->stream->sink->link) {
if (pipe->stream->sink->link == link)
break;
}
}
/* Stream not found */
if (i == MAX_PIPES)
return;
link_stream = link->dc->current_state->res_ctx.pipe_ctx[i].stream;
link->preferred_link_setting = store_settings;
if (link_stream)
@ -742,6 +759,8 @@ struct dc *dc_create(const struct dc_init_data *init_params)
dc->config = init_params->flags;
dc->build_id = DC_BUILD_ID;
DC_LOG_DC("Display Core initialized\n");
@ -1094,32 +1113,6 @@ static bool is_surface_in_context(
return false;
}
static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
{
switch (format) {
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
return 12;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
return 16;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
return 32;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
return 64;
default:
ASSERT_CRITICAL(false);
return -1;
}
}
static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
{
union surface_update_flags *update_flags = &u->surface->update_flags;
@ -1153,16 +1146,13 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
|| u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch)
update_flags->bits.dcc_change = 1;
if (pixel_format_to_bpp(u->plane_info->format) !=
pixel_format_to_bpp(u->surface->format))
if (resource_pixel_format_to_bpp(u->plane_info->format) !=
resource_pixel_format_to_bpp(u->surface->format))
/* different bytes per element will require full bandwidth
* and DML calculation
*/
update_flags->bits.bpp_change = 1;
if (u->gamma && dce_use_lut(u->plane_info->format))
update_flags->bits.gamma_change = 1;
if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
sizeof(union dc_tiling_info)) != 0) {
update_flags->bits.swizzle_change = 1;
@ -1179,7 +1169,6 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
if (update_flags->bits.rotation_change
|| update_flags->bits.stereo_format_change
|| update_flags->bits.pixel_format_change
|| update_flags->bits.gamma_change
|| update_flags->bits.bpp_change
|| update_flags->bits.bandwidth_change
|| update_flags->bits.output_tf_change)
@ -1269,13 +1258,26 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
if (u->coeff_reduction_factor)
update_flags->bits.coeff_reduction_change = 1;
if (u->gamma) {
enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
if (u->plane_info)
format = u->plane_info->format;
else if (u->surface)
format = u->surface->format;
if (dce_use_lut(format))
update_flags->bits.gamma_change = 1;
}
if (update_flags->bits.in_transfer_func_change) {
type = UPDATE_TYPE_MED;
elevate_update_type(&overall_type, type);
}
if (update_flags->bits.input_csc_change
|| update_flags->bits.coeff_reduction_change) {
|| update_flags->bits.coeff_reduction_change
|| update_flags->bits.gamma_change) {
type = UPDATE_TYPE_FULL;
elevate_update_type(&overall_type, type);
}
@ -1379,7 +1381,7 @@ static void notify_display_count_to_smu(
* sent as part of pplib_apply_display_requirements.
* So just return.
*/
if (!pp_smu->set_display_count)
if (!pp_smu || !pp_smu->set_display_count)
return;
display_count = 0;
@ -1834,3 +1836,16 @@ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
}
}
}
void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
{
info->displayClock = (unsigned int)state->bw.dcn.clk.dispclk_khz;
info->engineClock = (unsigned int)state->bw.dcn.clk.dcfclk_khz;
info->memoryClock = (unsigned int)state->bw.dcn.clk.dramclk_khz;
info->maxSupportedDppClock = (unsigned int)state->bw.dcn.clk.max_supported_dppclk_khz;
info->dppClock = (unsigned int)state->bw.dcn.clk.dppclk_khz;
info->socClock = (unsigned int)state->bw.dcn.clk.socclk_khz;
info->dcfClockDeepSleep = (unsigned int)state->bw.dcn.clk.dcfclk_deep_sleep_khz;
info->fClock = (unsigned int)state->bw.dcn.clk.fclk_khz;
info->phyClock = (unsigned int)state->bw.dcn.clk.phyclk_khz;
}

64
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -198,7 +198,7 @@ static bool program_hpd_filter(
return result;
}
static bool detect_sink(struct dc_link *link, enum dc_connection_type *type)
bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
{
uint32_t is_hpd_high = 0;
struct gpio *hpd_pin;
@ -612,7 +612,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
return false;
if (false == detect_sink(link, &new_connection_type)) {
if (false == dc_link_detect_sink(link, &new_connection_type)) {
BREAK_TO_DEBUGGER();
return false;
}
@ -2559,23 +2559,24 @@ void core_link_enable_stream(
pipe_ctx->stream_res.stream_enc,
&stream->timing);
resource_build_info_frame(pipe_ctx);
core_dc->hwss.update_info_frame(pipe_ctx);
if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
resource_build_info_frame(pipe_ctx);
core_dc->hwss.update_info_frame(pipe_ctx);
/* eDP lit up by bios already, no need to enable again. */
if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
pipe_ctx->stream->apply_edp_fast_boot_optimization) {
pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
pipe_ctx->stream->dpms_off = false;
return;
}
/* eDP lit up by bios already, no need to enable again. */
if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
pipe_ctx->stream->apply_edp_fast_boot_optimization) {
pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
pipe_ctx->stream->dpms_off = false;
return;
}
if (pipe_ctx->stream->dpms_off)
return;
if (pipe_ctx->stream->dpms_off)
return;
status = enable_link(state, pipe_ctx);
status = enable_link(state, pipe_ctx);
if (status != DC_OK) {
if (status != DC_OK) {
DC_LOG_WARNING("enabling link %u failed: %d\n",
pipe_ctx->stream->sink->link->link_index,
status);
@ -2590,23 +2591,26 @@ void core_link_enable_stream(
BREAK_TO_DEBUGGER();
return;
}
}
core_dc->hwss.enable_audio_stream(pipe_ctx);
/* turn off otg test pattern if enable */
if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
COLOR_DEPTH_UNDEFINED);
core_dc->hwss.enable_stream(pipe_ctx);
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
allocate_mst_payload(pipe_ctx);
core_dc->hwss.unblank_stream(pipe_ctx,
&pipe_ctx->stream->sink->link->cur_link_settings);
}
core_dc->hwss.enable_audio_stream(pipe_ctx);
/* turn off otg test pattern if enable */
if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
COLOR_DEPTH_UNDEFINED);
core_dc->hwss.enable_stream(pipe_ctx);
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
allocate_mst_payload(pipe_ctx);
core_dc->hwss.unblank_stream(pipe_ctx,
&pipe_ctx->stream->sink->link->cur_link_settings);
}
void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)

40
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -1975,6 +1975,9 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream)
else
stream->phy_pix_clk =
stream->timing.pix_clk_khz;
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
stream->phy_pix_clk *= 2;
}
enum dc_status resource_map_pool_resources(
@ -2096,6 +2099,14 @@ enum dc_status dc_validate_global_state(
if (pipe_ctx->stream != stream)
continue;
if (dc->res_pool->funcs->get_default_swizzle_mode &&
pipe_ctx->plane_state &&
pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
if (result != DC_OK)
return result;
}
/* Switch to dp clock source only if there is
* no non dp stream that shares the same timing
* with the dp stream.
@ -2885,3 +2896,32 @@ enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *pla
return res;
}
unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
{
switch (format) {
case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
return 8;
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
return 12;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
return 16;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
return 32;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
return 64;
default:
ASSERT_CRITICAL(false);
return -1;
}
}

8
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -38,13 +38,12 @@
#include "inc/compressor.h"
#include "dml/display_mode_lib.h"
#define DC_VER "3.1.66"
#define DC_VER "3.1.68"
#define MAX_SURFACES 3
#define MAX_STREAMS 6
#define MAX_SINKS_PER_LINK 4
/*******************************************************************************
* Display Core Interfaces
******************************************************************************/
@ -208,6 +207,7 @@ struct dc_clocks {
int dcfclk_deep_sleep_khz;
int fclk_khz;
int phyclk_khz;
int dramclk_khz;
};
struct dc_debug_options {
@ -315,6 +315,8 @@ struct dc {
struct compressor *fbc_compressor;
struct dc_debug_data debug_data;
const char *build_id;
};
enum frame_buffer_mode {
@ -599,6 +601,8 @@ struct dc_validation_set {
enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
enum dc_status dc_validate_global_state(
struct dc *dc,
struct dc_state *new_ctx);

3
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
View File

@ -289,7 +289,8 @@ enum swizzle_mode_values {
DC_SW_VAR_S_X = 29,
DC_SW_VAR_D_X = 30,
DC_SW_VAR_R_X = 31,
DC_SW_MAX
DC_SW_MAX = 32,
DC_SW_UNKNOWN = DC_SW_MAX
};
union dc_tiling_info {

1
drivers/gpu/drm/amd/display/dc/dc_link.h
View File

@ -216,6 +216,7 @@ void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
bool dc_link_is_dp_sink_present(struct dc_link *link);
bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type);
/*
* DPCD access interfaces
*/

12
drivers/gpu/drm/amd/display/dc/dc_types.h
View File

@ -659,4 +659,16 @@ enum i2c_mot_mode {
I2C_MOT_FALSE
};
struct AsicStateEx {
unsigned int memoryClock;
unsigned int displayClock;
unsigned int engineClock;
unsigned int maxSupportedDppClock;
unsigned int dppClock;
unsigned int socClock;
unsigned int dcfClockDeepSleep;
unsigned int fClock;
unsigned int phyClock;
};
#endif /* DC_TYPES_H_ */

2
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
View File

@ -312,7 +312,7 @@ static void process_channel_reply(
/* in case HPD is LOW, exit AUX transaction */
if ((sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) {
reply->status = AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON;
reply->status = AUX_TRANSACTION_REPLY_HPD_DISCON;
return;
}

8
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
View File

@ -468,6 +468,9 @@ static void dce12_update_clocks(struct dccg *dccg,
{
struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
/* TODO: Investigate why this is needed to fix display corruption. */
new_clocks->dispclk_khz = new_clocks->dispclk_khz * 115 / 100;
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
clock_voltage_req.clocks_in_khz = new_clocks->dispclk_khz;
@ -661,6 +664,11 @@ static void dce_update_clocks(struct dccg *dccg,
bool safe_to_lower)
{
struct dm_pp_power_level_change_request level_change_req;
struct dce_dccg *clk_dce = TO_DCE_CLOCKS(dccg);
/* TODO: Investigate why this is needed to fix display corruption. */
if (!clk_dce->dfs_bypass_active)
new_clocks->dispclk_khz = new_clocks->dispclk_khz * 115 / 100;
level_change_req.power_level = dce_get_required_clocks_state(dccg, new_clocks);
/* get max clock state from PPLIB */

17
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
View File

@ -662,21 +662,10 @@ bool dce110_link_encoder_validate_dp_output(
const struct dce110_link_encoder *enc110,
const struct dc_crtc_timing *crtc_timing)
{
/* default RGB only */
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
return true;
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
return false;
if (enc110->base.features.flags.bits.IS_YCBCR_CAPABLE)
return true;
/* for DCE 8.x or later DP Y-only feature,
* we need ASIC cap + FeatureSupportDPYonly, not support 666 */
if (crtc_timing->flags.Y_ONLY &&
enc110->base.features.flags.bits.IS_YCBCR_CAPABLE &&
crtc_timing->display_color_depth != COLOR_DEPTH_666)
return true;
return false;
return true;
}
void dce110_link_encoder_construct(

5
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
View File

@ -551,8 +551,7 @@ static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 300000,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
.flags.bits.IS_TPS3_CAPABLE = true
};
struct link_encoder *dce100_link_encoder_create(
@ -690,7 +689,9 @@ static void destruct(struct dce110_resource_pool *pool)
kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {

17
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -1377,26 +1377,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
/* */
dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
/* FPGA does not program backend */
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
pipe_ctx->stream_res.opp,
COLOR_SPACE_YCBCR601,
stream->timing.display_color_depth,
pipe_ctx->stream->signal);
pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
pipe_ctx->stream_res.opp,
&stream->bit_depth_params,
&stream->clamping);
return DC_OK;
}
/* TODO: move to stream encoder */
if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
BREAK_TO_DEBUGGER();
return DC_ERROR_UNEXPECTED;
}
pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
pipe_ctx->stream_res.opp,
COLOR_SPACE_YCBCR601,
@ -2550,7 +2537,7 @@ static void pplib_apply_display_requirements(
dc->prev_display_config = *pp_display_cfg;
}
void dce110_set_bandwidth(
static void dce110_set_bandwidth(
struct dc *dc,
struct dc_state *context,
bool decrease_allowed)

5
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
View File

@ -68,11 +68,6 @@ void dce110_fill_display_configs(
const struct dc_state *context,
struct dm_pp_display_configuration *pp_display_cfg);
void dce110_set_bandwidth(
struct dc *dc,
struct dc_state *context,
bool decrease_allowed);
uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context);
void dp_receiver_power_ctrl(struct dc_link *link, bool on);

5
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
View File

@ -570,8 +570,7 @@ static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 594000,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
.flags.bits.IS_TPS3_CAPABLE = true
};
static struct link_encoder *dce110_link_encoder_create(
@ -720,7 +719,9 @@ static void destruct(struct dce110_resource_pool *pool)
kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {

11
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View File

@ -555,8 +555,7 @@ static const struct encoder_feature_support link_enc_feature = {
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_TPS4_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
.flags.bits.IS_TPS4_CAPABLE = true
};
struct link_encoder *dce112_link_encoder_create(
@ -694,9 +693,6 @@ static void destruct(struct dce110_resource_pool *pool)
if (pool->base.opps[i] != NULL)
dce110_opp_destroy(&pool->base.opps[i]);
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.transforms[i] != NULL)
dce112_transform_destroy(&pool->base.transforms[i]);
@ -712,6 +708,11 @@ static void destruct(struct dce110_resource_pool *pool)
kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
kfree(pool->base.hw_i2cs[i]);
pool->base.hw_i2cs[i] = NULL;

12
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
View File

@ -244,17 +244,6 @@ static void dce120_update_dchub(
dh_data->dchub_info_valid = false;
}
static void dce120_set_bandwidth(
struct dc *dc,
struct dc_state *context,
bool decrease_allowed)
{
if (context->stream_count <= 0)
return;
dce110_set_bandwidth(dc, context, decrease_allowed);
}
void dce120_hw_sequencer_construct(struct dc *dc)
{
/* All registers used by dce11.2 match those in dce11 in offset and
@ -263,6 +252,5 @@ void dce120_hw_sequencer_construct(struct dc *dc)
dce110_hw_sequencer_construct(dc);
dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;
dc->hwss.update_dchub = dce120_update_dchub;
dc->hwss.set_bandwidth = dce120_set_bandwidth;
}

3
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
View File

@ -533,7 +533,9 @@ static void destruct(struct dce110_resource_pool *pool)
kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@ -609,7 +611,6 @@ static const struct encoder_feature_support link_enc_feature = {
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_TPS4_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
};
static struct link_encoder *dce120_link_encoder_create(

5
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
View File

@ -650,8 +650,7 @@ static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 297000,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
.flags.bits.IS_TPS3_CAPABLE = true
};
struct link_encoder *dce80_link_encoder_create(
@ -739,7 +738,9 @@ static void destruct(struct dce110_resource_pool *pool)
kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {

60
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
View File

@ -87,6 +87,23 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
}
void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub)
{
REG_UPDATE(DCHUBBUB_ARB_DRAM_STATE_CNTL,
DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, 0);
}
bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
{
uint32_t enable = 0;
REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL,
DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, &enable);
return true ? false : enable;
}
bool hubbub1_verify_allow_pstate_change_high(
struct hubbub *hubbub)
{
@ -116,7 +133,43 @@ bool hubbub1_verify_allow_pstate_change_high(
forced_pstate_allow = false;
}
/* RV1:
/* RV2:
* dchubbubdebugind, at: 0xB
* description
* 0: Pipe0 Plane0 Allow Pstate Change
* 1: Pipe0 Plane1 Allow Pstate Change
* 2: Pipe0 Cursor0 Allow Pstate Change
* 3: Pipe0 Cursor1 Allow Pstate Change
* 4: Pipe1 Plane0 Allow Pstate Change
* 5: Pipe1 Plane1 Allow Pstate Change
* 6: Pipe1 Cursor0 Allow Pstate Change
* 7: Pipe1 Cursor1 Allow Pstate Change
* 8: Pipe2 Plane0 Allow Pstate Change
* 9: Pipe2 Plane1 Allow Pstate Change
* 10: Pipe2 Cursor0 Allow Pstate Change
* 11: Pipe2 Cursor1 Allow Pstate Change
* 12: Pipe3 Plane0 Allow Pstate Change
* 13: Pipe3 Plane1 Allow Pstate Change
* 14: Pipe3 Cursor0 Allow Pstate Change
* 15: Pipe3 Cursor1 Allow Pstate Change
* 16: Pipe4 Plane0 Allow Pstate Change
* 17: Pipe4 Plane1 Allow Pstate Change
* 18: Pipe4 Cursor0 Allow Pstate Change
* 19: Pipe4 Cursor1 Allow Pstate Change
* 20: Pipe5 Plane0 Allow Pstate Change
* 21: Pipe5 Plane1 Allow Pstate Change
* 22: Pipe5 Cursor0 Allow Pstate Change
* 23: Pipe5 Cursor1 Allow Pstate Change
* 24: Pipe6 Plane0 Allow Pstate Change
* 25: Pipe6 Plane1 Allow Pstate Change
* 26: Pipe6 Cursor0 Allow Pstate Change
* 27: Pipe6 Cursor1 Allow Pstate Change
* 28: WB0 Allow Pstate Change
* 29: WB1 Allow Pstate Change
* 30: Arbiter's allow_pstate_change
* 31: SOC pstate change request"
*
* RV1:
* dchubbubdebugind, at: 0x7
* description "3-0: Pipe0 cursor0 QOS
* 7-4: Pipe1 cursor0 QOS
@ -140,7 +193,6 @@ bool hubbub1_verify_allow_pstate_change_high(
* 31: SOC pstate change request
*/
REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub->debug_test_index_pstate);
for (i = 0; i < pstate_wait_timeout_us; i++) {
@ -802,5 +854,9 @@ void hubbub1_construct(struct hubbub *hubbub,
hubbub->masks = hubbub_mask;
hubbub->debug_test_index_pstate = 0x7;
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
if (ctx->dce_version == DCN_VERSION_1_01)
hubbub->debug_test_index_pstate = 0xB;
#endif
}

4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
View File

@ -203,6 +203,10 @@ void hubbub1_program_watermarks(
unsigned int refclk_mhz,
bool safe_to_lower);
void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub);
bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubub);
void hubbub1_toggle_watermark_change_req(
struct hubbub *hubbub);

15
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -44,6 +44,7 @@
#include "dcn10_hubp.h"
#include "dcn10_hubbub.h"
#include "dcn10_cm_common.h"
#include "dc_link_dp.h"
#define DC_LOGGER_INIT(logger)
@ -996,7 +997,21 @@ static void dcn10_init_hw(struct dc *dc)
} else {
if (!dcb->funcs->is_accelerated_mode(dcb)) {
bool allow_self_fresh_force_enable =
hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub);
bios_golden_init(dc);
/* WA for making DF sleep when idle after resume from S0i3.
* DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
* command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
* before calling command table and it changed to 1 after,
* it should be set back to 0.
*/
if (allow_self_fresh_force_enable == false &&
hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
hubbub1_disable_allow_self_refresh(dc->res_pool->hubbub);
disable_vga(dc->hwseq);
}

18
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
View File

@ -606,22 +606,10 @@ bool dcn10_link_encoder_validate_dp_output(
const struct dcn10_link_encoder *enc10,
const struct dc_crtc_timing *crtc_timing)
{
/* default RGB only */
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
return true;
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
return false;
if (enc10->base.features.flags.bits.IS_YCBCR_CAPABLE)
return true;
/* for DCE 8.x or later DP Y-only feature,
* we need ASIC cap + FeatureSupportDPYonly, not support 666
*/
if (crtc_timing->flags.Y_ONLY &&
enc10->base.features.flags.bits.IS_YCBCR_CAPABLE &&
crtc_timing->display_color_depth != COLOR_DEPTH_666)
return true;
return false;
return true;
}
void dcn10_link_encoder_construct(

34
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
View File

@ -98,7 +98,6 @@ static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_c
struct dc_crtc_timing patched_crtc_timing;
int vesa_sync_start;
int asic_blank_end;
int interlace_factor;
int vertical_line_start;
patched_crtc_timing = *dc_crtc_timing;
@ -112,16 +111,13 @@ static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_c
vesa_sync_start -
patched_crtc_timing.h_border_left;
interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
vesa_sync_start = patched_crtc_timing.v_addressable +
patched_crtc_timing.v_border_bottom +
patched_crtc_timing.v_front_porch;
asic_blank_end = (patched_crtc_timing.v_total -
vesa_sync_start -
patched_crtc_timing.v_border_top)
* interlace_factor;
patched_crtc_timing.v_border_top);
vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
if (vertical_line_start < 0) {
@ -154,7 +150,7 @@ void optc1_program_vline_interrupt(
req_delta_lines--;
if (req_delta_lines > vsync_line)
start_line = dc_crtc_timing->v_total - (req_delta_lines - vsync_line) - 1;
start_line = dc_crtc_timing->v_total - (req_delta_lines - vsync_line) + 2;
else
start_line = vsync_line - req_delta_lines;
@ -186,7 +182,6 @@ void optc1_program_timing(
uint32_t v_sync_end;
uint32_t v_init, v_fp2;
uint32_t h_sync_polarity, v_sync_polarity;
uint32_t interlace_factor;
uint32_t start_point = 0;
uint32_t field_num = 0;
uint32_t h_div_2;
@ -237,16 +232,8 @@ void optc1_program_timing(
REG_UPDATE(OTG_H_SYNC_A_CNTL,
OTG_H_SYNC_A_POL, h_sync_polarity);
/* Load vertical timing */
v_total = patched_crtc_timing.v_total - 1;
/* CRTC_V_TOTAL = v_total - 1 */
if (patched_crtc_timing.flags.INTERLACE) {
interlace_factor = 2;
v_total = 2 * patched_crtc_timing.v_total;
} else {
interlace_factor = 1;
v_total = patched_crtc_timing.v_total - 1;
}
REG_SET(OTG_V_TOTAL, 0,
OTG_V_TOTAL, v_total);
@ -259,7 +246,7 @@ void optc1_program_timing(
OTG_V_TOTAL_MIN, v_total);
/* v_sync_start = 0, v_sync_end = v_sync_width */
v_sync_end = patched_crtc_timing.v_sync_width * interlace_factor;
v_sync_end = patched_crtc_timing.v_sync_width;
REG_UPDATE_2(OTG_V_SYNC_A,
OTG_V_SYNC_A_START, 0,
@ -271,15 +258,13 @@ void optc1_program_timing(
asic_blank_end = (patched_crtc_timing.v_total -
vesa_sync_start -
patched_crtc_timing.v_border_top)
* interlace_factor;
patched_crtc_timing.v_border_top);
/* v_blank_start = v_blank_end + v_active */
asic_blank_start = asic_blank_end +
(patched_crtc_timing.v_border_top +
patched_crtc_timing.v_addressable +
patched_crtc_timing.v_border_bottom)
* interlace_factor;
patched_crtc_timing.v_border_bottom);
REG_UPDATE_2(OTG_V_BLANK_START_END,
OTG_V_BLANK_START, asic_blank_start,
@ -301,7 +286,7 @@ void optc1_program_timing(
0 : 1;
REG_UPDATE(OTG_V_SYNC_A_CNTL,
OTG_V_SYNC_A_POL, v_sync_polarity);
OTG_V_SYNC_A_POL, v_sync_polarity);
v_init = asic_blank_start;
if (optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT ||
@ -532,7 +517,6 @@ bool optc1_validate_timing(
struct timing_generator *optc,
const struct dc_crtc_timing *timing)
{
uint32_t interlace_factor;
uint32_t v_blank;
uint32_t h_blank;
uint32_t min_v_blank;
@ -540,10 +524,8 @@ bool optc1_validate_timing(
ASSERT(timing != NULL);
interlace_factor = timing->flags.INTERLACE ? 2 : 1;
v_blank = (timing->v_total - timing->v_addressable -
timing->v_border_top - timing->v_border_bottom) *
interlace_factor;
timing->v_border_top - timing->v_border_bottom);
h_blank = (timing->h_total - timing->h_addressable -
timing->h_border_right -

45
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View File

@ -507,6 +507,18 @@ static const struct resource_caps res_cap = {
.num_ddc = 4,
};
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
static const struct resource_caps rv2_res_cap = {
.num_timing_generator = 3,
.num_opp = 3,
.num_video_plane = 3,
.num_audio = 3,
.num_stream_encoder = 3,
.num_pll = 3,
.num_ddc = 3,
};
#endif
static const struct dc_debug_options debug_defaults_drv = {
.sanity_checks = true,
.disable_dmcu = true,
@ -711,8 +723,7 @@ static const struct encoder_feature_support link_enc_feature = {
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_TPS4_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
.flags.bits.IS_TPS4_CAPABLE = true
};
struct link_encoder *dcn10_link_encoder_create(
@ -897,7 +908,9 @@ static void destruct(struct dcn10_resource_pool *pool)
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
pool->base.engines[i]->funcs->destroy_engine(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@ -1119,6 +1132,24 @@ static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_st
return DC_OK;
}
static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state)
{
enum dc_status result = DC_OK;
enum surface_pixel_format surf_pix_format = plane_state->format;
unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
enum swizzle_mode_values swizzle = DC_SW_LINEAR;
if (bpp == 64)
swizzle = DC_SW_64KB_D;
else
swizzle = DC_SW_64KB_S;
plane_state->tiling_info.gfx9.swizzle = swizzle;
return result;
}
static const struct dc_cap_funcs cap_funcs = {
.get_dcc_compression_cap = dcn10_get_dcc_compression_cap
};
@ -1129,7 +1160,8 @@ static const struct resource_funcs dcn10_res_pool_funcs = {
.validate_bandwidth = dcn_validate_bandwidth,
.acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
.validate_plane = dcn10_validate_plane,
.add_stream_to_ctx = dcn10_add_stream_to_ctx
.add_stream_to_ctx = dcn10_add_stream_to_ctx,
.get_default_swizzle_mode = dcn10_get_default_swizzle_mode
};
static uint32_t read_pipe_fuses(struct dc_context *ctx)
@ -1152,7 +1184,12 @@ static bool construct(
ctx->dc_bios->regs = &bios_regs;
pool->base.res_cap = &res_cap;
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
if (ctx->dce_version == DCN_VERSION_1_01)
pool->base.res_cap = &rv2_res_cap;
else
#endif
pool->base.res_cap = &res_cap;
pool->base.funcs = &dcn10_res_pool_funcs;
/*

2
drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
View File

@ -346,7 +346,7 @@ static void process_channel_reply(
/* in case HPD is LOW, exit AUX transaction */
if ((sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) {
reply->status = AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON;
reply->status = AUX_TRANSACTION_REPLY_HPD_DISCON;
return;
}

3
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View File

@ -120,6 +120,9 @@ struct resource_funcs {
struct dc *dc,
struct dc_state *new_ctx,
struct dc_stream_state *stream);
enum dc_status (*get_default_swizzle_mode)(
struct dc_plane_state *plane_state);
};
struct audio_support{

6
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
View File

@ -504,10 +504,10 @@ struct dcn_bw_internal_vars {
float prefetch_mode;
float dstx_after_scaler;
float dsty_after_scaler;
float v_update_offset_pix;
float v_update_offset_pix[number_of_planes_minus_one + 1];
float total_repeater_delay_time;
float v_update_width_pix;
float v_ready_offset_pix;
float v_update_width_pix[number_of_planes_minus_one + 1];
float v_ready_offset_pix[number_of_planes_minus_one + 1];
float t_setup;
float t_wait;
float bandwidth_available_for_immediate_flip;

1
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
View File

@ -58,7 +58,6 @@ struct encoder_feature_support {
uint32_t IS_HBR3_CAPABLE:1;
uint32_t IS_TPS3_CAPABLE:1;
uint32_t IS_TPS4_CAPABLE:1;
uint32_t IS_YCBCR_CAPABLE:1;
uint32_t HDMI_6GB_EN:1;
} bits;
uint32_t raw;

3
drivers/gpu/drm/amd/display/dc/inc/resource.h
View File

@ -172,4 +172,7 @@ void update_audio_usage(
const struct resource_pool *pool,
struct audio *audio,
bool acquired);
unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format);
#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */

5
drivers/gpu/drm/amd/display/include/signal_types.h
View File

@ -102,4 +102,9 @@ static inline bool dc_is_audio_capable_signal(enum signal_type signal)
dc_is_hdmi_signal(signal));
}
static inline bool dc_is_virtual_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_VIRTUAL);
}
#endif

8
drivers/gpu/drm/amd/display/modules/color/color_gamma.c
View File

@ -1069,10 +1069,14 @@ static void build_evenly_distributed_points(
struct dividers dividers)
{
struct gamma_pixel *p = points;
struct gamma_pixel *p_last = p + numberof_points - 1;
struct gamma_pixel *p_last;
uint32_t i = 0;
// This function should not gets called with 0 as a parameter
ASSERT(numberof_points > 0);
p_last = p + numberof_points - 1;
do {
struct fixed31_32 value = dc_fixpt_from_fraction(i,
numberof_points - 1);
@ -1083,7 +1087,7 @@ static void build_evenly_distributed_points(
++p;
++i;
} while (i != numberof_points);
} while (i < numberof_points);
p->r = dc_fixpt_div(p_last->r, dividers.divider1);
p->g = dc_fixpt_div(p_last->g, dividers.divider1);

164
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
View File

@ -480,22 +480,11 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
return false;
}
void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
const struct dc_stream_state *stream,
const struct mod_vrr_params *vrr,
struct dc_info_packet *infopacket)
static void build_vrr_infopacket_header_v1(enum signal_type signal,
struct dc_info_packet *infopacket,
unsigned int *payload_size)
{
/* SPD info packet for FreeSync */
unsigned char checksum = 0;
unsigned int idx, payload_size = 0;
/* Check if Freesync is supported. Return if false. If true,
* set the corresponding bit in the info packet
*/
if (!vrr->supported || !vrr->send_vsif)
return;
if (dc_is_hdmi_signal(stream->signal)) {
if (dc_is_hdmi_signal(signal)) {
/* HEADER */
@ -510,9 +499,9 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
/* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
infopacket->hb2 = 0x08;
payload_size = 0x08;
*payload_size = 0x08;
} else if (dc_is_dp_signal(stream->signal)) {
} else if (dc_is_dp_signal(signal)) {
/* HEADER */
@ -536,9 +525,62 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
*/
infopacket->hb3 = 0x04;
payload_size = 0x1B;
*payload_size = 0x1B;
}
}
static void build_vrr_infopacket_header_v2(enum signal_type signal,
struct dc_info_packet *infopacket,
unsigned int *payload_size)
{
if (dc_is_hdmi_signal(signal)) {
/* HEADER */
/* HB0 = Packet Type = 0x83 (Source Product
* Descriptor InfoFrame)
*/
infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
/* HB1 = Version = 0x02 */
infopacket->hb1 = 0x02;
/* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x09] */
infopacket->hb2 = 0x09;
*payload_size = 0x0A;
} else if (dc_is_dp_signal(signal)) {
/* HEADER */
/* HB0 = Secondary-data Packet ID = 0 - Only non-zero
* when used to associate audio related info packets
*/
infopacket->hb0 = 0x00;
/* HB1 = Packet Type = 0x83 (Source Product
* Descriptor InfoFrame)
*/
infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
/* HB2 = [Bits 7:0 = Least significant eight bits -
* For INFOFRAME, the value must be 1Bh]
*/
infopacket->hb2 = 0x1B;
/* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
* [Bits 1:0 = Most significant two bits = 0x00]
*/
infopacket->hb3 = 0x08;
*payload_size = 0x1B;
}
}
static void build_vrr_infopacket_data(const struct mod_vrr_params *vrr,
struct dc_info_packet *infopacket)
{
/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
infopacket->sb[1] = 0x1A;
@ -576,15 +618,39 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
*/
infopacket->sb[8] = (unsigned char)(vrr->max_refresh_in_uhz / 1000000);
/* PB9 - PB27 = Reserved */
//FreeSync HDR
infopacket->sb[9] = 0;
infopacket->sb[10] = 0;
}
static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
struct dc_info_packet *infopacket)
{
if (app_tf != transfer_func_unknown) {
infopacket->valid = true;
infopacket->sb[6] |= 0x08; // PB6 = [Bit 3 = Native Color Active]
if (app_tf == transfer_func_gamma_22) {
infopacket->sb[9] |= 0x04; // PB6 = [Bit 2 = Gamma 2.2 EOTF Active]
}
}
}
static void build_vrr_infopacket_checksum(unsigned int *payload_size,
struct dc_info_packet *infopacket)
{
/* Calculate checksum */
unsigned int idx = 0;
unsigned char checksum = 0;
checksum += infopacket->hb0;
checksum += infopacket->hb1;
checksum += infopacket->hb2;
checksum += infopacket->hb3;
for (idx = 1; idx <= payload_size; idx++)
for (idx = 1; idx <= *payload_size; idx++)
checksum += infopacket->sb[idx];
/* PB0 = Checksum (one byte complement) */
@ -593,6 +659,64 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
infopacket->valid = true;
}
static void build_vrr_infopacket_v1(enum signal_type signal,
const struct mod_vrr_params *vrr,
struct dc_info_packet *infopacket)
{
/* SPD info packet for FreeSync */
unsigned int payload_size = 0;
build_vrr_infopacket_header_v1(signal, infopacket, &payload_size);
build_vrr_infopacket_data(vrr, infopacket);
build_vrr_infopacket_checksum(&payload_size, infopacket);
infopacket->valid = true;
}
static void build_vrr_infopacket_v2(enum signal_type signal,
const struct mod_vrr_params *vrr,
const enum color_transfer_func *app_tf,
struct dc_info_packet *infopacket)
{
unsigned int payload_size = 0;
build_vrr_infopacket_header_v2(signal, infopacket, &payload_size);
build_vrr_infopacket_data(vrr, infopacket);
if (app_tf != NULL)
build_vrr_infopacket_fs2_data(*app_tf, infopacket);
build_vrr_infopacket_checksum(&payload_size, infopacket);
infopacket->valid = true;
}
void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
const struct dc_stream_state *stream,
const struct mod_vrr_params *vrr,
enum vrr_packet_type packet_type,
const enum color_transfer_func *app_tf,
struct dc_info_packet *infopacket)
{
/* SPD info packet for FreeSync */
/* Check if Freesync is supported. Return if false. If true,
* set the corresponding bit in the info packet
*/
if (!vrr->supported || !vrr->send_vsif)
return;
switch (packet_type) {
case packet_type_fs2:
build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket);
break;
case packet_type_vrr:
case packet_type_fs1:
default:
build_vrr_infopacket_v1(stream->signal, vrr, infopacket);
}
}
void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
const struct dc_stream_state *stream,
struct mod_freesync_config *in_config,

4
drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
View File

@ -54,7 +54,7 @@
#ifndef MOD_FREESYNC_H_
#define MOD_FREESYNC_H_
#include "dm_services.h"
#include "mod_shared.h"
// Access structures
struct mod_freesync {
@ -144,6 +144,8 @@ void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
const struct dc_stream_state *stream,
const struct mod_vrr_params *vrr,
enum vrr_packet_type packet_type,
const enum color_transfer_func *app_tf,
struct dc_info_packet *infopacket);
void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,

49
drivers/gpu/drm/amd/display/modules/inc/mod_shared.h Normal file
View File

@ -0,0 +1,49 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef MOD_SHARED_H_
#define MOD_SHARED_H_
enum color_transfer_func {
transfer_func_unknown,
transfer_func_srgb,
transfer_func_bt709,
transfer_func_pq2084,
transfer_func_pq2084_interim,
transfer_func_linear_0_1,
transfer_func_linear_0_125,
transfer_func_dolbyvision,
transfer_func_gamma_22,
transfer_func_gamma_26
};
enum vrr_packet_type {
packet_type_vrr,
packet_type_fs1,
packet_type_fs2
};
#endif /* MOD_SHARED_H_ */

58
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
View File

@ -48,9 +48,12 @@ static void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
unsigned int i;
unsigned int pixelEncoding = 0;
unsigned int colorimetryFormat = 0;
bool stereo3dSupport = false;
if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE)
if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) {
vscPacketRevision = 1;
stereo3dSupport = true;
}
/*VSC packet set to 2 when DP revision >= 1.2*/
if (stream->psr_version != 0)
@ -94,12 +97,59 @@ static void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
info_packet->hb2 = 0x01; // 01h = Revision number. VSC SDP supporting 3D stereo only
info_packet->hb3 = 0x01; // 01h = VSC SDP supporting 3D stereo only (HB2 = 01h).
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_INBAND_FA)
info_packet->sb[0] = 0x1;
info_packet->valid = true;
}
if (stereo3dSupport) {
/* ==============================================================================================================|
* A. STEREO 3D
* ==============================================================================================================|
* VSC Payload (1 byte) From DP1.2 spec
*
* Bits 3:0 (Stereo Interface Method Code) | Bits 7:4 (Stereo Interface Method Specific Parameter)
* -----------------------------------------------------------------------------------------------------
* 0 = Non Stereo Video | Must be set to 0x0
* -----------------------------------------------------------------------------------------------------
* 1 = Frame/Field Sequential | 0x0: L + R view indication based on MISC1 bit 2:1
* | 0x1: Right when Stereo Signal = 1
* | 0x2: Left when Stereo Signal = 1
* | (others reserved)
* -----------------------------------------------------------------------------------------------------
* 2 = Stacked Frame | 0x0: Left view is on top and right view on bottom
* | (others reserved)
* -----------------------------------------------------------------------------------------------------
* 3 = Pixel Interleaved | 0x0: horiz interleaved, right view pixels on even lines
* | 0x1: horiz interleaved, right view pixels on odd lines
* | 0x2: checker board, start with left view pixel
* | 0x3: vertical interleaved, start with left view pixels
* | 0x4: vertical interleaved, start with right view pixels
* | (others reserved)
* -----------------------------------------------------------------------------------------------------
* 4 = Side-by-side | 0x0: left half represents left eye view
* | 0x1: left half represents right eye view
*/
switch (stream->timing.timing_3d_format) {
case TIMING_3D_FORMAT_HW_FRAME_PACKING:
case TIMING_3D_FORMAT_SW_FRAME_PACKING:
case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
case TIMING_3D_FORMAT_TB_SW_PACKED:
info_packet->sb[0] = 0x02; // Stacked Frame, Left view is on top and right view on bottom.
break;
case TIMING_3D_FORMAT_DP_HDMI_INBAND_FA:
case TIMING_3D_FORMAT_INBAND_FA:
info_packet->sb[0] = 0x01; // Frame/Field Sequential, L + R view indication based on MISC1 bit 2:1
break;
case TIMING_3D_FORMAT_SIDE_BY_SIDE:
case TIMING_3D_FORMAT_SBS_SW_PACKED:
info_packet->sb[0] = 0x04; // Side-by-side
break;
default:
info_packet->sb[0] = 0x00; // No Stereo Video, Shall be cleared to 0x0.
break;
}
}
/* 05h = VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/Colorimetry Format indication.
* Added in DP1.3, a DP Source device is allowed to indicate the pixel encoding/colorimetry
* format to the DP Sink device with VSC SDP only when the DP Sink device supports it

8
drivers/gpu/drm/amd/display/modules/stats/stats.c
View File

@ -186,12 +186,8 @@ void mod_stats_destroy(struct mod_stats *mod_stats)
if (mod_stats != NULL) {
struct core_stats *core_stats = MOD_STATS_TO_CORE(mod_stats);
if (core_stats->time != NULL)
kfree(core_stats->time);
if (core_stats->events != NULL)
kfree(core_stats->events);
kfree(core_stats->time);
kfree(core_stats->events);
kfree(core_stats);
}
}