drm/amdgpu: update pd shadow while updating pd V2
V2: Checking if shadow is valid. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -816,6 +816,7 @@ struct amdgpu_ring {
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struct amdgpu_vm_pt {
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struct amdgpu_vm_pt {
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struct amdgpu_bo_list_entry entry;
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struct amdgpu_bo_list_entry entry;
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uint64_t addr;
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uint64_t addr;
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uint64_t shadow_addr;
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};
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};
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struct amdgpu_vm {
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struct amdgpu_vm {
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@ -604,24 +604,14 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
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return result;
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return result;
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}
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}
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/**
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static int amdgpu_vm_update_pd_or_shadow(struct amdgpu_device *adev,
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* amdgpu_vm_update_pdes - make sure that page directory is valid
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struct amdgpu_vm *vm,
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*
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bool shadow)
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* @adev: amdgpu_device pointer
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* @vm: requested vm
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* @start: start of GPU address range
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* @end: end of GPU address range
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*
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* Allocates new page tables if necessary
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* and updates the page directory.
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* Returns 0 for success, error for failure.
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*/
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int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
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struct amdgpu_vm *vm)
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{
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{
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struct amdgpu_ring *ring;
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struct amdgpu_ring *ring;
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struct amdgpu_bo *pd = vm->page_directory;
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struct amdgpu_bo *pd = shadow ? vm->page_directory->shadow :
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uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
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vm->page_directory;
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uint64_t pd_addr;
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uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
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uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
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uint64_t last_pde = ~0, last_pt = ~0;
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uint64_t last_pde = ~0, last_pt = ~0;
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unsigned count = 0, pt_idx, ndw;
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unsigned count = 0, pt_idx, ndw;
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@ -631,6 +621,9 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
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int r;
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int r;
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if (!pd)
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return 0;
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pd_addr = amdgpu_bo_gpu_offset(pd);
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ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
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ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
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/* padding, etc. */
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/* padding, etc. */
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@ -656,9 +649,15 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
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continue;
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continue;
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pt = amdgpu_bo_gpu_offset(bo);
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pt = amdgpu_bo_gpu_offset(bo);
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if (vm->page_tables[pt_idx].addr == pt)
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if (!shadow) {
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continue;
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if (vm->page_tables[pt_idx].addr == pt)
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vm->page_tables[pt_idx].addr = pt;
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continue;
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vm->page_tables[pt_idx].addr = pt;
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} else {
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if (vm->page_tables[pt_idx].shadow_addr == pt)
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continue;
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vm->page_tables[pt_idx].shadow_addr = pt;
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}
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pde = pd_addr + pt_idx * 8;
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pde = pd_addr + pt_idx * 8;
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if (((last_pde + 8 * count) != pde) ||
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if (((last_pde + 8 * count) != pde) ||
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@ -709,6 +708,29 @@ error_free:
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return r;
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return r;
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}
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}
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/*
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* amdgpu_vm_update_pdes - make sure that page directory is valid
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*
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* @adev: amdgpu_device pointer
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* @vm: requested vm
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* @start: start of GPU address range
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* @end: end of GPU address range
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*
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* Allocates new page tables if necessary
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* and updates the page directory.
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* Returns 0 for success, error for failure.
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*/
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int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
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struct amdgpu_vm *vm)
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{
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int r;
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r = amdgpu_vm_update_pd_or_shadow(adev, vm, true);
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if (r)
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return r;
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return amdgpu_vm_update_pd_or_shadow(adev, vm, false);
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}
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/**
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/**
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* amdgpu_vm_update_ptes - make sure that page tables are valid
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* amdgpu_vm_update_ptes - make sure that page tables are valid
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*
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*
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