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drm/i915: Extend Wa_14015795083 platforms

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This workaround was already implemented for DG2, PVC, and some steppings
of MTL, but the workaround database has now been updated to extend this
workaround to TGL, RKL, DG1, and ADL.

v2:
 - Skip readback verification for these extra gen12lp platforms.  On
   some of the platforms, the firmware locks this register, preventing
   the driver from making any modifications.  We should still try to
   apply the workaround, but if the register is locked and the value
   doesn't stick, that's semi-expected and not something we want to flag
   as a driver error on debug builds.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230616225041.3922719-1-matthew.d.roper@intel.com
This commit is contained in:
Matt Roper 2023-06-16 15:50:41 -07:00
parent 668f37e1ee
commit 6580176fd0
1 changed files with 12 additions and 0 deletions
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12
drivers/gpu/drm/i915/gt/intel_workarounds.c
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@ -1485,6 +1485,18 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
/*
* Wa_14015795083
*
* Firmware on some gen12 platforms locks the MISCCPCTL register,
* preventing i915 from modifying it for this workaround. Skip the
* readback verification for this workaround on debug builds; if the
* workaround doesn't stick due to firmware behavior, it's not an error
* that we want CI to flag.
*/
wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,
0, 0, false);
}
static void