iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize

Browse Source 
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
be delayed 100ms (TPVPERL) for the power and clock to become stable.

Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Pali Rohár <pali@kernel.org>
This commit is contained in:
qizhong cheng 2021-12-27 21:31:10 +08:00 committed by Lorenzo Pieralisi
parent fa55b7dcdc
commit 65ace9a85f
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/pci/controller/pcie-mediatek.c
View File

@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
*/
writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
/*
* Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
* 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
* be delayed 100ms (TPVPERL) for the power and clock to become stable.
*/
msleep(100);
/* De-assert PHY, PE, PIPE, MAC and configuration reset */
val = readl(port->base + PCIE_RST_CTRL);
val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |