dt-bindings: timer: Convert Exynos MCT bindings to json-schema
Convert Samsung Exynos Soc Multi Core Timer bindings to DT schema format using json-schema. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
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Krzysztof Kozlowski
Rob Herring
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b204731689
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65eba0db22
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Samsung's Multi Core Timer (MCT)
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The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
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global timer and CPU local timers. The global timer is a 64-bit free running
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up-counter and can generate 4 interrupts when the counter reaches one of the
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four preset counter values. The CPU local timers are 32-bit free running
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down-counters and generate an interrupt when the counter expires. There is
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one CPU local timer instantiated in MCT for every CPU in the system.
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Required properties:
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- compatible: should be "samsung,exynos4210-mct".
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(a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
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(b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
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- reg: base address of the mct controller and length of the address space
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it occupies.
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- interrupts: the list of interrupts generated by the controller. The following
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should be the order of the interrupts specified. The local timer interrupts
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should be specified after the four global timer interrupts have been
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specified.
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0: Global Timer Interrupt 0
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1: Global Timer Interrupt 1
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2: Global Timer Interrupt 2
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3: Global Timer Interrupt 3
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4: Local Timer Interrupt 0
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5: Local Timer Interrupt 1
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6: ..
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7: ..
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i: Local Timer Interrupt n
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For MCT block that uses a per-processor interrupt for local timers, such
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as ones compatible with "samsung,exynos4412-mct", only one local timer
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interrupt might be specified, meaning that all local timers use the same
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per processor interrupt.
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Example 1: In this example, the IP contains two local timers, using separate
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interrupts, so two local timer interrupts have been specified,
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in addition to four global timer interrupts.
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mct@10050000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x10050000 0x800>;
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interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
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<0 42 0>, <0 48 0>;
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};
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Example 2: In this example, the timer interrupts are connected to two separate
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interrupt controllers. Hence, an interrupt-map is created to map
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the interrupts to the respective interrupt controllers.
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mct@101c0000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x101C0000 0x800>;
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interrupt-parent = <&mct_map>;
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interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
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mct_map: mct-map {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <0 &gic 0 57 0>,
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<1 &gic 0 69 0>,
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<2 &combiner 12 6>,
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<3 &combiner 12 7>,
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<4 &gic 0 42 0>,
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<5 &gic 0 48 0>;
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};
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};
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Example 3: In this example, the IP contains four local timers, but using
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a per-processor interrupt to handle them. Either all the local
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timer interrupts can be specified, with the same interrupt specifier
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value or just the first one.
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mct@10050000 {
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compatible = "samsung,exynos4412-mct";
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reg = <0x10050000 0x800>;
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/* Both ways are possible in this case. Either: */
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interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
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<0 42 0>;
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/* or: */
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interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
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<0 42 0>, <0 42 0>, <0 42 0>, <0 42 0>;
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};
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@ -0,0 +1,107 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos SoC Multi Core Timer (MCT)
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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description: |+
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The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
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global timer and CPU local timers. The global timer is a 64-bit free running
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up-counter and can generate 4 interrupts when the counter reaches one of the
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four preset counter values. The CPU local timers are 32-bit free running
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down-counters and generate an interrupt when the counter expires. There is
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one CPU local timer instantiated in MCT for every CPU in the system.
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properties:
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compatible:
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enum:
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- samsung,exynos4210-mct
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- samsung,exynos4412-mct
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reg:
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maxItems: 1
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interrupts:
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description: |
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Interrupts should be put in specific order. This is, the local timer
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interrupts should be specified after the four global timer interrupts
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have been specified:
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0: Global Timer Interrupt 0
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1: Global Timer Interrupt 1
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2: Global Timer Interrupt 2
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3: Global Timer Interrupt 3
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4: Local Timer Interrupt 0
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5: Local Timer Interrupt 1
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6: ..
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7: ..
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i: Local Timer Interrupt n
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For MCT block that uses a per-processor interrupt for local timers, such
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as ones compatible with "samsung,exynos4412-mct", only one local timer
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interrupt might be specified, meaning that all local timers use the same
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per processor interrupt.
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minItems: 5 # 4 Global + 1 local
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maxItems: 20 # 4 Global + 16 local
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required:
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- compatible
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- interrupts
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- reg
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examples:
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- |
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// In this example, the IP contains two local timers, using separate
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// interrupts, so two local timer interrupts have been specified,
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// in addition to four global timer interrupts.
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timer@10050000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x10050000 0x800>;
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interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
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<0 42 0>, <0 48 0>;
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};
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- |
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// In this example, the timer interrupts are connected to two separate
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// interrupt controllers. Hence, an interrupts-extended is needed.
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timer@101c0000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x101C0000 0x800>;
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interrupts-extended = <&gic 0 57 0>,
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<&gic 0 69 0>,
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<&combiner 12 6>,
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<&combiner 12 7>,
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<&gic 0 42 0>,
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<&gic 0 48 0>;
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};
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- |
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// In this example, the IP contains four local timers, but using
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// a per-processor interrupt to handle them. Only one first local
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// interrupt is specified.
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timer@10050000 {
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compatible = "samsung,exynos4412-mct";
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reg = <0x10050000 0x800>;
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interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
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<0 42 0>;
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};
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- |
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// In this example, the IP contains four local timers, but using
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// a per-processor interrupt to handle them. All the local timer
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// interrupts are specified.
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timer@10050000 {
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compatible = "samsung,exynos4412-mct";
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reg = <0x10050000 0x800>;
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interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
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<0 42 0>, <0 42 0>, <0 42 0>, <0 42 0>;
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};
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