clk: qcom: gcc-sm6115: Move alpha pll bramo overrides
sm6115 uses a modified default and bramo alpha pll offsets. Put them in the same place for consistency. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220830075620.974009-3-iskren.chernev@gmail.com
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@ -65,6 +65,16 @@ static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
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[PLL_OFF_CONFIG_CTL] = 0x20,
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[PLL_OFF_STATUS] = 0x24,
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},
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[CLK_ALPHA_PLL_TYPE_BRAMMO] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_ALPHA_VAL_U] = 0x0c,
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[PLL_OFF_TEST_CTL] = 0x10,
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[PLL_OFF_TEST_CTL_U] = 0x14,
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[PLL_OFF_USER_CTL] = 0x18,
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[PLL_OFF_CONFIG_CTL] = 0x1C,
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[PLL_OFF_STATUS] = 0x20,
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},
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};
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static struct clk_alpha_pll gpll0 = {
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@ -106,18 +116,6 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
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},
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};
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/* listed as BRAMMO, but it doesn't really match */
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static const u8 clk_gpll9_regs[PLL_OFF_MAX_REGS] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_ALPHA_VAL_U] = 0x0c,
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[PLL_OFF_TEST_CTL] = 0x10,
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[PLL_OFF_TEST_CTL_U] = 0x14,
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[PLL_OFF_USER_CTL] = 0x18,
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[PLL_OFF_CONFIG_CTL] = 0x1C,
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[PLL_OFF_STATUS] = 0x20,
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};
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static const struct clk_div_table post_div_table_gpll0_out_main[] = {
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{ 0x0, 1 },
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{ }
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@ -445,7 +443,7 @@ static struct clk_alpha_pll gpll9 = {
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.offset = 0x9000,
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.vco_table = gpll9_vco,
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.num_vco = ARRAY_SIZE(gpll9_vco),
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.regs = clk_gpll9_regs,
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO],
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.clkr = {
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.enable_reg = 0x79000,
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.enable_mask = BIT(9),
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@ -471,7 +469,7 @@ static struct clk_alpha_pll_postdiv gpll9_out_main = {
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.post_div_table = post_div_table_gpll9_out_main,
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.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
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.width = 2,
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.regs = clk_gpll9_regs,
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll9_out_main",
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.parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },
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