iwlwifi: pcie: implement set_pnvm op
Implement the set_pnvm op to store the PNVM settings to the context info and the corresponding code to free the DRAM block when the context is freed. Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/iwlwifi.20201008181047.85847cfb0972.I202d90e99779f722df14b2d4102d3e466343a6f6@changeid
This commit is contained in:
Luca Coelho
Kalle Valo
parent
a182dfab28
commit
6654cd4eb9
@ -291,4 +291,7 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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const struct fw_img *fw);
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void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans);
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int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
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const void *data, u32 len);
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#endif /* __iwl_context_info_file_gen3_h__ */
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@ -6,7 +6,7 @@
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 - 2019 Intel Corporation
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* Copyright(c) 2018 - 2020 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@ -20,7 +20,7 @@
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* BSD LICENSE
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 - 2019 Intel Corporation
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* Copyright(c) 2018 - 2020 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -225,5 +225,8 @@ void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans);
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int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
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const struct fw_img *fw,
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struct iwl_context_info_dram *ctxt_dram);
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int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
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const void *data, u32 len,
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struct iwl_dram_data *dram);
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#endif /* __iwl_context_info_file_h__ */
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@ -300,4 +300,37 @@ void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans)
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trans_pcie->prph_info_dma_addr);
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trans_pcie->prph_info_dma_addr = 0;
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trans_pcie->prph_info = NULL;
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dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size,
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trans_pcie->pnvm_dram.block,
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trans_pcie->pnvm_dram.physical);
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trans_pcie->pnvm_dram.size = 0;
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trans_pcie->pnvm_dram.block = NULL;
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trans_pcie->pnvm_dram.physical = 0;
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}
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int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
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const void *data, u32 len)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
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&trans_pcie->prph_scratch->ctrl_cfg;
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int ret;
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if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
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return 0;
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ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len,
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&trans_pcie->pnvm_dram);
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if (ret < 0) {
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IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n",
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ret);
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return ret;
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}
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prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
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cpu_to_le64(trans_pcie->pnvm_dram.physical);
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prph_sc_ctrl->pnvm_cfg.pnvm_size =
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cpu_to_le32(trans_pcie->pnvm_dram.size);
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return 0;
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}
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@ -93,17 +93,17 @@ static void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
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return _iwl_pcie_ctxt_info_dma_alloc_coherent(trans, size, phys, 0);
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}
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static int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
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const struct fw_desc *sec,
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struct iwl_dram_data *dram)
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int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
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const void *data, u32 len,
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struct iwl_dram_data *dram)
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{
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dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, sec->len,
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dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len,
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&dram->physical);
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if (!dram->block)
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return -ENOMEM;
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dram->size = sec->len;
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memcpy(dram->block, sec->data, sec->len);
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dram->size = len;
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memcpy(dram->block, data, len);
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return 0;
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}
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@ -156,7 +156,8 @@ int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
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/* initialize lmac sections */
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for (i = 0; i < lmac_cnt; i++) {
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ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[i],
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ret = iwl_pcie_ctxt_info_alloc_dma(trans, fw->sec[i].data,
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fw->sec[i].len,
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&dram->fw[dram->fw_cnt]);
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if (ret)
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return ret;
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@ -169,7 +170,8 @@ int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
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for (i = 0; i < umac_cnt; i++) {
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/* access FW with +1 to make up for lmac separator */
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ret = iwl_pcie_ctxt_info_alloc_dma(trans,
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&fw->sec[dram->fw_cnt + 1],
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fw->sec[dram->fw_cnt + 1].data,
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fw->sec[dram->fw_cnt + 1].len,
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&dram->fw[dram->fw_cnt]);
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if (ret)
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return ret;
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@ -192,7 +194,8 @@ int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
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/* access FW with +2 to make up for lmac & umac separators */
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int fw_idx = dram->fw_cnt + i + 2;
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ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[fw_idx],
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ret = iwl_pcie_ctxt_info_alloc_dma(trans, fw->sec[fw_idx].data,
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fw->sec[fw_idx].len,
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&dram->paging[i]);
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if (ret)
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return ret;
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@ -339,6 +339,7 @@ struct cont_rec {
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* @trans: pointer to the generic transport area
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* @scd_base_addr: scheduler sram base address in SRAM
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* @kw: keep warm address
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* @pnvm_dram: DRAM area that contains the PNVM data
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* @pci_dev: basic pci-network driver stuff
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* @hw_base: pci hardware address support
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* @ucode_write_complete: indicates that the ucode has been copied.
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@ -410,6 +411,8 @@ struct iwl_trans_pcie {
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u32 scd_base_addr;
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struct iwl_dma_ptr kw;
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struct iwl_dram_data pnvm_dram;
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struct iwl_txq *txq_memory;
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/* PCI bus related data */
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@ -81,6 +81,7 @@
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#include "fw/api/tx.h"
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#include "internal.h"
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#include "iwl-fh.h"
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#include "iwl-context-info-gen3.h"
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/* extended range in FW SRAM */
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#define IWL_FW_MEM_EXTENDED_START 0x40000
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@ -3451,6 +3452,7 @@ static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
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.txq_free = iwl_txq_dyn_free,
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.wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
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.rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
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.set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
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#ifdef CONFIG_IWLWIFI_DEBUGFS
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.debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
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#endif
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