RDMA/mlx5: Refactor mlx5_post_send() to improve readability
Add small helpers in order to avoid code duplication and improve code readability. Decrease the amount of code in the gigantic post_send function and divide it to readable methods that will help in code maintenance in the future. Link: https://lore.kernel.org/r/20200506065513.4668-3-leon@kernel.org Signed-off-by: Max Gurtovoy <maxg@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Max Gurtovoy
Jason Gunthorpe
parent
31578defe4
commit
6671cde83d
@ -5234,18 +5234,279 @@ static void finish_wqe(struct mlx5_ib_qp *qp,
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cur_edge;
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}
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static void handle_rdma_op(const struct ib_send_wr *wr, void **seg, int *size)
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{
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set_raddr_seg(*seg, rdma_wr(wr)->remote_addr, rdma_wr(wr)->rkey);
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*seg += sizeof(struct mlx5_wqe_raddr_seg);
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*size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
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}
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static void handle_local_inv(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
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struct mlx5_wqe_ctrl_seg **ctrl, void **seg,
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int *size, void **cur_edge, unsigned int idx)
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{
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qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
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(*ctrl)->imm = cpu_to_be32(wr->ex.invalidate_rkey);
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set_linv_wr(qp, seg, size, cur_edge);
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}
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static int handle_reg_mr(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
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struct mlx5_wqe_ctrl_seg **ctrl, void **seg, int *size,
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void **cur_edge, unsigned int idx)
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{
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qp->sq.wr_data[idx] = IB_WR_REG_MR;
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(*ctrl)->imm = cpu_to_be32(reg_wr(wr)->key);
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return set_reg_wr(qp, reg_wr(wr), seg, size, cur_edge, true);
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}
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static int handle_psv(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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const struct ib_send_wr *wr,
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struct mlx5_wqe_ctrl_seg **ctrl, void **seg, int *size,
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void **cur_edge, unsigned int *idx, int nreq,
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struct ib_sig_domain *domain, u32 psv_index,
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u8 next_fence)
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{
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int err;
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/*
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* SET_PSV WQEs are not signaled and solicited on error.
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*/
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err = __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
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false, true);
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if (unlikely(err)) {
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mlx5_ib_warn(dev, "\n");
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err = -ENOMEM;
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goto out;
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}
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err = set_psv_wr(domain, psv_index, seg, size);
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if (unlikely(err)) {
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mlx5_ib_warn(dev, "\n");
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goto out;
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}
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finish_wqe(qp, *ctrl, *seg, *size, *cur_edge, *idx, wr->wr_id, nreq,
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next_fence, MLX5_OPCODE_SET_PSV);
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out:
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return err;
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}
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static int handle_reg_mr_integrity(struct mlx5_ib_dev *dev,
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struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
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struct mlx5_wqe_ctrl_seg **ctrl, void **seg, int *size,
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void **cur_edge, unsigned int *idx, int nreq, u8 fence,
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u8 next_fence)
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{
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struct mlx5_ib_mr *mr;
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struct mlx5_ib_mr *pi_mr;
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struct mlx5_ib_mr pa_pi_mr;
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struct ib_sig_attrs *sig_attrs;
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struct ib_reg_wr reg_pi_wr;
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int err;
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qp->sq.wr_data[*idx] = IB_WR_REG_MR_INTEGRITY;
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mr = to_mmr(reg_wr(wr)->mr);
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pi_mr = mr->pi_mr;
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if (pi_mr) {
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memset(®_pi_wr, 0,
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sizeof(struct ib_reg_wr));
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reg_pi_wr.mr = &pi_mr->ibmr;
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reg_pi_wr.access = reg_wr(wr)->access;
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reg_pi_wr.key = pi_mr->ibmr.rkey;
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(*ctrl)->imm = cpu_to_be32(reg_pi_wr.key);
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/* UMR for data + prot registration */
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err = set_reg_wr(qp, ®_pi_wr, seg, size, cur_edge, false);
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if (unlikely(err))
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goto out;
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finish_wqe(qp, *ctrl, *seg, *size, *cur_edge, *idx, wr->wr_id,
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nreq, fence, MLX5_OPCODE_UMR);
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err = begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq);
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if (unlikely(err)) {
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mlx5_ib_warn(dev, "\n");
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err = -ENOMEM;
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goto out;
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}
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} else {
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memset(&pa_pi_mr, 0, sizeof(struct mlx5_ib_mr));
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/* No UMR, use local_dma_lkey */
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pa_pi_mr.ibmr.lkey = mr->ibmr.pd->local_dma_lkey;
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pa_pi_mr.ndescs = mr->ndescs;
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pa_pi_mr.data_length = mr->data_length;
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pa_pi_mr.data_iova = mr->data_iova;
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if (mr->meta_ndescs) {
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pa_pi_mr.meta_ndescs = mr->meta_ndescs;
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pa_pi_mr.meta_length = mr->meta_length;
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pa_pi_mr.pi_iova = mr->pi_iova;
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}
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pa_pi_mr.ibmr.length = mr->ibmr.length;
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mr->pi_mr = &pa_pi_mr;
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}
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(*ctrl)->imm = cpu_to_be32(mr->ibmr.rkey);
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/* UMR for sig MR */
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err = set_pi_umr_wr(wr, qp, seg, size, cur_edge);
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if (unlikely(err)) {
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mlx5_ib_warn(dev, "\n");
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goto out;
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}
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finish_wqe(qp, *ctrl, *seg, *size, *cur_edge, *idx, wr->wr_id, nreq,
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fence, MLX5_OPCODE_UMR);
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sig_attrs = mr->ibmr.sig_attrs;
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err = handle_psv(dev, qp, wr, ctrl, seg, size, cur_edge, idx, nreq,
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&sig_attrs->mem, mr->sig->psv_memory.psv_idx,
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next_fence);
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if (unlikely(err))
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goto out;
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err = handle_psv(dev, qp, wr, ctrl, seg, size, cur_edge, idx, nreq,
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&sig_attrs->wire, mr->sig->psv_wire.psv_idx,
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next_fence);
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if (unlikely(err))
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goto out;
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qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
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out:
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return err;
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}
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static int handle_qpt_rc(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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const struct ib_send_wr *wr,
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struct mlx5_wqe_ctrl_seg **ctrl, void **seg, int *size,
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void **cur_edge, unsigned int *idx, int nreq, u8 fence,
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u8 next_fence, int *num_sge)
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{
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int err = 0;
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switch (wr->opcode) {
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case IB_WR_RDMA_READ:
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case IB_WR_RDMA_WRITE:
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case IB_WR_RDMA_WRITE_WITH_IMM:
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handle_rdma_op(wr, seg, size);
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break;
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case IB_WR_ATOMIC_CMP_AND_SWP:
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case IB_WR_ATOMIC_FETCH_AND_ADD:
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case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
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mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
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err = -EOPNOTSUPP;
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goto out;
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case IB_WR_LOCAL_INV:
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handle_local_inv(qp, wr, ctrl, seg, size, cur_edge, *idx);
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*num_sge = 0;
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break;
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case IB_WR_REG_MR:
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err = handle_reg_mr(qp, wr, ctrl, seg, size, cur_edge, *idx);
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if (unlikely(err))
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goto out;
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*num_sge = 0;
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break;
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case IB_WR_REG_MR_INTEGRITY:
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err = handle_reg_mr_integrity(dev, qp, wr, ctrl, seg, size,
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cur_edge, idx, nreq, fence,
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next_fence);
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if (unlikely(err))
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goto out;
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*num_sge = 0;
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break;
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default:
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break;
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}
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out:
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return err;
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}
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static void handle_qpt_uc(const struct ib_send_wr *wr, void **seg, int *size)
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{
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switch (wr->opcode) {
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case IB_WR_RDMA_WRITE:
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case IB_WR_RDMA_WRITE_WITH_IMM:
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handle_rdma_op(wr, seg, size);
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break;
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default:
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break;
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}
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}
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static void handle_qpt_hw_gsi(struct mlx5_ib_qp *qp,
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const struct ib_send_wr *wr, void **seg,
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int *size, void **cur_edge)
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{
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set_datagram_seg(*seg, wr);
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*seg += sizeof(struct mlx5_wqe_datagram_seg);
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*size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
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handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
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}
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static void handle_qpt_ud(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
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void **seg, int *size, void **cur_edge)
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{
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set_datagram_seg(*seg, wr);
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*seg += sizeof(struct mlx5_wqe_datagram_seg);
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*size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
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handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
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/* handle qp that supports ud offload */
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if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
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struct mlx5_wqe_eth_pad *pad;
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pad = *seg;
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memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
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*seg += sizeof(struct mlx5_wqe_eth_pad);
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*size += sizeof(struct mlx5_wqe_eth_pad) / 16;
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set_eth_seg(wr, qp, seg, size, cur_edge);
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handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
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}
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}
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static int handle_qpt_reg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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const struct ib_send_wr *wr,
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struct mlx5_wqe_ctrl_seg **ctrl, void **seg,
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int *size, void **cur_edge, unsigned int idx)
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{
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int err = 0;
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if (unlikely(wr->opcode != MLX5_IB_WR_UMR)) {
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err = -EINVAL;
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mlx5_ib_warn(dev, "bad opcode %d\n", wr->opcode);
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goto out;
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}
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qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
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(*ctrl)->imm = cpu_to_be32(umr_wr(wr)->mkey);
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err = set_reg_umr_segment(dev, *seg, wr,
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!!(MLX5_CAP_GEN(dev->mdev, atomic)));
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if (unlikely(err))
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goto out;
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*seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
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*size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
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handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
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set_reg_mkey_segment(*seg, wr);
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*seg += sizeof(struct mlx5_mkey_seg);
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*size += sizeof(struct mlx5_mkey_seg) / 16;
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handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
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out:
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return err;
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}
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static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
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const struct ib_send_wr **bad_wr, bool drain)
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{
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struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
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struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
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struct mlx5_core_dev *mdev = dev->mdev;
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struct ib_reg_wr reg_pi_wr;
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struct mlx5_ib_qp *qp;
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struct mlx5_ib_mr *mr;
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struct mlx5_ib_mr *pi_mr;
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struct mlx5_ib_mr pa_pi_mr;
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struct ib_sig_attrs *sig_attrs;
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struct mlx5_wqe_xrc_seg *xrc;
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struct mlx5_bf *bf;
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void *cur_edge;
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@ -5321,186 +5582,20 @@ static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
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size += sizeof(*xrc) / 16;
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/* fall through */
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case IB_QPT_RC:
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switch (wr->opcode) {
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case IB_WR_RDMA_READ:
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case IB_WR_RDMA_WRITE:
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case IB_WR_RDMA_WRITE_WITH_IMM:
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set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
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rdma_wr(wr)->rkey);
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seg += sizeof(struct mlx5_wqe_raddr_seg);
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size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
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break;
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case IB_WR_ATOMIC_CMP_AND_SWP:
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case IB_WR_ATOMIC_FETCH_AND_ADD:
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case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
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mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
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err = -ENOSYS;
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err = handle_qpt_rc(dev, qp, wr, &ctrl, &seg, &size,
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&cur_edge, &idx, nreq, fence,
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next_fence, &num_sge);
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if (unlikely(err)) {
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*bad_wr = wr;
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goto out;
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case IB_WR_LOCAL_INV:
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qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
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ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
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set_linv_wr(qp, &seg, &size, &cur_edge);
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num_sge = 0;
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break;
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case IB_WR_REG_MR:
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qp->sq.wr_data[idx] = IB_WR_REG_MR;
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ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
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err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
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&cur_edge, true);
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if (err) {
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*bad_wr = wr;
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goto out;
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}
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num_sge = 0;
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break;
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case IB_WR_REG_MR_INTEGRITY:
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qp->sq.wr_data[idx] = IB_WR_REG_MR_INTEGRITY;
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mr = to_mmr(reg_wr(wr)->mr);
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pi_mr = mr->pi_mr;
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if (pi_mr) {
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memset(®_pi_wr, 0,
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sizeof(struct ib_reg_wr));
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reg_pi_wr.mr = &pi_mr->ibmr;
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reg_pi_wr.access = reg_wr(wr)->access;
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reg_pi_wr.key = pi_mr->ibmr.rkey;
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ctrl->imm = cpu_to_be32(reg_pi_wr.key);
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/* UMR for data + prot registration */
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err = set_reg_wr(qp, ®_pi_wr, &seg,
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&size, &cur_edge,
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false);
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if (err) {
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*bad_wr = wr;
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goto out;
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}
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finish_wqe(qp, ctrl, seg, size,
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cur_edge, idx, wr->wr_id,
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nreq, fence,
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MLX5_OPCODE_UMR);
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err = begin_wqe(qp, &seg, &ctrl, wr,
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&idx, &size, &cur_edge,
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nreq);
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if (err) {
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mlx5_ib_warn(dev, "\n");
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err = -ENOMEM;
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*bad_wr = wr;
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goto out;
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}
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} else {
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memset(&pa_pi_mr, 0,
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sizeof(struct mlx5_ib_mr));
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/* No UMR, use local_dma_lkey */
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pa_pi_mr.ibmr.lkey =
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mr->ibmr.pd->local_dma_lkey;
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pa_pi_mr.ndescs = mr->ndescs;
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pa_pi_mr.data_length = mr->data_length;
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pa_pi_mr.data_iova = mr->data_iova;
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if (mr->meta_ndescs) {
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pa_pi_mr.meta_ndescs =
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mr->meta_ndescs;
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pa_pi_mr.meta_length =
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mr->meta_length;
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pa_pi_mr.pi_iova = mr->pi_iova;
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}
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pa_pi_mr.ibmr.length = mr->ibmr.length;
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mr->pi_mr = &pa_pi_mr;
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}
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ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
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/* UMR for sig MR */
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err = set_pi_umr_wr(wr, qp, &seg, &size,
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&cur_edge);
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if (err) {
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mlx5_ib_warn(dev, "\n");
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*bad_wr = wr;
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goto out;
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}
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finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
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wr->wr_id, nreq, fence,
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MLX5_OPCODE_UMR);
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/*
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* SET_PSV WQEs are not signaled and solicited
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* on error
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*/
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sig_attrs = mr->ibmr.sig_attrs;
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err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
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&size, &cur_edge, nreq, false,
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true);
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if (err) {
|
||||
mlx5_ib_warn(dev, "\n");
|
||||
err = -ENOMEM;
|
||||
*bad_wr = wr;
|
||||
goto out;
|
||||
}
|
||||
err = set_psv_wr(&sig_attrs->mem,
|
||||
mr->sig->psv_memory.psv_idx,
|
||||
&seg, &size);
|
||||
if (err) {
|
||||
mlx5_ib_warn(dev, "\n");
|
||||
*bad_wr = wr;
|
||||
goto out;
|
||||
}
|
||||
finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
|
||||
wr->wr_id, nreq, next_fence,
|
||||
MLX5_OPCODE_SET_PSV);
|
||||
|
||||
err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
|
||||
&size, &cur_edge, nreq, false,
|
||||
true);
|
||||
if (err) {
|
||||
mlx5_ib_warn(dev, "\n");
|
||||
err = -ENOMEM;
|
||||
*bad_wr = wr;
|
||||
goto out;
|
||||
}
|
||||
err = set_psv_wr(&sig_attrs->wire,
|
||||
mr->sig->psv_wire.psv_idx,
|
||||
&seg, &size);
|
||||
if (err) {
|
||||
mlx5_ib_warn(dev, "\n");
|
||||
*bad_wr = wr;
|
||||
goto out;
|
||||
}
|
||||
finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
|
||||
wr->wr_id, nreq, next_fence,
|
||||
MLX5_OPCODE_SET_PSV);
|
||||
|
||||
qp->next_fence =
|
||||
MLX5_FENCE_MODE_INITIATOR_SMALL;
|
||||
num_sge = 0;
|
||||
} else if (wr->opcode == IB_WR_REG_MR_INTEGRITY) {
|
||||
goto skip_psv;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case IB_QPT_UC:
|
||||
switch (wr->opcode) {
|
||||
case IB_WR_RDMA_WRITE:
|
||||
case IB_WR_RDMA_WRITE_WITH_IMM:
|
||||
set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
|
||||
rdma_wr(wr)->rkey);
|
||||
seg += sizeof(struct mlx5_wqe_raddr_seg);
|
||||
size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
handle_qpt_uc(wr, &seg, &size);
|
||||
break;
|
||||
|
||||
case IB_QPT_SMI:
|
||||
if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
|
||||
mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
|
||||
@ -5510,49 +5605,16 @@ static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
|
||||
}
|
||||
/* fall through */
|
||||
case MLX5_IB_QPT_HW_GSI:
|
||||
set_datagram_seg(seg, wr);
|
||||
seg += sizeof(struct mlx5_wqe_datagram_seg);
|
||||
size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
|
||||
handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
|
||||
|
||||
handle_qpt_hw_gsi(qp, wr, &seg, &size, &cur_edge);
|
||||
break;
|
||||
case IB_QPT_UD:
|
||||
set_datagram_seg(seg, wr);
|
||||
seg += sizeof(struct mlx5_wqe_datagram_seg);
|
||||
size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
|
||||
handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
|
||||
|
||||
/* handle qp that supports ud offload */
|
||||
if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
|
||||
struct mlx5_wqe_eth_pad *pad;
|
||||
|
||||
pad = seg;
|
||||
memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
|
||||
seg += sizeof(struct mlx5_wqe_eth_pad);
|
||||
size += sizeof(struct mlx5_wqe_eth_pad) / 16;
|
||||
set_eth_seg(wr, qp, &seg, &size, &cur_edge);
|
||||
handle_post_send_edge(&qp->sq, &seg, size,
|
||||
&cur_edge);
|
||||
}
|
||||
handle_qpt_ud(qp, wr, &seg, &size, &cur_edge);
|
||||
break;
|
||||
case MLX5_IB_QPT_REG_UMR:
|
||||
if (wr->opcode != MLX5_IB_WR_UMR) {
|
||||
err = -EINVAL;
|
||||
mlx5_ib_warn(dev, "bad opcode\n");
|
||||
goto out;
|
||||
}
|
||||
qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
|
||||
ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
|
||||
err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
|
||||
err = handle_qpt_reg_umr(dev, qp, wr, &ctrl, &seg,
|
||||
&size, &cur_edge, idx);
|
||||
if (unlikely(err))
|
||||
goto out;
|
||||
seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
|
||||
size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
|
||||
handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
|
||||
set_reg_mkey_segment(seg, wr);
|
||||
seg += sizeof(struct mlx5_mkey_seg);
|
||||
size += sizeof(struct mlx5_mkey_seg) / 16;
|
||||
handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user