clk: en7523: Add EN7581 support
Introduce EN7581 clock support to clk-en7523 driver. Add hw_init callback to en_clk_soc_data data structure. Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/57b6e53ed4d2b2e38abff6a3ea56841bad6be8a9.1712399981.git.lorenzo@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -10,7 +10,9 @@
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#define REG_PCI_CONTROL 0x88
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#define REG_PCI_CONTROL_PERSTOUT BIT(29)
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#define REG_PCI_CONTROL_PERSTOUT1 BIT(26)
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#define REG_PCI_CONTROL_REFCLK_EN0 BIT(23)
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#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22)
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#define REG_PCI_CONTROL_PERSTOUT2 BIT(16)
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#define REG_GSW_CLK_DIV_SEL 0x1b4
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#define REG_EMI_CLK_DIV_SEL 0x1b8
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#define REG_BUS_CLK_DIV_SEL 0x1bc
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@ -18,10 +20,25 @@
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#define REG_SPI_CLK_FREQ_SEL 0x1c8
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#define REG_NPU_CLK_DIV_SEL 0x1fc
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#define REG_CRYPTO_CLKSRC 0x200
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#define REG_RESET_CONTROL 0x834
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#define REG_RESET_CONTROL2 0x830
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#define REG_RESET2_CONTROL_PCIE2 BIT(27)
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#define REG_RESET_CONTROL1 0x834
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#define REG_RESET_CONTROL_PCIEHB BIT(29)
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#define REG_RESET_CONTROL_PCIE1 BIT(27)
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#define REG_RESET_CONTROL_PCIE2 BIT(26)
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/* EN7581 */
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#define REG_PCIE0_MEM 0x00
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#define REG_PCIE0_MEM_MASK 0x04
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#define REG_PCIE1_MEM 0x08
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#define REG_PCIE1_MEM_MASK 0x0c
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#define REG_PCIE2_MEM 0x10
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#define REG_PCIE2_MEM_MASK 0x14
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#define REG_PCIE_RESET_OPEN_DRAIN 0x018c
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#define REG_PCIE_RESET_OPEN_DRAIN_MASK GENMASK(2, 0)
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#define REG_NP_SCU_PCIC 0x88
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#define REG_NP_SCU_SSTR 0x9c
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#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
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#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
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struct en_clk_desc {
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int id;
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@ -49,6 +66,8 @@ struct en_clk_gate {
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struct en_clk_soc_data {
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const struct clk_ops pcie_ops;
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int (*hw_init)(struct platform_device *pdev, void __iomem *base,
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void __iomem *np_base);
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};
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static const u32 gsw_base[] = { 400000000, 500000000 };
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@ -211,14 +230,14 @@ static int en7523_pci_prepare(struct clk_hw *hw)
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usleep_range(1000, 2000);
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/* Reset to default */
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val = readl(np_base + REG_RESET_CONTROL);
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val = readl(np_base + REG_RESET_CONTROL1);
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mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
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REG_RESET_CONTROL_PCIEHB;
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writel(val & ~mask, np_base + REG_RESET_CONTROL);
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writel(val & ~mask, np_base + REG_RESET_CONTROL1);
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usleep_range(1000, 2000);
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writel(val | mask, np_base + REG_RESET_CONTROL);
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writel(val | mask, np_base + REG_RESET_CONTROL1);
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msleep(100);
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writel(val & ~mask, np_base + REG_RESET_CONTROL);
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writel(val & ~mask, np_base + REG_RESET_CONTROL1);
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usleep_range(5000, 10000);
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/* Release device */
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@ -259,6 +278,9 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
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cg->base = np_base;
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cg->hw.init = &init;
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if (init.ops->disable)
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init.ops->disable(&cg->hw);
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init.ops->unprepare(&cg->hw);
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if (clk_hw_register(dev, &cg->hw))
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@ -267,6 +289,111 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
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return &cg->hw;
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}
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static int en7581_pci_is_enabled(struct clk_hw *hw)
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{
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struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
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u32 val, mask;
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mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1;
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val = readl(cg->base + REG_PCI_CONTROL);
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return (val & mask) == mask;
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}
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static int en7581_pci_prepare(struct clk_hw *hw)
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{
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struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
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void __iomem *np_base = cg->base;
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u32 val, mask;
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mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
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REG_RESET_CONTROL_PCIEHB;
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val = readl(np_base + REG_RESET_CONTROL1);
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writel(val & ~mask, np_base + REG_RESET_CONTROL1);
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val = readl(np_base + REG_RESET_CONTROL2);
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writel(val & ~REG_RESET2_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
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usleep_range(5000, 10000);
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return 0;
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}
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static int en7581_pci_enable(struct clk_hw *hw)
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{
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struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
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void __iomem *np_base = cg->base;
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u32 val, mask;
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mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 |
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REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 |
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REG_PCI_CONTROL_PERSTOUT;
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val = readl(np_base + REG_PCI_CONTROL);
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writel(val | mask, np_base + REG_PCI_CONTROL);
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msleep(250);
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return 0;
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}
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static void en7581_pci_unprepare(struct clk_hw *hw)
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{
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struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
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void __iomem *np_base = cg->base;
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u32 val, mask;
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mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
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REG_RESET_CONTROL_PCIEHB;
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val = readl(np_base + REG_RESET_CONTROL1);
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writel(val | mask, np_base + REG_RESET_CONTROL1);
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mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2;
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writel(val | mask, np_base + REG_RESET_CONTROL1);
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val = readl(np_base + REG_RESET_CONTROL2);
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writel(val | REG_RESET_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
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msleep(100);
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}
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static void en7581_pci_disable(struct clk_hw *hw)
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{
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struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
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void __iomem *np_base = cg->base;
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u32 val, mask;
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mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 |
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REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 |
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REG_PCI_CONTROL_PERSTOUT;
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val = readl(np_base + REG_PCI_CONTROL);
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writel(val & ~mask, np_base + REG_PCI_CONTROL);
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usleep_range(1000, 2000);
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}
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static int en7581_clk_hw_init(struct platform_device *pdev,
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void __iomem *base,
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void __iomem *np_base)
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{
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void __iomem *pb_base;
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u32 val;
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pb_base = devm_platform_ioremap_resource(pdev, 2);
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if (IS_ERR(pb_base))
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return PTR_ERR(pb_base);
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val = readl(np_base + REG_NP_SCU_SSTR);
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val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
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writel(val, np_base + REG_NP_SCU_SSTR);
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val = readl(np_base + REG_NP_SCU_PCIC);
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writel(val | 3, np_base + REG_NP_SCU_PCIC);
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writel(0x20000000, pb_base + REG_PCIE0_MEM);
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writel(0xfc000000, pb_base + REG_PCIE0_MEM_MASK);
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writel(0x24000000, pb_base + REG_PCIE1_MEM);
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writel(0xfc000000, pb_base + REG_PCIE1_MEM_MASK);
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writel(0x28000000, pb_base + REG_PCIE2_MEM);
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writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK);
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val = readl(base + REG_PCIE_RESET_OPEN_DRAIN);
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writel(val | REG_PCIE_RESET_OPEN_DRAIN_MASK,
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base + REG_PCIE_RESET_OPEN_DRAIN);
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return 0;
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}
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static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
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void __iomem *base, void __iomem *np_base)
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{
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@ -299,6 +426,7 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat
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static int en7523_clk_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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const struct en_clk_soc_data *soc_data;
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struct clk_hw_onecell_data *clk_data;
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void __iomem *base, *np_base;
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int r;
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@ -311,6 +439,13 @@ static int en7523_clk_probe(struct platform_device *pdev)
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if (IS_ERR(np_base))
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return PTR_ERR(np_base);
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soc_data = device_get_match_data(&pdev->dev);
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if (soc_data->hw_init) {
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r = soc_data->hw_init(pdev, base, np_base);
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if (r)
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return r;
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}
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clk_data = devm_kzalloc(&pdev->dev,
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struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
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GFP_KERNEL);
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@ -336,8 +471,20 @@ static const struct en_clk_soc_data en7523_data = {
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},
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};
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static const struct en_clk_soc_data en7581_data = {
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.pcie_ops = {
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.is_enabled = en7581_pci_is_enabled,
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.prepare = en7581_pci_prepare,
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.enable = en7581_pci_enable,
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.unprepare = en7581_pci_unprepare,
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.disable = en7581_pci_disable,
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},
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.hw_init = en7581_clk_hw_init,
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};
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static const struct of_device_id of_match_clk_en7523[] = {
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{ .compatible = "airoha,en7523-scu", .data = &en7523_data },
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{ .compatible = "airoha,en7581-scu", .data = &en7581_data },
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{ /* sentinel */ }
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};
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