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iio: dac: ad5449: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: 8341dc04dfb3 ("iio:dac: Add support for the ad5449")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-47-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:26 +01:00
parent d2b240d3d3
commit 678d536bb4
1 changed files with 2 additions and 2 deletions
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4
drivers/iio/dac/ad5449.c
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@ -68,10 +68,10 @@ struct ad5449 {
uint16_t dac_cache[AD5449_MAX_CHANNELS];
/*
* DMA (thus cache coherency maintenance) requires the
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
__be16 data[2] ____cacheline_aligned;
__be16 data[2] __aligned(IIO_DMA_MINALIGN);
};
enum ad5449_type {