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[SPARC64]: Fix _PAGE_EXEC_4U check in sun4u I-TLB miss handler.

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It was using an immediate _PAGE_EXEC_4U value in an 'and'
instruction to perform the test.  This doesn't work because
the immediate field is signed 13-bit, this the mask being
tested against the PTE was 0x1000 sign-extended to 32-bits
instead of just plain 0x1000.

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2007-05-27 20:24:47 -07:00
parent b00ccd0f0b
commit 679292993c
1 changed files with 2 additions and 2 deletions
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4
arch/sparc64/kernel/itlb_miss.S
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@ -11,12 +11,12 @@
/* ITLB ** ICACHE line 2: TSB compare and TLB load */ /* ITLB ** ICACHE line 2: TSB compare and TLB load */
bne,pn %xcc, tsb_miss_itlb ! Miss bne,pn %xcc, tsb_miss_itlb ! Miss
mov FAULT_CODE_ITLB, %g3 mov FAULT_CODE_ITLB, %g3
andcc %g5, _PAGE_EXEC_4U, %g0 ! Executable? sethi %hi(_PAGE_EXEC_4U), %g4
andcc %g5, %g4, %g0 ! Executable?
be,pn %xcc, tsb_do_fault be,pn %xcc, tsb_do_fault
nop ! Delay slot, fill me nop ! Delay slot, fill me
stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB
retry ! Trap done retry ! Trap done
nop
/* ITLB ** ICACHE line 3: */ /* ITLB ** ICACHE line 3: */
nop nop