ice: Implement getting and setting ethtool coalesce
This patch includes the following ethtool operations: 1. get_coalesce 2. set_coalesce 3. get_per_q_coalesce 4. set_per_q_coalesce Each ITR value (current_itr/target_itr) are stored on a per ice_ring_container basis. This is because each valid ice_ring_container can have 1 or more rings that are tied to the same q_vector ITR index. Signed-off-by: Brett Creeley <brett.creeley@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Brett Creeley
Jeff Kirsher
parent
63f545ed12
commit
67fe64d78c
@ -110,6 +110,9 @@ extern const char ice_drv_ver[];
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#define ice_for_each_alloc_rxq(vsi, i) \
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for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++)
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#define ice_for_each_q_vector(vsi, i) \
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for ((i) = 0; (i) < (vsi)->num_q_vectors; (i)++)
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struct ice_tc_info {
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u16 qoffset;
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u16 qcount_tx;
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@ -1823,6 +1823,258 @@ static int ice_set_rxfh(struct net_device *netdev, const u32 *indir,
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return 0;
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}
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enum ice_container_type {
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ICE_RX_CONTAINER,
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ICE_TX_CONTAINER,
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};
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/**
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* ice_get_rc_coalesce - get ITR values for specific ring container
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* @ec: ethtool structure to fill with driver's coalesce settings
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* @c_type: container type, RX or TX
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* @rc: ring container that the ITR values will come from
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*
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* Query the device for ice_ring_container specific ITR values. This is
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* done per ice_ring_container because each q_vector can have 1 or more rings
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* and all of said ring(s) will have the same ITR values.
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*
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* Returns 0 on success, negative otherwise.
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*/
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static int
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ice_get_rc_coalesce(struct ethtool_coalesce *ec, enum ice_container_type c_type,
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struct ice_ring_container *rc)
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{
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struct ice_pf *pf = rc->ring->vsi->back;
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switch (c_type) {
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case ICE_RX_CONTAINER:
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ec->use_adaptive_rx_coalesce = ITR_IS_DYNAMIC(rc->itr_setting);
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ec->rx_coalesce_usecs = rc->itr_setting & ~ICE_ITR_DYNAMIC;
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break;
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case ICE_TX_CONTAINER:
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ec->use_adaptive_tx_coalesce = ITR_IS_DYNAMIC(rc->itr_setting);
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ec->tx_coalesce_usecs = rc->itr_setting & ~ICE_ITR_DYNAMIC;
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break;
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default:
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dev_dbg(&pf->pdev->dev, "Invalid c_type %d\n", c_type);
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return -EINVAL;
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}
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return 0;
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}
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/**
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* __ice_get_coalesce - get ITR/INTRL values for the device
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* @netdev: pointer to the netdev associated with this query
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* @ec: ethtool structure to fill with driver's coalesce settings
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* @q_num: queue number to get the coalesce settings for
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*/
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static int
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__ice_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec,
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int q_num)
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{
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struct ice_netdev_priv *np = netdev_priv(netdev);
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int tx = -EINVAL, rx = -EINVAL;
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struct ice_vsi *vsi = np->vsi;
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if (q_num < 0) {
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rx = ice_get_rc_coalesce(ec, ICE_RX_CONTAINER,
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&vsi->rx_rings[0]->q_vector->rx);
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tx = ice_get_rc_coalesce(ec, ICE_TX_CONTAINER,
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&vsi->tx_rings[0]->q_vector->tx);
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goto update_coalesced_frames;
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}
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if (q_num < vsi->num_rxq && q_num < vsi->num_txq) {
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rx = ice_get_rc_coalesce(ec, ICE_RX_CONTAINER,
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&vsi->rx_rings[q_num]->q_vector->rx);
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tx = ice_get_rc_coalesce(ec, ICE_TX_CONTAINER,
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&vsi->tx_rings[q_num]->q_vector->tx);
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} else if (q_num < vsi->num_rxq) {
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rx = ice_get_rc_coalesce(ec, ICE_RX_CONTAINER,
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&vsi->rx_rings[q_num]->q_vector->rx);
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} else if (q_num < vsi->num_txq) {
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tx = ice_get_rc_coalesce(ec, ICE_TX_CONTAINER,
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&vsi->tx_rings[q_num]->q_vector->tx);
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} else {
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/* q_num is invalid for both Rx and Tx queues */
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return -EINVAL;
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}
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update_coalesced_frames:
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/* either q_num is invalid for both Rx and Tx queues or setting coalesce
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* failed completely
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*/
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if (tx && rx)
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return -EINVAL;
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if (q_num < vsi->num_txq)
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ec->tx_max_coalesced_frames_irq = vsi->work_lmt;
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if (q_num < vsi->num_rxq)
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ec->rx_max_coalesced_frames_irq = vsi->work_lmt;
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return 0;
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}
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static int
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ice_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec)
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{
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return __ice_get_coalesce(netdev, ec, -1);
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}
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static int ice_get_per_q_coalesce(struct net_device *netdev, u32 q_num,
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struct ethtool_coalesce *ec)
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{
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return __ice_get_coalesce(netdev, ec, q_num);
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}
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/**
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* ice_set_rc_coalesce - set ITR values for specific ring container
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* @c_type: container type, RX or TX
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* @ec: ethtool structure from user to update ITR settings
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* @rc: ring container that the ITR values will come from
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* @vsi: VSI associated to the ring container
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*
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* Set specific ITR values. This is done per ice_ring_container because each
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* q_vector can have 1 or more rings and all of said ring(s) will have the same
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* ITR values.
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*
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* Returns 0 on success, negative otherwise.
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*/
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static int
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ice_set_rc_coalesce(enum ice_container_type c_type, struct ethtool_coalesce *ec,
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struct ice_ring_container *rc, struct ice_vsi *vsi)
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{
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struct ice_pf *pf = vsi->back;
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u16 itr_setting;
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if (!rc->ring)
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return -EINVAL;
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itr_setting = rc->itr_setting & ~ICE_ITR_DYNAMIC;
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switch (c_type) {
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case ICE_RX_CONTAINER:
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if (ec->rx_coalesce_usecs != itr_setting &&
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ec->use_adaptive_rx_coalesce) {
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netdev_info(vsi->netdev,
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"Rx interrupt throttling cannot be changed if adaptive-rx is enabled\n");
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return -EINVAL;
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}
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if (ec->rx_coalesce_usecs > ICE_ITR_MAX) {
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netdev_info(vsi->netdev,
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"Invalid value, rx-usecs range is 0-%d\n",
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ICE_ITR_MAX);
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return -EINVAL;
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}
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if (ec->use_adaptive_rx_coalesce) {
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rc->itr_setting |= ICE_ITR_DYNAMIC;
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} else {
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rc->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs);
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rc->target_itr = ITR_TO_REG(rc->itr_setting);
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}
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break;
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case ICE_TX_CONTAINER:
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if (ec->tx_coalesce_usecs != itr_setting &&
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ec->use_adaptive_tx_coalesce) {
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netdev_info(vsi->netdev,
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"Tx interrupt throttling cannot be changed if adaptive-tx is enabled\n");
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return -EINVAL;
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}
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if (ec->tx_coalesce_usecs > ICE_ITR_MAX) {
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netdev_info(vsi->netdev,
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"Invalid value, tx-usecs range is 0-%d\n",
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ICE_ITR_MAX);
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return -EINVAL;
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}
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if (ec->use_adaptive_tx_coalesce) {
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rc->itr_setting |= ICE_ITR_DYNAMIC;
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} else {
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rc->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs);
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rc->target_itr = ITR_TO_REG(rc->itr_setting);
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}
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break;
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default:
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dev_dbg(&pf->pdev->dev, "Invalid container type %d\n", c_type);
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return -EINVAL;
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}
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return 0;
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}
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static int
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__ice_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec,
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int q_num)
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{
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struct ice_netdev_priv *np = netdev_priv(netdev);
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int rx = -EINVAL, tx = -EINVAL;
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struct ice_vsi *vsi = np->vsi;
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if (q_num < 0) {
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int i;
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ice_for_each_q_vector(vsi, i) {
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struct ice_q_vector *q_vector = vsi->q_vectors[i];
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if (ice_set_rc_coalesce(ICE_RX_CONTAINER, ec,
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&q_vector->rx, vsi) ||
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ice_set_rc_coalesce(ICE_TX_CONTAINER, ec,
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&q_vector->tx, vsi))
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return -EINVAL;
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}
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goto set_work_lmt;
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}
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if (q_num < vsi->num_rxq && q_num < vsi->num_txq) {
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rx = ice_set_rc_coalesce(ICE_RX_CONTAINER, ec,
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&vsi->rx_rings[q_num]->q_vector->rx,
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vsi);
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tx = ice_set_rc_coalesce(ICE_TX_CONTAINER, ec,
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&vsi->tx_rings[q_num]->q_vector->tx,
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vsi);
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} else if (q_num < vsi->num_rxq) {
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rx = ice_set_rc_coalesce(ICE_RX_CONTAINER, ec,
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&vsi->rx_rings[q_num]->q_vector->rx,
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vsi);
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} else if (q_num < vsi->num_txq) {
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tx = ice_set_rc_coalesce(ICE_TX_CONTAINER, ec,
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&vsi->tx_rings[q_num]->q_vector->tx,
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vsi);
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}
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/* either q_num is invalid for both Rx and Tx queues or setting coalesce
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* failed completely
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*/
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if (rx && tx)
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return -EINVAL;
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set_work_lmt:
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if (ec->tx_max_coalesced_frames_irq || ec->rx_max_coalesced_frames_irq)
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vsi->work_lmt = max(ec->tx_max_coalesced_frames_irq,
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ec->rx_max_coalesced_frames_irq);
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return 0;
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}
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static int
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ice_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec)
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{
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return __ice_set_coalesce(netdev, ec, -1);
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}
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static int ice_set_per_q_coalesce(struct net_device *netdev, u32 q_num,
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struct ethtool_coalesce *ec)
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{
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return __ice_set_coalesce(netdev, ec, q_num);
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}
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static const struct ethtool_ops ice_ethtool_ops = {
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.get_link_ksettings = ice_get_link_ksettings,
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.set_link_ksettings = ice_set_link_ksettings,
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@ -1834,6 +2086,8 @@ static const struct ethtool_ops ice_ethtool_ops = {
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.get_link = ethtool_op_get_link,
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.get_eeprom_len = ice_get_eeprom_len,
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.get_eeprom = ice_get_eeprom,
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.get_coalesce = ice_get_coalesce,
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.set_coalesce = ice_set_coalesce,
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.get_strings = ice_get_strings,
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.set_phys_id = ice_set_phys_id,
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.get_ethtool_stats = ice_get_ethtool_stats,
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@ -1850,6 +2104,8 @@ static const struct ethtool_ops ice_ethtool_ops = {
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.get_rxfh_indir_size = ice_get_rxfh_indir_size,
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.get_rxfh = ice_get_rxfh,
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.set_rxfh = ice_set_rxfh,
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.get_per_queue_coalesce = ice_get_per_q_coalesce,
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.set_per_queue_coalesce = ice_set_per_q_coalesce,
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};
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/**
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@ -118,9 +118,11 @@ enum ice_rx_dtype {
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#define ICE_TX_ITR ICE_IDX_ITR1
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#define ICE_ITR_8K 124
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#define ICE_ITR_20K 50
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#define ICE_ITR_MAX 8160
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#define ICE_DFLT_TX_ITR (ICE_ITR_20K | ICE_ITR_DYNAMIC)
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#define ICE_DFLT_RX_ITR (ICE_ITR_20K | ICE_ITR_DYNAMIC)
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#define ICE_ITR_DYNAMIC 0x8000 /* used as flag for itr_setting */
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#define ITR_IS_DYNAMIC(setting) (!!((setting) & ICE_ITR_DYNAMIC))
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#define ITR_TO_REG(setting) ((setting) & ~ICE_ITR_DYNAMIC)
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#define ICE_ITR_GRAN_S 1 /* Assume ITR granularity is 2us */
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#define ICE_ITR_MASK 0x1FFE /* ITR register value alignment mask */
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