[ARM] pxa/corgi: remove now unused corgi_ssp.c and corgi_lcd.c
Now poodle/corgi/spitz have been been converted to use SPI-based
drivers, remove the now unused corgi_ssp.c and corgi_lcd.c. And
as well as the unused reference of {corgi,spitz}ssp_device.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Eric Miao
Russell King
parent
859b796349
commit
68677ab3d0
@ -1,290 +0,0 @@
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/*
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* linux/arch/arm/mach-pxa/corgi_lcd.c
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*
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* Corgi/Spitz LCD Specific Code
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*
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* Copyright (C) 2005 Richard Purdie
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*
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* Connectivity:
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* Corgi - LCD to ATI Imageon w100 (Wallaby)
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* Spitz - LCD to PXA Framebuffer
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <mach/akita.h>
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#include <mach/corgi.h>
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#include <mach/hardware.h>
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#include <mach/pxa-regs.h>
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#include <mach/sharpsl.h>
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#include <mach/spitz.h>
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#include <asm/hardware/scoop.h>
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#include <asm/mach/sharpsl_param.h>
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#include "generic.h"
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/* Register Addresses */
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#define RESCTL_ADRS 0x00
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#define PHACTRL_ADRS 0x01
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#define DUTYCTRL_ADRS 0x02
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#define POWERREG0_ADRS 0x03
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#define POWERREG1_ADRS 0x04
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#define GPOR3_ADRS 0x05
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#define PICTRL_ADRS 0x06
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#define POLCTRL_ADRS 0x07
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/* Register Bit Definitions */
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#define RESCTL_QVGA 0x01
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#define RESCTL_VGA 0x00
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#define POWER1_VW_ON 0x01 /* VW Supply FET ON */
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#define POWER1_GVSS_ON 0x02 /* GVSS(-8V) Power Supply ON */
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#define POWER1_VDD_ON 0x04 /* VDD(8V),SVSS(-4V) Power Supply ON */
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#define POWER1_VW_OFF 0x00 /* VW Supply FET OFF */
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#define POWER1_GVSS_OFF 0x00 /* GVSS(-8V) Power Supply OFF */
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#define POWER1_VDD_OFF 0x00 /* VDD(8V),SVSS(-4V) Power Supply OFF */
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#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
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#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */
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#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */
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#define POWER0_COM_ON 0x08 /* COM Power Supply ON */
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#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */
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#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */
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#define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */
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#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */
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#define PICTRL_INIT_STATE 0x01
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#define PICTRL_INIOFF 0x02
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#define PICTRL_POWER_DOWN 0x04
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#define PICTRL_COM_SIGNAL_OFF 0x08
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#define PICTRL_DAC_SIGNAL_OFF 0x10
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#define POLCTRL_SYNC_POL_FALL 0x01
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#define POLCTRL_EN_POL_FALL 0x02
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#define POLCTRL_DATA_POL_FALL 0x04
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#define POLCTRL_SYNC_ACT_H 0x08
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#define POLCTRL_EN_ACT_L 0x10
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#define POLCTRL_SYNC_POL_RISE 0x00
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#define POLCTRL_EN_POL_RISE 0x00
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#define POLCTRL_DATA_POL_RISE 0x00
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#define POLCTRL_SYNC_ACT_L 0x00
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#define POLCTRL_EN_ACT_H 0x00
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#define PHACTRL_PHASE_MANUAL 0x01
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#define DEFAULT_PHAD_QVGA (9)
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#define DEFAULT_COMADJ (125)
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/*
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* This is only a psuedo I2C interface. We can't use the standard kernel
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* routines as the interface is write only. We just assume the data is acked...
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*/
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static void lcdtg_ssp_i2c_send(u8 data)
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{
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, data);
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udelay(10);
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}
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static void lcdtg_i2c_send_bit(u8 data)
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{
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lcdtg_ssp_i2c_send(data);
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lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK);
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lcdtg_ssp_i2c_send(data);
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}
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static void lcdtg_i2c_send_start(u8 base)
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{
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lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
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lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
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lcdtg_ssp_i2c_send(base);
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}
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static void lcdtg_i2c_send_stop(u8 base)
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{
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lcdtg_ssp_i2c_send(base);
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lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
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lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
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}
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static void lcdtg_i2c_send_byte(u8 base, u8 data)
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{
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int i;
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for (i = 0; i < 8; i++) {
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if (data & 0x80)
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lcdtg_i2c_send_bit(base | POWER0_COM_DOUT);
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else
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lcdtg_i2c_send_bit(base);
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data <<= 1;
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}
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}
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static void lcdtg_i2c_wait_ack(u8 base)
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{
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lcdtg_i2c_send_bit(base);
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}
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static void lcdtg_set_common_voltage(u8 base_data, u8 data)
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{
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/* Set Common Voltage to M62332FP via I2C */
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lcdtg_i2c_send_start(base_data);
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lcdtg_i2c_send_byte(base_data, 0x9c);
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lcdtg_i2c_wait_ack(base_data);
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lcdtg_i2c_send_byte(base_data, 0x00);
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lcdtg_i2c_wait_ack(base_data);
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lcdtg_i2c_send_byte(base_data, data);
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lcdtg_i2c_wait_ack(base_data);
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lcdtg_i2c_send_stop(base_data);
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}
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/* Set Phase Adjust */
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static void lcdtg_set_phadadj(int mode)
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{
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int adj;
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switch(mode) {
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case 480:
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case 640:
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/* Setting for VGA */
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adj = sharpsl_param.phadadj;
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if (adj < 0) {
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adj = PHACTRL_PHASE_MANUAL;
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} else {
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adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL;
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}
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break;
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case 240:
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case 320:
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default:
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/* Setting for QVGA */
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adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL;
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break;
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}
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corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj);
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}
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static int lcd_inited;
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void corgi_lcdtg_hw_init(int mode)
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{
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if (!lcd_inited) {
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int comadj;
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/* Initialize Internal Logic & Port */
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corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE
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| PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF);
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF
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| POWER0_COM_OFF | POWER0_VCC5_OFF);
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
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/* VDD(+8V), SVSS(-4V) ON */
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
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mdelay(3);
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/* DAC ON */
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
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| POWER0_COM_OFF | POWER0_VCC5_OFF);
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/* INIB = H, INI = L */
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/* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
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corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
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/* Set Common Voltage */
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comadj = sharpsl_param.comadj;
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if (comadj < 0)
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comadj = DEFAULT_COMADJ;
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lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj);
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/* VCC5 ON, DAC ON */
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON |
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POWER0_COM_OFF | POWER0_VCC5_ON);
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/* GVSS(-8V) ON, VDD ON */
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
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mdelay(2);
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/* COM SIGNAL ON (PICTL[3] = L) */
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corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE);
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/* COM ON, DAC ON, VCC5_ON */
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
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| POWER0_COM_ON | POWER0_VCC5_ON);
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/* VW ON, GVSS ON, VDD ON */
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON);
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/* Signals output enable */
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corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
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/* Set Phase Adjust */
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lcdtg_set_phadadj(mode);
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/* Initialize for Input Signals from ATI */
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corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE
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| POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H);
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udelay(1000);
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lcd_inited=1;
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} else {
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lcdtg_set_phadadj(mode);
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}
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switch(mode) {
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case 480:
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case 640:
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/* Set Lcd Resolution (VGA) */
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corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA);
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break;
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case 240:
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case 320:
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default:
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/* Set Lcd Resolution (QVGA) */
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corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA);
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break;
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}
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}
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void corgi_lcdtg_suspend(void)
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{
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/* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
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mdelay(34);
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/* (1)VW OFF */
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
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/* (2)COM OFF */
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corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF);
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON);
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/* (3)Set Common Voltage Bias 0V */
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lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0);
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/* (4)GVSS OFF */
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
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/* (5)VCC5 OFF */
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF);
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/* (6)Set PDWN, INIOFF, DACOFF */
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corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF |
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PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF);
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/* (7)DAC OFF */
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF);
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/* (8)VDD OFF */
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
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lcd_inited = 0;
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}
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@ -1,276 +0,0 @@
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/*
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* SSP control code for Sharp Corgi devices
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*
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* Copyright (c) 2004-2005 Richard Purdie
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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#include <mach/ssp.h>
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#include <mach/pxa-regs.h>
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#include <mach/pxa2xx-gpio.h>
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#include <mach/regs-ssp.h>
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#include "sharpsl.h"
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static DEFINE_SPINLOCK(corgi_ssp_lock);
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static struct ssp_dev corgi_ssp_dev;
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static struct ssp_state corgi_ssp_state;
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static struct corgissp_machinfo *ssp_machinfo;
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/*
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* There are three devices connected to the SSP interface:
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* 1. A touchscreen controller (TI ADS7846 compatible)
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* 2. An LCD controller (with some Backlight functionality)
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* 3. A battery monitoring IC (Maxim MAX1111)
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*
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* Each device uses a different speed/mode of communication.
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*
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* The touchscreen is very sensitive and the most frequently used
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* so the port is left configured for this.
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||||||
*
|
|
||||||
* Devices are selected using Chip Selects on GPIOs.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* ADS7846 Routines
|
|
||||||
*/
|
|
||||||
unsigned long corgi_ssp_ads7846_putget(ulong data)
|
|
||||||
{
|
|
||||||
unsigned long flag;
|
|
||||||
u32 ret = 0;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&corgi_ssp_lock, flag);
|
|
||||||
if (ssp_machinfo->cs_ads7846 >= 0)
|
|
||||||
GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
|
|
||||||
|
|
||||||
ssp_write_word(&corgi_ssp_dev,data);
|
|
||||||
ssp_read_word(&corgi_ssp_dev, &ret);
|
|
||||||
|
|
||||||
if (ssp_machinfo->cs_ads7846 >= 0)
|
|
||||||
GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
|
|
||||||
spin_unlock_irqrestore(&corgi_ssp_lock, flag);
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NOTE: These functions should always be called in interrupt context
|
|
||||||
* and use the _lock and _unlock functions. They are very time sensitive.
|
|
||||||
*/
|
|
||||||
void corgi_ssp_ads7846_lock(void)
|
|
||||||
{
|
|
||||||
spin_lock(&corgi_ssp_lock);
|
|
||||||
if (ssp_machinfo->cs_ads7846 >= 0)
|
|
||||||
GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
|
|
||||||
}
|
|
||||||
|
|
||||||
void corgi_ssp_ads7846_unlock(void)
|
|
||||||
{
|
|
||||||
if (ssp_machinfo->cs_ads7846 >= 0)
|
|
||||||
GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
|
|
||||||
spin_unlock(&corgi_ssp_lock);
|
|
||||||
}
|
|
||||||
|
|
||||||
void corgi_ssp_ads7846_put(ulong data)
|
|
||||||
{
|
|
||||||
ssp_write_word(&corgi_ssp_dev,data);
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned long corgi_ssp_ads7846_get(void)
|
|
||||||
{
|
|
||||||
u32 ret = 0;
|
|
||||||
ssp_read_word(&corgi_ssp_dev, &ret);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
EXPORT_SYMBOL(corgi_ssp_ads7846_putget);
|
|
||||||
EXPORT_SYMBOL(corgi_ssp_ads7846_lock);
|
|
||||||
EXPORT_SYMBOL(corgi_ssp_ads7846_unlock);
|
|
||||||
EXPORT_SYMBOL(corgi_ssp_ads7846_put);
|
|
||||||
EXPORT_SYMBOL(corgi_ssp_ads7846_get);
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* LCD/Backlight Routines
|
|
||||||
*/
|
|
||||||
unsigned long corgi_ssp_dac_put(ulong data)
|
|
||||||
{
|
|
||||||
unsigned long flag, sscr1 = SSCR1_SPH;
|
|
||||||
u32 tmp;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&corgi_ssp_lock, flag);
|
|
||||||
|
|
||||||
if (machine_is_spitz() || machine_is_akita() || machine_is_borzoi())
|
|
||||||
sscr1 = 0;
|
|
||||||
|
|
||||||
ssp_disable(&corgi_ssp_dev);
|
|
||||||
ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), sscr1, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_lcdcon));
|
|
||||||
ssp_enable(&corgi_ssp_dev);
|
|
||||||
|
|
||||||
if (ssp_machinfo->cs_lcdcon >= 0)
|
|
||||||
GPCR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
|
|
||||||
ssp_write_word(&corgi_ssp_dev,data);
|
|
||||||
/* Read null data back from device to prevent SSP overflow */
|
|
||||||
ssp_read_word(&corgi_ssp_dev, &tmp);
|
|
||||||
if (ssp_machinfo->cs_lcdcon >= 0)
|
|
||||||
GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
|
|
||||||
|
|
||||||
ssp_disable(&corgi_ssp_dev);
|
|
||||||
ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
|
|
||||||
ssp_enable(&corgi_ssp_dev);
|
|
||||||
|
|
||||||
spin_unlock_irqrestore(&corgi_ssp_lock, flag);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
void corgi_ssp_lcdtg_send(u8 adrs, u8 data)
|
|
||||||
{
|
|
||||||
corgi_ssp_dac_put(((adrs & 0x07) << 5) | (data & 0x1f));
|
|
||||||
}
|
|
||||||
|
|
||||||
void corgi_ssp_blduty_set(int duty)
|
|
||||||
{
|
|
||||||
corgi_ssp_lcdtg_send(0x02,duty);
|
|
||||||
}
|
|
||||||
|
|
||||||
EXPORT_SYMBOL(corgi_ssp_lcdtg_send);
|
|
||||||
EXPORT_SYMBOL(corgi_ssp_blduty_set);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Max1111 Routines
|
|
||||||
*/
|
|
||||||
int corgi_ssp_max1111_get(ulong data)
|
|
||||||
{
|
|
||||||
unsigned long flag;
|
|
||||||
long voltage = 0, voltage1 = 0, voltage2 = 0;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&corgi_ssp_lock, flag);
|
|
||||||
if (ssp_machinfo->cs_max1111 >= 0)
|
|
||||||
GPCR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
|
|
||||||
ssp_disable(&corgi_ssp_dev);
|
|
||||||
ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_max1111));
|
|
||||||
ssp_enable(&corgi_ssp_dev);
|
|
||||||
|
|
||||||
udelay(1);
|
|
||||||
|
|
||||||
/* TB1/RB1 */
|
|
||||||
ssp_write_word(&corgi_ssp_dev,data);
|
|
||||||
ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); /* null read */
|
|
||||||
|
|
||||||
/* TB12/RB2 */
|
|
||||||
ssp_write_word(&corgi_ssp_dev,0);
|
|
||||||
ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1);
|
|
||||||
|
|
||||||
/* TB13/RB3*/
|
|
||||||
ssp_write_word(&corgi_ssp_dev,0);
|
|
||||||
ssp_read_word(&corgi_ssp_dev, (u32*)&voltage2);
|
|
||||||
|
|
||||||
ssp_disable(&corgi_ssp_dev);
|
|
||||||
ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
|
|
||||||
ssp_enable(&corgi_ssp_dev);
|
|
||||||
if (ssp_machinfo->cs_max1111 >= 0)
|
|
||||||
GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
|
|
||||||
spin_unlock_irqrestore(&corgi_ssp_lock, flag);
|
|
||||||
|
|
||||||
if (voltage1 & 0xc0 || voltage2 & 0x3f)
|
|
||||||
voltage = -1;
|
|
||||||
else
|
|
||||||
voltage = ((voltage1 << 2) & 0xfc) | ((voltage2 >> 6) & 0x03);
|
|
||||||
|
|
||||||
return voltage;
|
|
||||||
}
|
|
||||||
|
|
||||||
EXPORT_SYMBOL(corgi_ssp_max1111_get);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Support Routines
|
|
||||||
*/
|
|
||||||
|
|
||||||
void __init corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo)
|
|
||||||
{
|
|
||||||
ssp_machinfo = machinfo;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int __init corgi_ssp_probe(struct platform_device *dev)
|
|
||||||
{
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
/* Chip Select - Disable All */
|
|
||||||
if (ssp_machinfo->cs_lcdcon >= 0)
|
|
||||||
pxa_gpio_mode(ssp_machinfo->cs_lcdcon | GPIO_OUT | GPIO_DFLT_HIGH);
|
|
||||||
if (ssp_machinfo->cs_max1111 >= 0)
|
|
||||||
pxa_gpio_mode(ssp_machinfo->cs_max1111 | GPIO_OUT | GPIO_DFLT_HIGH);
|
|
||||||
if (ssp_machinfo->cs_ads7846 >= 0)
|
|
||||||
pxa_gpio_mode(ssp_machinfo->cs_ads7846 | GPIO_OUT | GPIO_DFLT_HIGH);
|
|
||||||
|
|
||||||
ret = ssp_init(&corgi_ssp_dev, ssp_machinfo->port, 0);
|
|
||||||
|
|
||||||
if (ret)
|
|
||||||
printk(KERN_ERR "Unable to register SSP handler!\n");
|
|
||||||
else {
|
|
||||||
ssp_disable(&corgi_ssp_dev);
|
|
||||||
ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
|
|
||||||
ssp_enable(&corgi_ssp_dev);
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int corgi_ssp_remove(struct platform_device *dev)
|
|
||||||
{
|
|
||||||
ssp_exit(&corgi_ssp_dev);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int corgi_ssp_suspend(struct platform_device *dev, pm_message_t state)
|
|
||||||
{
|
|
||||||
ssp_flush(&corgi_ssp_dev);
|
|
||||||
ssp_save_state(&corgi_ssp_dev,&corgi_ssp_state);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int corgi_ssp_resume(struct platform_device *dev)
|
|
||||||
{
|
|
||||||
if (ssp_machinfo->cs_lcdcon >= 0)
|
|
||||||
GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); /* High - Disable LCD Control/Timing Gen */
|
|
||||||
if (ssp_machinfo->cs_max1111 >= 0)
|
|
||||||
GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111); /* High - Disable MAX1111*/
|
|
||||||
if (ssp_machinfo->cs_ads7846 >= 0)
|
|
||||||
GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); /* High - Disable ADS7846*/
|
|
||||||
ssp_restore_state(&corgi_ssp_dev,&corgi_ssp_state);
|
|
||||||
ssp_enable(&corgi_ssp_dev);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct platform_driver corgissp_driver = {
|
|
||||||
.probe = corgi_ssp_probe,
|
|
||||||
.remove = corgi_ssp_remove,
|
|
||||||
.suspend = corgi_ssp_suspend,
|
|
||||||
.resume = corgi_ssp_resume,
|
|
||||||
.driver = {
|
|
||||||
.name = "corgi-ssp",
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
int __init corgi_ssp_init(void)
|
|
||||||
{
|
|
||||||
return platform_driver_register(&corgissp_driver);
|
|
||||||
}
|
|
||||||
|
|
||||||
arch_initcall(corgi_ssp_init);
|
|
||||||
@ -103,7 +103,6 @@
|
|||||||
* Shared data structures
|
* Shared data structures
|
||||||
*/
|
*/
|
||||||
extern struct platform_device corgiscoop_device;
|
extern struct platform_device corgiscoop_device;
|
||||||
extern struct platform_device corgissp_device;
|
|
||||||
|
|
||||||
#endif /* __ASM_ARCH_CORGI_H */
|
#endif /* __ASM_ARCH_CORGI_H */
|
||||||
|
|
||||||
|
|||||||
@ -154,5 +154,4 @@
|
|||||||
*/
|
*/
|
||||||
extern struct platform_device spitzscoop_device;
|
extern struct platform_device spitzscoop_device;
|
||||||
extern struct platform_device spitzscoop2_device;
|
extern struct platform_device spitzscoop2_device;
|
||||||
extern struct platform_device spitzssp_device;
|
|
||||||
extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
|
extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
|
||||||
|
|||||||
@ -116,33 +116,20 @@ struct battery_thresh spitz_battery_levels_noac[] = {
|
|||||||
{ 0, 0},
|
{ 0, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
/* MAX1111 Commands */
|
|
||||||
#define MAXCTRL_PD0 1u << 0
|
|
||||||
#define MAXCTRL_PD1 1u << 1
|
|
||||||
#define MAXCTRL_SGL 1u << 2
|
|
||||||
#define MAXCTRL_UNI 1u << 3
|
|
||||||
#define MAXCTRL_SEL_SH 4
|
|
||||||
#define MAXCTRL_STR 1u << 7
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Read MAX1111 ADC
|
* Read MAX1111 ADC
|
||||||
*/
|
*/
|
||||||
|
extern int max1111_read_channel(int);
|
||||||
|
|
||||||
int sharpsl_pm_pxa_read_max1111(int channel)
|
int sharpsl_pm_pxa_read_max1111(int channel)
|
||||||
{
|
{
|
||||||
if (machine_is_tosa()) // Ugly, better move this function into another module
|
if (machine_is_tosa()) // Ugly, better move this function into another module
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
#ifdef CONFIG_SENSORS_MAX1111
|
|
||||||
extern int max1111_read_channel(int);
|
|
||||||
|
|
||||||
/* max1111 accepts channels from 0-3, however,
|
/* max1111 accepts channels from 0-3, however,
|
||||||
* it is encoded from 0-7 here in the code.
|
* it is encoded from 0-7 here in the code.
|
||||||
*/
|
*/
|
||||||
return max1111_read_channel(channel >> 1);
|
return max1111_read_channel(channel >> 1);
|
||||||
#else
|
|
||||||
return corgi_ssp_max1111_get((channel << MAXCTRL_SEL_SH) | MAXCTRL_PD0 | MAXCTRL_PD1
|
|
||||||
| MAXCTRL_SGL | MAXCTRL_UNI | MAXCTRL_STR);
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void sharpsl_pm_pxa_init(void)
|
void sharpsl_pm_pxa_init(void)
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user