arm64: dts: ZynqMP DT changes for v5.16-v2
- Add support for Kria SOM board -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYV6e2AAKCRDKSWXLKUoM IS/BAKCZ7K9fo7UhgytlPzxnY99nm3wu9QCeK/0bs3dHFgOv3ICARrQMwrzZzuA= =jrSM -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmFkU9cACgkQmmx57+YA GNnVTRAAvViib69MVXtwdWr6e984+UaQtkIw4aiEJoVchU8P7FalAvOqfjNP9Buo Mp1SMleTBQAigF4oWE/IuukOVlI5x6sbN6qrpzb/sKQ3NBn4l/MT71UaP8mrs9of CnUzRWGJxlu7oaQX65ZCAc01jdFhyai9/o6gipP17LWHZUaGZVI6P43/17JW/EP0 QWuOyb0swgPLhUTbtSpZQdR5G5Y+b98nfOAhwYSxngSI4/xYzR2md8blt1hwVol8 3d2laoz2PtfR/LYuWFmgr95KdUza/H9EL00WRo0hrhdGItG3C7/jZ/FlqAOzME7o P+AS1YSCqIR37IJTqEckjHO8iAkeEIJGVyRDhRXlu/HJ93f2DWpMAFszv3Bphdh/ JD5qvs7tfC8oZTCI/RU7ovbcg0U9iMlAu16UfnV8Tcp37kuGOa8564nLh9YbaJxG YXPLhSkkxg9axTJX7AHcVK9W5oRszneHA0o/kDHdvqGcZQR6Sl8a6yCaS8beeTcS UbCJYry1eIthkpB3GzwFiriUVsfRHfX1qmvTcuvaNQ2viZNqVB52Ela+v2JLCpbE lbFE0eTim3kPdcQta8qFT0iJklezLFDL/cXYMl+ApongbUB2khXPn7a6/ugn3tCE tU5FtuXUHdZnYKiYaW0ucxZEkVVQRsSbiyn2QpJdPRzd8sGzj5U= =JffT -----END PGP SIGNATURE----- Merge tag 'zynqmp-dt-for-v5.16-v2' of https://github.com/Xilinx/linux-xlnx into arm/dt arm64: dts: ZynqMP DT changes for v5.16-v2 - Add support for Kria SOM board * tag 'zynqmp-dt-for-v5.16-v2' of https://github.com/Xilinx/linux-xlnx: arm64: zynqmp: Add support for Xilinx Kria SOM board Link: https://lore.kernel.org/r/9815867c-ffbb-fc9d-64b9-badee5e2862b@xilinx.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
687d67639b
@ -116,6 +116,22 @@ properties:
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- const: xlnx,zynqmp-zcu111
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- const: xlnx,zynqmp
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- description: Xilinx Kria SOMs
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items:
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- const: xlnx,zynqmp-sm-k26-rev1
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- const: xlnx,zynqmp-sm-k26-revB
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- const: xlnx,zynqmp-sm-k26-revA
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- const: xlnx,zynqmp-sm-k26
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- const: xlnx,zynqmp
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- description: Xilinx Kria SOMs (starter)
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items:
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- const: xlnx,zynqmp-smk-k26-rev1
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- const: xlnx,zynqmp-smk-k26-revB
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- const: xlnx,zynqmp-smk-k26-revA
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- const: xlnx,zynqmp-smk-k26
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- const: xlnx,zynqmp
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additionalProperties: true
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...
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@ -17,3 +17,16 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA.dtb
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sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
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sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
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smk-k26-revA-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
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smk-k26-revA-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
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dtb-$(CONFIG_ARCH_ZYNQMP) += sm-k26-revA-sck-kv-g-revA.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += sm-k26-revA-sck-kv-g-revB.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += smk-k26-revA-sm-k26-revA-sck-kv-g-revA.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += smk-k26-revA-sm-k26-revA-sck-kv-g-revB.dtb
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315
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dts
Normal file
315
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dts
Normal file
@ -0,0 +1,315 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for KV260 revA Carrier Card
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*
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* (C) Copyright 2020 - 2021, Xilinx, Inc.
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*
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* SD level shifter:
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* "A" – A01 board un-modified (NXP)
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* "Y" – A01 board modified with legacy interposer (Nexperia)
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* "Z" – A01 board modified with Diode interposer
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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/dts-v1/;
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/plugin/;
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&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
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/* u14 - 0x40 - ina260 */
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/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
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};
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&amba {
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si5332_0: si5332_0 { /* u17 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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si5332_1: si5332_1 { /* u17 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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si5332_2: si5332_2 { /* u17 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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si5332_3: si5332_3 { /* u17 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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si5332_4: si5332_4 { /* u17 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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si5332_5: si5332_5 { /* u17 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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};
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/* DP/USB 3.0 and SATA */
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&psgtr {
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status = "okay";
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/* pcie, usb3, sata */
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clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
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clock-names = "ref0", "ref1", "ref2";
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};
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&sata {
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status = "okay";
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/* SATA OOB timing settings */
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ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
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ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
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ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
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ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
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ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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phy-names = "sata-phy";
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phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
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};
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&zynqmp_dpsub {
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status = "disabled";
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phy-names = "dp-phy0", "dp-phy1";
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phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
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};
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&zynqmp_dpdma {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_default>;
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phy-names = "usb3-phy";
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phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
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/* missing usb5744 - u43 */
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};
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&dwc3_0 {
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status = "okay";
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dr_mode = "host";
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snps,usb3_lpm_capable;
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maximum-speed = "super-speed";
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};
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&sdhci1 { /* on CC with tuned parameters */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci1_default>;
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/*
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* SD 3.0 requires level shifter and this property
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* should be removed if the board has level shifter and
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* need to work in UHS mode
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*/
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no-1-8-v;
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disable-wp;
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xlnx,mio-bank = <1>;
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};
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&gem3 { /* required by spec */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem3_default>;
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
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reset-delay-us = <2>;
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phy0: ethernet-phy@1 {
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#phy-cells = <1>;
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reg = <1>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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};
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};
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};
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&pinctrl0 { /* required by spec */
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status = "okay";
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pinctrl_uart1_default: uart1-default {
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conf {
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groups = "uart1_9_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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conf-rx {
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pins = "MIO37";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO36";
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bias-disable;
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};
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mux {
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groups = "uart1_9_grp";
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function = "uart1";
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};
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};
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pinctrl_i2c1_default: i2c1-default {
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conf {
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groups = "i2c1_6_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux {
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groups = "i2c1_6_grp";
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function = "i2c1";
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};
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};
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pinctrl_i2c1_gpio: i2c1-gpio {
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conf {
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groups = "gpio0_24_grp", "gpio0_25_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux {
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groups = "gpio0_24_grp", "gpio0_25_grp";
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function = "gpio0";
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};
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};
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pinctrl_gem3_default: gem3-default {
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conf {
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groups = "ethernet3_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO70", "MIO72", "MIO74";
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bias-high-impedance;
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low-power-disable;
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};
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conf-bootstrap {
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pins = "MIO71", "MIO73", "MIO75";
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bias-disable;
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low-power-disable;
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};
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conf-tx {
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pins = "MIO64", "MIO65", "MIO66",
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"MIO67", "MIO68", "MIO69";
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bias-disable;
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low-power-enable;
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};
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conf-mdio {
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groups = "mdio3_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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};
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mux-mdio {
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function = "mdio3";
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groups = "mdio3_0_grp";
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};
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mux {
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function = "ethernet3";
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groups = "ethernet3_0_grp";
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};
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};
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pinctrl_usb0_default: usb0-default {
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conf {
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groups = "usb0_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO52", "MIO53", "MIO55";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
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"MIO60", "MIO61", "MIO62", "MIO63";
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bias-disable;
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};
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mux {
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groups = "usb0_0_grp";
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function = "usb0";
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};
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};
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pinctrl_sdhci1_default: sdhci1-default {
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conf {
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groups = "sdio1_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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};
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conf-cd {
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groups = "sdio1_cd_0_grp";
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bias-high-impedance;
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux-cd {
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groups = "sdio1_cd_0_grp";
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function = "sdio1_cd";
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};
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mux {
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groups = "sdio1_0_grp";
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function = "sdio1";
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};
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};
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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298
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dts
Normal file
298
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dts
Normal file
@ -0,0 +1,298 @@
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// SPDX-License-Identifier: GPL-2.0
|
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/*
|
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* dts file for KV260 revA Carrier Card
|
||||
*
|
||||
* (C) Copyright 2020 - 2021, Xilinx, Inc.
|
||||
*
|
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* Michal Simek <michal.simek@xilinx.com>
|
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*/
|
||||
|
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#include <dt-bindings/gpio/gpio.h>
|
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/phy/phy.h>
|
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
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|
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/dts-v1/;
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/plugin/;
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|
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&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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pinctrl-names = "default", "gpio";
|
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pinctrl-0 = <&pinctrl_i2c1_default>;
|
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
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scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
|
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sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/* u14 - 0x40 - ina260 */
|
||||
/* u43 - 0x2d - usb5744 */
|
||||
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
|
||||
};
|
||||
|
||||
&amba {
|
||||
si5332_0: si5332_0 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
si5332_1: si5332_1 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
si5332_2: si5332_2 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
si5332_3: si5332_3 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
si5332_4: si5332_4 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
si5332_5: si5332_5 { /* u17 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* DP/USB 3.0 */
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* pcie, usb3, sata */
|
||||
clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
|
||||
clock-names = "ref0", "ref1", "ref2";
|
||||
};
|
||||
|
||||
&zynqmp_dpsub {
|
||||
status = "disabled";
|
||||
phy-names = "dp-phy0", "dp-phy1";
|
||||
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
&sdhci1 { /* on CC with tuned parameters */
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
/*
|
||||
* SD 3.0 requires level shifter and this property
|
||||
* should be removed if the board has level shifter and
|
||||
* need to work in UHS mode
|
||||
*/
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
xlnx,mio-bank = <1>;
|
||||
clk-phase-sd-hs = <126>, <60>;
|
||||
clk-phase-uhs-sdr25 = <120>, <60>;
|
||||
clk-phase-uhs-ddr50 = <126>, <48>;
|
||||
};
|
||||
|
||||
&gem3 { /* required by spec */
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
|
||||
reset-delay-us = <2>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
#phy-cells = <1>;
|
||||
reg = <1>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl0 { /* required by spec */
|
||||
status = "okay";
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
conf {
|
||||
groups = "uart1_9_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO37";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO36";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "uart1_9_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
conf {
|
||||
groups = "i2c1_6_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "i2c1_6_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
conf {
|
||||
groups = "gpio0_24_grp", "gpio0_25_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "gpio0_24_grp", "gpio0_25_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO72", "MIO74";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-bootstrap {
|
||||
pins = "MIO71", "MIO73", "MIO75";
|
||||
bias-disable;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66",
|
||||
"MIO67", "MIO68", "MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
289
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
Normal file
289
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
Normal file
@ -0,0 +1,289 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP SM-K26 rev1/B/A
|
||||
*
|
||||
* (C) Copyright 2020 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP SM-K26 Rev1/B/A";
|
||||
compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
|
||||
"xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
|
||||
"xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
nvmem0 = &eeprom;
|
||||
nvmem1 = &eeprom_cc;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &dcc;
|
||||
spi0 = &qspi;
|
||||
spi1 = &spi0;
|
||||
spi2 = &spi1;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial1:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory"; /* 4GB */
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
fwuen {
|
||||
label = "fwuen";
|
||||
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
ds35-led {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
ds36-led {
|
||||
label = "vbus_det";
|
||||
gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 { /* MIO36/MIO37 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi { /* MIO 0-5 - U143 */
|
||||
status = "okay";
|
||||
flash@0 { /* MT25QU512A */
|
||||
compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <40000000>; /* 40MHz */
|
||||
partition@0 {
|
||||
label = "Image Selector";
|
||||
reg = <0x0 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "Image Selector Golden";
|
||||
reg = <0x80000 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "Persistent Register";
|
||||
reg = <0x100000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@120000 {
|
||||
label = "Persistent Register Backup";
|
||||
reg = <0x120000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@140000 {
|
||||
label = "Open_1";
|
||||
reg = <0x140000 0xC0000>; /* 768KB */
|
||||
};
|
||||
partition@200000 {
|
||||
label = "Image A (FSBL, PMU, ATF, U-Boot)";
|
||||
reg = <0x200000 0xD00000>; /* 13MB */
|
||||
};
|
||||
partition@f00000 {
|
||||
label = "ImgSel Image A Catch";
|
||||
reg = <0xF00000 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@f80000 {
|
||||
label = "Image B (FSBL, PMU, ATF, U-Boot)";
|
||||
reg = <0xF80000 0xD00000>; /* 13MB */
|
||||
};
|
||||
partition@1c80000 {
|
||||
label = "ImgSel Image B Catch";
|
||||
reg = <0x1C80000 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@1d00000 {
|
||||
label = "Open_2";
|
||||
reg = <0x1D00000 0x100000>; /* 1MB */
|
||||
};
|
||||
partition@1e00000 {
|
||||
label = "Recovery Image";
|
||||
reg = <0x1E00000 0x200000>; /* 2MB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@2000000 {
|
||||
label = "Recovery Image Backup";
|
||||
reg = <0x2000000 0x200000>; /* 2MB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@2200000 {
|
||||
label = "U-Boot storage variables";
|
||||
reg = <0x2200000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@2220000 {
|
||||
label = "U-Boot storage variables backup";
|
||||
reg = <0x2220000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@2240000 {
|
||||
label = "SHA256";
|
||||
reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@2250000 {
|
||||
label = "User";
|
||||
reg = <0x2250000 0x1db0000>; /* 29.5 MB */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
|
||||
status = "okay";
|
||||
non-removable;
|
||||
disable-wp;
|
||||
bus-width = <8>;
|
||||
xlnx,mio-bank = <0>;
|
||||
};
|
||||
|
||||
&spi1 { /* MIO6, 9-11 */
|
||||
status = "okay";
|
||||
label = "TPM";
|
||||
num-cs = <1>;
|
||||
tpm@0 { /* slm9670 - U144 */
|
||||
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <18500000>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
eeprom: eeprom@50 { /* u46 - also at address 0x58 */
|
||||
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
|
||||
reg = <0x50>;
|
||||
/* WP pin EE_WP_EN connected to slg7x644092@68 */
|
||||
};
|
||||
|
||||
eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
|
||||
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
/* da9062@30 - u170 - also at address 0x31 */
|
||||
/* da9131@33 - u167 */
|
||||
da9131: pmic@33 {
|
||||
compatible = "dlg,da9131";
|
||||
reg = <0x33>;
|
||||
regulators {
|
||||
da9131_buck1: buck1 {
|
||||
regulator-name = "da9131_buck1";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
da9131_buck2: buck2 {
|
||||
regulator-name = "da9131_buck2";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* da9130@32 - u166 */
|
||||
da9130: pmic@32 {
|
||||
compatible = "dlg,da9130";
|
||||
reg = <0x32>;
|
||||
regulators {
|
||||
da9130_buck1: buck1 {
|
||||
regulator-name = "da9130_buck1";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
|
||||
/*
|
||||
* stdp4320 - u27 FW has below two issues to be fixed in next board revision.
|
||||
* Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
|
||||
* Address conflict with slg7x644091@70 making both the devices NOT accessible.
|
||||
* With the FW fix, stdp4320 should respond to address 0x73 only.
|
||||
*/
|
||||
/* slg7x644092@68 - u169 */
|
||||
/* Also connected via JA1C as C23/C24 */
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
|
||||
"QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
|
||||
"SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
|
||||
"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
|
||||
"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
|
||||
"I2C1_SDA", "", "", "", "", /* 25 - 29 */
|
||||
"", "", "", "", "", /* 30 - 34 */
|
||||
"", "", "", "", "", /* 35 - 39 */
|
||||
"", "", "", "", "", /* 40 - 44 */
|
||||
"", "", "", "", "", /* 45 - 49 */
|
||||
"", "", "", "", "", /* 50 - 54 */
|
||||
"", "", "", "", "", /* 55 - 59 */
|
||||
"", "", "", "", "", /* 60 - 64 */
|
||||
"", "", "", "", "", /* 65 - 69 */
|
||||
"", "", "", "", "", /* 70 - 74 */
|
||||
"", "", "", /* 75 - 77, MIO end and EMIO start */
|
||||
"", "", /* 78 - 79 */
|
||||
"", "", "", "", "", /* 80 - 84 */
|
||||
"", "", "", "", "", /* 85 - 89 */
|
||||
"", "", "", "", "", /* 90 - 94 */
|
||||
"", "", "", "", "", /* 95 - 99 */
|
||||
"", "", "", "", "", /* 100 - 104 */
|
||||
"", "", "", "", "", /* 105 - 109 */
|
||||
"", "", "", "", "", /* 110 - 114 */
|
||||
"", "", "", "", "", /* 115 - 119 */
|
||||
"", "", "", "", "", /* 120 - 124 */
|
||||
"", "", "", "", "", /* 125 - 129 */
|
||||
"", "", "", "", "", /* 130 - 134 */
|
||||
"", "", "", "", "", /* 135 - 139 */
|
||||
"", "", "", "", "", /* 140 - 144 */
|
||||
"", "", "", "", "", /* 145 - 149 */
|
||||
"", "", "", "", "", /* 150 - 154 */
|
||||
"", "", "", "", "", /* 155 - 159 */
|
||||
"", "", "", "", "", /* 160 - 164 */
|
||||
"", "", "", "", "", /* 165 - 169 */
|
||||
"", "", "", ""; /* 170 - 174 */
|
||||
};
|
||||
21
arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
Normal file
21
arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
Normal file
@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
|
||||
*
|
||||
* (C) Copyright 2020 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
#include "zynqmp-sm-k26-revA.dts"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP SMK-K26 Rev1/B/A";
|
||||
compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
|
||||
"xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
|
||||
"xlnx,zynqmp";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
Loading…
x
Reference in New Issue
Block a user