perf, x86: Make a second write to performance counter if needed
On Netburst PMU we need a second write to a performance counter due to cpu erratum. A simple flag test instead of alternative instructions was choosen because wrmsrl is already a macro and if virtualization is turned on will need an additional wrapper call which is more expencise. nb: we should propably switch to jump-labels as only this facility reach the mainline. Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Robert Richter <robert.richter@amd.com> Cc: Lin Ming <ming.m.lin@intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> LKML-Reference: <20100602212304.GC5264@lenovo> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -220,6 +220,7 @@ struct x86_pmu {
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struct perf_event *event);
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struct event_constraint *event_constraints;
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void (*quirks)(void);
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int perfctr_second_write;
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int (*cpu_prepare)(int cpu);
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void (*cpu_starting)(int cpu);
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@ -925,8 +926,17 @@ x86_perf_event_set_period(struct perf_event *event)
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*/
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atomic64_set(&hwc->prev_count, (u64)-left);
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wrmsrl(hwc->event_base + idx,
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wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
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/*
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* Due to erratum on certan cpu we need
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* a second write to be sure the register
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* is updated properly
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*/
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if (x86_pmu.perfctr_second_write) {
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wrmsrl(hwc->event_base + idx,
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(u64)(-left) & x86_pmu.cntval_mask);
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}
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perf_event_update_userpage(event);
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@ -829,6 +829,15 @@ static __initconst const struct x86_pmu p4_pmu = {
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.max_period = (1ULL << 39) - 1,
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.hw_config = p4_hw_config,
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.schedule_events = p4_pmu_schedule_events,
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/*
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* This handles erratum N15 in intel doc 249199-029,
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* the counter may not be updated correctly on write
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* so we need a second write operation to do the trick
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* (the official workaround didn't work)
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*
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* the former idea is taken from OProfile code
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*/
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.perfctr_second_write = 1,
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};
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static __init int p4_pmu_init(void)
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