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perf tools changes for v6.11

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Build
 -----
 * Build each directory as a library so that depedency check for the
   python extension module can be automatic.  But it also introduces
   some trivial merge conflicts with other trees that touched perf tools
   codes.  Basically it changes perf-y to perf-util-y or similar and you
   can find the resolution in the perf-next tree here.
 
   - https://lore.kernel.org/r/Zn8HeRRX3JV2IcxQ@sirena.org.uk
   - https://lore.kernel.org/r/20240709100536.238f4d12@canb.auug.org.au
 
 * Use pkg-config to check libtraceevent and libtracefs.
 
 perf sched
 ----------
 * Add --task-name and --fuzzy-name options for `perf sched map`.  It's
   to focus on selected tasks only by removing unrelated tasks in the
   output.  It matches the task comm with the given string and the
   --fuzzy-name option allows the partial matching.
 
     $ sudo perf sched record -a sleep 1
 
     $ sudo perf sched map --task-name kworker --fuzzy-name
        .   .   .   .   -  *A0  .   .    481065.315131 secs A0 => kworker/5:2-i91:438521
        .   .   .   .   -  *-   .   .    481065.315160 secs
       *B0  .   .   .   -   .   .   .    481065.316435 secs B0 => kworker/0:0-i91:437860
       *-   .   .   .   .   .   .   .    481065.316441 secs
        .   .   .   .   .  *A0  .   .    481065.318703 secs
        .   .   .   .   .  *-   .   .    481065.318717 secs
        .   .  *C0  .   .   .   .   .    481065.320544 secs C0 => kworker/u16:30-:430186
        .   .  *-   .   .   .   .   .    481065.320555 secs
        .   .  *D0  .   .   .   .   .    481065.328524 secs D0 => kworker/2:0-kdm:429654
       *B0  .   D0  .   -   .   .   .    481065.328527 secs
       *-   .   D0  .   -   .   .   .    481065.328535 secs
        .   .  *-   .   .   .   .   .    481065.328535 secs
 
 * Fix -r/--repeat option of perf sched replay.  The documentation said
   -1 will work as infinity but it didn't accept the value.  Update the
   code and document to use 0 instead.
 
 * Fix perf sched timehist to account the delay time for preempted tasks.
 
 Perf event filtering
 --------------------
 * perf top gained filtering support on regular events using BPF like
   perf record.  Previously it was able to use it for tracepoints only.
 
 * The BPF filter now supports filtering by UID/GID.  This should be
   preferred than -u <UID> option as it's racy to scan /proc to check
   tasks for the user and fails to open an event for the task if it's
   already gone.
 
     $ sudo perf top -e cycles --filter "uid == $(id -u)"
 
 perf report
 -----------
 * Skip dummy events in the group output by default.  The --skip-empty
   option controls display of empty events without samples.  But perf
   report can force display all events in a group.  In this case, auto-
   added a dummy event (for a system-wide record) ends up in the output.
   Now it can skip those empty events even in the group display mode.
   To preserve the old behavior, run this:
 
     $ perf report --group --no-skip-empty
 
 perf stat
 ---------
 * Choose the most disaggregate option when multiple aggregation options
   are given.  It used to pick the last option in the command line but
   it can be confusing and not consistent.  Now it'll choose the smallest
   unit.
 
   For example, it'd aggregate the result per-core when the user gave
   both --per-socket and --per-core options at the same time.
 
 Internals
 ---------
 * Fix `perf bench` when some CPUs are offline.
 
 * Fix handling of JIT symbol mappings to accept "/tmp/perf-${PID}.map
   patterns only so that it can not be confused by other /tmp/perf-*
   files.
 
 * Many improvements and fixes for `perf test`.
 
 Others
 ------
 * Support some new instructions for Intel-PT.
 * Fix syscall ID mapping in perf trace.
 * Document AMD IBS PMU usages.
 * Change `perf lock info` to show map and thread info by default.
 
 Vendor JSON events
 ------------------
 * Update Intel events and metrics
 * Add i.MX9[35] DDR metrics
 
 Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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Merge tag 'perf-tools-for-v6.11-2024-07-16' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools

Pull perf tools updates from Namhyung Kim:
 "Build:

   - Build each directory as a library so that depedency check for the
     python extension module can be automatic

   - Use pkg-config to check libtraceevent and libtracefs

  perf sched:

   - Add --task-name and --fuzzy-name options for `perf sched map`

     It focuses on selected tasks only by removing unrelated tasks in
     the output. It matches the task comm with the given string and the
     --fuzzy-name option allows the partial matching:

       $ sudo perf sched record -a sleep 1

       $ sudo perf sched map --task-name kworker --fuzzy-name
          .   .   .   .   -  *A0  .   .    481065.315131 secs A0 => kworker/5:2-i91:438521
          .   .   .   .   -  *-   .   .    481065.315160 secs
         *B0  .   .   .   -   .   .   .    481065.316435 secs B0 => kworker/0:0-i91:437860
         *-   .   .   .   .   .   .   .    481065.316441 secs
          .   .   .   .   .  *A0  .   .    481065.318703 secs
          .   .   .   .   .  *-   .   .    481065.318717 secs
          .   .  *C0  .   .   .   .   .    481065.320544 secs C0 => kworker/u16:30-:430186
          .   .  *-   .   .   .   .   .    481065.320555 secs
          .   .  *D0  .   .   .   .   .    481065.328524 secs D0 => kworker/2:0-kdm:429654
         *B0  .   D0  .   -   .   .   .    481065.328527 secs
         *-   .   D0  .   -   .   .   .    481065.328535 secs
          .   .  *-   .   .   .   .   .    481065.328535 secs

   - Fix -r/--repeat option of perf sched replay

     The documentation said -1 will work as infinity but it didn't
     accept the value. Update the code and document to use 0 instead

   - Fix perf sched timehist to account the delay time for preempted
     tasks

  Perf event filtering:

   - perf top gained filtering support on regular events using BPF like
     perf record. Previously it was able to use it for tracepoints only

   - The BPF filter now supports filtering by UID/GID. This should be
     preferred than -u <UID> option as it's racy to scan /proc to check
     tasks for the user and fails to open an event for the task if it's
     already gone

       $ sudo perf top -e cycles --filter "uid == $(id -u)"

  perf report:

   - Skip dummy events in the group output by default. The --skip-empty
     option controls display of empty events without samples. But perf
     report can force display all events in a group

     In this case, auto-added a dummy event (for a system-wide record)
     ends up in the output. Now it can skip those empty events even in
     the group display mode

     To preserve the old behavior, run this:

       $ perf report --group --no-skip-empty

  perf stat:

   - Choose the most disaggregate option when multiple aggregation
     options are given. It used to pick the last option in the command
     line but it can be confusing and not consistent. Now it'll choose
     the smallest unit

     For example, it'd aggregate the result per-core when the user gave
     both --per-socket and --per-core options at the same time

  Internals:

   - Fix `perf bench` when some CPUs are offline

   - Fix handling of JIT symbol mappings to accept "/tmp/perf-${PID}.map
     patterns only so that it can not be confused by other /tmp/perf-*
     files

   - Many improvements and fixes for `perf test`

  Others:

   - Support some new instructions for Intel-PT

   - Fix syscall ID mapping in perf trace

   - Document AMD IBS PMU usages

   - Change `perf lock info` to show map and thread info by default

  Vendor JSON events:

   - Update Intel events and metrics

   - Add i.MX9[35] DDR metrics"

* tag 'perf-tools-for-v6.11-2024-07-16' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools: (125 commits)
  perf trace: Fix iteration of syscall ids in syscalltbl->entries
  perf dso: Fix address sanitizer build
  perf mem: Warn if memory events are not supported on all CPUs
  perf arm-spe: Support multiple Arm SPE PMUs
  perf build x86: Fix SC2034 error in syscalltbl.sh
  perf record: Fix memset out-of-range error
  perf sched map: Add --fuzzy-name option for fuzzy matching in task names
  perf sched map: Add support for multiple task names using CSV
  perf sched map: Add task-name option to filter the output map
  perf build: Conditionally add feature check flags for libtrace{event,fs}
  perf install: Don't propagate subdir to Documentation submake
  perf vendor events arm64:: Add i.MX95 DDR Performance Monitor metrics
  perf vendor events arm64:: Add i.MX93 DDR Performance Monitor metrics
  perf dsos: When adding a dso into sorted dsos maintain the sort order
  perf comm str: Avoid sort during insert
  perf report: Calling available function for stats printing
  perf intel-pt: Fix exclude_guest setting
  perf intel-pt: Fix aux_watermark calculation for 64-bit size
  perf sched replay: Fix -r/--repeat command line option for infinity
  perf: pmus: Remove unneeded semicolon
  ...
This commit is contained in:
Linus Torvalds 2024-07-18 14:16:35 -07:00
commit 68b5973045
581 changed files with 81371 additions and 4465 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
tools/lib/api/io.h
View File

@ -43,48 +43,55 @@ static inline void io__init(struct io *io, int fd,
io->eof = false;
}
/* Reads one character from the "io" file with similar semantics to fgetc. */
static inline int io__get_char(struct io *io)
/* Read from fd filling the buffer. Called when io->data == io->end. */
static inline int io__fill_buffer(struct io *io)
{
char *ptr = io->data;
ssize_t n;
if (io->eof)
return -1;
if (ptr == io->end) {
ssize_t n;
if (io->timeout_ms != 0) {
struct pollfd pfds[] = {
{
.fd = io->fd,
.events = POLLIN,
},
};
if (io->timeout_ms != 0) {
struct pollfd pfds[] = {
{
.fd = io->fd,
.events = POLLIN,
},
};
n = poll(pfds, 1, io->timeout_ms);
if (n == 0)
errno = ETIMEDOUT;
if (n > 0 && !(pfds[0].revents & POLLIN)) {
errno = EIO;
n = -1;
}
if (n <= 0) {
io->eof = true;
return -1;
}
n = poll(pfds, 1, io->timeout_ms);
if (n == 0)
errno = ETIMEDOUT;
if (n > 0 && !(pfds[0].revents & POLLIN)) {
errno = EIO;
n = -1;
}
n = read(io->fd, io->buf, io->buf_len);
if (n <= 0) {
io->eof = true;
return -1;
}
ptr = &io->buf[0];
io->end = &io->buf[n];
}
io->data = ptr + 1;
return *ptr;
n = read(io->fd, io->buf, io->buf_len);
if (n <= 0) {
io->eof = true;
return -1;
}
io->data = &io->buf[0];
io->end = &io->buf[n];
return 0;
}
/* Reads one character from the "io" file with similar semantics to fgetc. */
static inline int io__get_char(struct io *io)
{
if (io->data == io->end) {
int ret = io__fill_buffer(io);
if (ret)
return ret;
}
return *io->data++;
}
/* Read a hexadecimal value with no 0x prefix into the out argument hex. If the

6
tools/lib/perf/include/perf/event.h
View File

@ -77,6 +77,12 @@ struct perf_record_lost_samples {
__u64 lost;
};
#define MAX_ID_HDR_ENTRIES 6
struct perf_record_lost_samples_and_ids {
struct perf_record_lost_samples lost;
__u64 sample_ids[MAX_ID_HDR_ENTRIES];
};
/*
* PERF_FORMAT_ENABLED | PERF_FORMAT_RUNNING | PERF_FORMAT_ID | PERF_FORMAT_LOST
*/

14
tools/perf/Build
View File

@ -1,4 +1,4 @@
perf-y += builtin-bench.o
perf-bench-y += builtin-bench.o
perf-y += builtin-annotate.o
perf-y += builtin-config.o
perf-y += builtin-diff.o
@ -35,8 +35,8 @@ endif
perf-$(CONFIG_LIBELF) += builtin-probe.o
perf-y += bench/
perf-y += tests/
perf-bench-y += bench/
perf-test-y += tests/
perf-y += perf.o
@ -53,10 +53,12 @@ CFLAGS_builtin-trace.o += -DSTRACE_GROUPS_DIR="BUILD_STR($(STRACE_GROUPS_DIR_
CFLAGS_builtin-report.o += -DTIPDIR="BUILD_STR($(tipdir_SQ))"
CFLAGS_builtin-report.o += -DDOCDIR="BUILD_STR($(srcdir_SQ)/Documentation)"
perf-y += util/
perf-util-y += util/
perf-util-y += arch/
perf-y += arch/
perf-y += ui/
perf-y += scripts/
perf-test-y += arch/
perf-ui-y += ui/
perf-util-y += scripts/
gtk-y += ui/gtk/

189
tools/perf/Documentation/perf-amd-ibs.txt Normal file
View File

@ -0,0 +1,189 @@
perf-amd-ibs(1)
===============
NAME
----
perf-amd-ibs - Support for AMD Instruction-Based Sampling (IBS) with perf tool
SYNOPSIS
--------
[verse]
'perf record' -e ibs_op//
'perf record' -e ibs_fetch//
DESCRIPTION
-----------
Instruction-Based Sampling (IBS) provides precise Instruction Pointer (IP)
profiling support on AMD platforms. IBS has two independent components: IBS
Op and IBS Fetch. IBS Op sampling provides information about instruction
execution (micro-op execution to be precise) with details like d-cache
hit/miss, d-TLB hit/miss, cache miss latency, load/store data source, branch
behavior etc. IBS Fetch sampling provides information about instruction fetch
with details like i-cache hit/miss, i-TLB hit/miss, fetch latency etc. IBS is
per-smt-thread i.e. each SMT hardware thread contains standalone IBS units.
Both, IBS Op and IBS Fetch, are exposed as PMUs by Linux and can be exploited
using the Linux perf utility. The following files will be created at boot time
if IBS is supported by the hardware and kernel.
/sys/bus/event_source/devices/ibs_op/
/sys/bus/event_source/devices/ibs_fetch/
IBS Op PMU supports two events: cycles and micro ops. IBS Fetch PMU supports
one event: fetch ops.
IBS PMUs do not have user/kernel filtering capability and thus it requires
CAP_SYS_ADMIN or CAP_PERFMON privilege.
IBS VS. REGULAR CORE PMU
------------------------
IBS gives samples with precise IP, i.e. the IP recorded with IBS sample has
no skid. Whereas the IP recorded by regular core PMU will have some skid
(sample was generated at IP X but perf would record it at IP X+n). Hence,
regular core PMU might not help for profiling with instruction level
precision. Further, IBS provides additional information about the sample in
question. On the other hand, regular core PMU has it's own advantages like
plethora of events, counting mode (less interference), up to 6 parallel
counters, event grouping support, filtering capabilities etc.
Three regular core PMU events are internally forwarded to IBS Op PMU when
precise_ip attribute is set:
-e cpu-cycles:p becomes -e ibs_op//
-e r076:p becomes -e ibs_op//
-e r0C1:p becomes -e ibs_op/cnt_ctl=1/
EXAMPLES
--------
IBS Op PMU
~~~~~~~~~~
System-wide profile, cycles event, sampling period: 100000
# perf record -e ibs_op// -c 100000 -a
Per-cpu profile (cpu10), cycles event, sampling period: 100000
# perf record -e ibs_op// -c 100000 -C 10
Per-cpu profile (cpu10), cycles event, sampling freq: 1000
# perf record -e ibs_op// -F 1000 -C 10
System-wide profile, uOps event, sampling period: 100000
# perf record -e ibs_op/cnt_ctl=1/ -c 100000 -a
Same command, but also capture IBS register raw dump along with perf sample:
# perf record -e ibs_op/cnt_ctl=1/ -c 100000 -a --raw-samples
System-wide profile, uOps event, sampling period: 100000, L3MissOnly (Zen4 onward)
# perf record -e ibs_op/cnt_ctl=1,l3missonly=1/ -c 100000 -a
Per process(upstream v6.2 onward), uOps event, sampling period: 100000
# perf record -e ibs_op/cnt_ctl=1/ -c 100000 -p 1234
Per process(upstream v6.2 onward), uOps event, sampling period: 100000
# perf record -e ibs_op/cnt_ctl=1/ -c 100000 -- ls
To analyse recorded profile in aggregate mode
# perf report
/* Select a line and press 'a' to drill down at instruction level. */
To go over each sample
# perf script
Raw dump of IBS registers when profiled with --raw-samples
# perf report -D
/* Look for PERF_RECORD_SAMPLE */
Example register raw dump:
ibs_op_ctl: 000002c30006186a MaxCnt 100000 L3MissOnly 0 En 1
Val 1 CntCtl 0=cycles CurCnt 707
IbsOpRip: ffffffff8204aea7
ibs_op_data: 0000010002550001 CompToRetCtr 1 TagToRetCtr 597
BrnRet 0 RipInvalid 0 BrnFuse 0 Microcode 1
ibs_op_data2: 0000000000000013 RmtNode 1 DataSrc 3=DRAM
ibs_op_data3: 0000000031960092 LdOp 0 StOp 1 DcL1TlbMiss 0
DcL2TlbMiss 0 DcL1TlbHit2M 1 DcL1TlbHit1G 0 DcL2TlbHit2M 0
DcMiss 1 DcMisAcc 0 DcWcMemAcc 0 DcUcMemAcc 0 DcLockedOp 0
DcMissNoMabAlloc 0 DcLinAddrValid 1 DcPhyAddrValid 1
DcL2TlbHit1G 0 L2Miss 1 SwPf 0 OpMemWidth 32 bytes
OpDcMissOpenMemReqs 12 DcMissLat 0 TlbRefillLat 0
IbsDCLinAd: ff110008a5398920
IbsDCPhysAd: 00000008a5398920
IBS applied in a real world usecase
~90% regression was observed in tbench with specific scheduler hint
which was counter intuitive. IBS profile of good and bad run captured
using perf helped in identifying exact cause of the problem:
https://lore.kernel.org/r/20220921063638.2489-1-kprateek.nayak@amd.com
IBS Fetch PMU
~~~~~~~~~~~~~
Similar commands can be used with Fetch PMU as well.
System-wide profile, fetch ops event, sampling period: 100000
# perf record -e ibs_fetch// -c 100000 -a
System-wide profile, fetch ops event, sampling period: 100000, Random enable
# perf record -e ibs_fetch/rand_en=1/ -c 100000 -a
Random enable adds small degree of variability to sample period. This
helps in cases like long running loops where PMU is tagging the same
instruction over and over because of fixed sample period.
etc.
PERF MEM AND PERF C2C
---------------------
perf mem is a memory access profiler tool and perf c2c is a shared data
cacheline analyser tool. Both of them internally uses IBS Op PMU on AMD.
Below is a simple example of the perf mem tool.
# perf mem record -c 100000 -- make
# perf mem report
A normal perf mem report output will provide detailed memory access profile.
However, it can also be aggregated based on output fields. For example:
# perf mem report -F mem,sample,snoop
Samples: 3M of event 'ibs_op//', Event count (approx.): 23524876
Memory access Samples Snoop
N/A 1903343 N/A
L1 hit 1056754 N/A
L2 hit 75231 N/A
L3 hit 9496 HitM
L3 hit 2270 N/A
RAM hit 8710 N/A
Remote node, same socket RAM hit 3241 N/A
Remote core, same node Any cache hit 1572 HitM
Remote core, same node Any cache hit 514 N/A
Remote node, same socket Any cache hit 1216 HitM
Remote node, same socket Any cache hit 350 N/A
Uncached hit 18 N/A
Please refer to their man page for more detail.
SEE ALSO
--------
linkperf:perf-record[1], linkperf:perf-script[1], linkperf:perf-report[1],
linkperf:perf-mem[1], linkperf:perf-c2c[1]

4
tools/perf/Documentation/perf-kwork.txt
View File

@ -1,4 +1,4 @@
perf-kowrk(1)
perf-kwork(1)
=============
NAME
@ -35,7 +35,7 @@ There are several variants of 'perf kwork':
perf kwork top
perf kwork top -b
By default it shows the individual work events such as irq, workqeueu,
By default it shows the individual work events such as irq, workqueue,
including the run time and delay (time between raise and actually entry):
Runtime start Runtime end Cpu Kwork name Runtime Delaytime

4
tools/perf/Documentation/perf-lock.txt
View File

@ -111,11 +111,11 @@ INFO OPTIONS
-t::
--threads::
dump thread list in perf.data
dump only the thread list in perf.data
-m::
--map::
dump map of lock instances (address:name table)
dump only the map of lock instances (address:name table)
CONTENTION OPTIONS

2
tools/perf/Documentation/perf-mem.txt
View File

@ -21,7 +21,7 @@ and stores are sampled. Use the -t option to limit to loads or stores.
Note that on Intel systems the memory latency reported is the use-latency,
not the pure load (or store latency). Use latency includes any pipeline
queueing delays in addition to the memory subsystem latency.
queuing delays in addition to the memory subsystem latency.
On Arm64 this uses SPE to sample load and store operations, therefore hardware
and kernel support is required. See linkperf:perf-arm-spe[1] for a setup guide.

4
tools/perf/Documentation/perf-record.txt
View File

@ -200,7 +200,7 @@ OPTIONS
ip, id, tid, pid, cpu, time, addr, period, txn, weight, phys_addr,
code_pgsz, data_pgsz, weight1, weight2, weight3, ins_lat, retire_lat,
p_stage_cyc, mem_op, mem_lvl, mem_snoop, mem_remote, mem_lock,
mem_dtlb, mem_blk, mem_hops
mem_dtlb, mem_blk, mem_hops, uid, gid
The <operator> can be one of:
==, !=, >, >=, <, <=, &
@ -311,7 +311,7 @@ OPTIONS
User can change the size by passing the size after comma like
"--call-graph dwarf,4096".
When "fp" recording is used, perf tries to save stack enties
When "fp" recording is used, perf tries to save stack entries
up to the number specified in sysctl.kernel.perf_event_max_stack
by default. User can change the number by passing it after comma
like "--call-graph fp,32".

21
tools/perf/Documentation/perf-sched.txt
View File

@ -64,8 +64,8 @@ There are several variants of 'perf sched':
By default it shows the individual schedule events, including the wait
time (time between sched-out and next sched-in events for the task), the
task scheduling delay (time between wakeup and actually running) and run
time for the task:
task scheduling delay (time between runnable and actually running) and
run time for the task:
time cpu task name wait time sch delay run time
[tid/pid] (msec) (msec) (msec)
@ -130,6 +130,16 @@ OPTIONS for 'perf sched map'
--color-pids::
Highlight the given pids.
--task-name <task>::
Map output only for the given task name(s). Separate the
task names with a comma (without whitespace). The sched-out
time is printed and is represented by '*-' for the given
task name(s).
('-' indicates other tasks while '.' is idle).
--fuzzy-name::
Given task name(s) can be partially matched (fuzzy matching).
OPTIONS for 'perf sched timehist'
---------------------------------
-k::
@ -202,6 +212,13 @@ OPTIONS for 'perf sched timehist'
--state::
Show task state when it switched out.
OPTIONS for 'perf sched replay'
------------------------------
-r::
--repeat <n>::
repeat the workload n times (0: infinite). Default is 10.
SEE ALSO
--------
linkperf:perf-record[1]

4
tools/perf/Documentation/perf-top.txt
View File

@ -43,6 +43,10 @@ Default is to monitor all CPUS.
encoding with the layout of the event control registers as described
by entries in /sys/bus/event_source/devices/cpu/format/*.
--filter=<filter>::
Event filter. This option should follow an event selector (-e). For
syntax see linkperf:perf-record[1].
-E <entries>::
--entries=<entries>::
Display this many functions.

3
tools/perf/Documentation/perf.txt
View File

@ -82,7 +82,8 @@ linkperf:perf-stat[1], linkperf:perf-top[1],
linkperf:perf-record[1], linkperf:perf-report[1],
linkperf:perf-list[1]
linkperf:perf-annotate[1],linkperf:perf-archive[1],linkperf:perf-arm-spe[1],
linkperf:perf-amd-ibs[1], linkperf:perf-annotate[1],
linkperf:perf-archive[1], linkperf:perf-arm-spe[1],
linkperf:perf-bench[1], linkperf:perf-buildid-cache[1],
linkperf:perf-buildid-list[1], linkperf:perf-c2c[1],
linkperf:perf-config[1], linkperf:perf-data[1], linkperf:perf-diff[1],

46
tools/perf/Makefile.config
View File

@ -182,15 +182,19 @@ endif
FEATURE_CHECK_CFLAGS-libzstd := $(LIBZSTD_CFLAGS)
FEATURE_CHECK_LDFLAGS-libzstd := $(LIBZSTD_LDFLAGS)
# for linking with debug library, run like:
# make DEBUG=1 LIBTRACEEVENT_DIR=/opt/libtraceevent/
TRACEEVENTLIBS := -ltraceevent
ifdef LIBTRACEEVENT_DIR
LIBTRACEEVENT_CFLAGS := -I$(LIBTRACEEVENT_DIR)/include
LIBTRACEEVENT_LDFLAGS := -L$(LIBTRACEEVENT_DIR)/lib
ifneq ($(NO_LIBTRACEEVENT),1)
ifeq ($(call get-executable,$(PKG_CONFIG)),)
$(error Error: $(PKG_CONFIG) needed by libtraceevent is missing on this system, please install it)
endif
endif
FEATURE_CHECK_CFLAGS-libtraceevent := $(LIBTRACEEVENT_CFLAGS)
FEATURE_CHECK_LDFLAGS-libtraceevent := $(LIBTRACEEVENT_LDFLAGS) $(TRACEEVENTLIBS)
# for linking with debug library, run like:
# make DEBUG=1 PKG_CONFIG_PATH=/opt/libtraceevent/(lib|lib64)/pkgconfig
FEATURE_CHECK_CFLAGS-libtraceevent := $(shell $(PKG_CONFIG) --cflags libtraceevent 2>/dev/null)
FEATURE_CHECK_LDFLAGS-libtraceevent := $(shell $(PKG_CONFIG) --libs libtraceevent 2>/dev/null)
FEATURE_CHECK_CFLAGS-libtracefs := $(shell $(PKG_CONFIG) --cflags libtracefs 2>/dev/null)
FEATURE_CHECK_LDFLAGS-libtracefs := $(shell $(PKG_CONFIG) --libs libtracefs 2>/dev/null)
FEATURE_CHECK_CFLAGS-bpf = -I. -I$(srctree)/tools/include -I$(srctree)/tools/arch/$(SRCARCH)/include/uapi -I$(srctree)/tools/include/uapi
# include ARCH specific config
@ -210,12 +214,6 @@ ifeq ($(call get-executable,$(BISON)),)
$(error Error: $(BISON) is missing on this system, please install it)
endif
ifneq ($(NO_LIBTRACEEVENT),1)
ifeq ($(call get-executable,$(PKG_CONFIG)),)
dummy := $(error Error: $(PKG_CONFIG) needed by libtraceevent is missing on this system, please install it)
endif
endif
ifneq ($(OUTPUT),)
ifeq ($(shell expr $(shell $(BISON) --version | grep bison | sed -e 's/.\+ \([0-9]\+\).\([0-9]\+\).\([0-9]\+\)/\1\2\3/g') \>\= 371), 1)
BISON_FILE_PREFIX_MAP := --file-prefix-map=$(OUTPUT)=
@ -910,6 +908,11 @@ else
endif
CFLAGS += -DHAVE_LIBPYTHON_SUPPORT
$(call detected,CONFIG_LIBPYTHON)
ifeq ($(filter -fPIC,$(CFLAGS)),)
# Building a shared library requires position independent code.
CFLAGS += -fPIC
CXXFLAGS += -fPIC
endif
endif
endif
endif
@ -1178,10 +1181,10 @@ endif
ifneq ($(NO_LIBTRACEEVENT),1)
$(call feature_check,libtraceevent)
ifeq ($(feature-libtraceevent), 1)
CFLAGS += -DHAVE_LIBTRACEEVENT $(LIBTRACEEVENT_CFLAGS)
LDFLAGS += $(LIBTRACEEVENT_LDFLAGS)
EXTLIBS += ${TRACEEVENTLIBS}
LIBTRACEEVENT_VERSION := $(shell PKG_CONFIG_PATH=$(LIBTRACEEVENT_DIR) $(PKG_CONFIG) --modversion libtraceevent)
CFLAGS += -DHAVE_LIBTRACEEVENT
LDFLAGS += $(shell $(PKG_CONFIG) --libs-only-L libtraceevent)
EXTLIBS += $(shell $(PKG_CONFIG) --libs-only-l libtraceevent)
LIBTRACEEVENT_VERSION := $(shell $(PKG_CONFIG) --modversion libtraceevent).0.0
LIBTRACEEVENT_VERSION_1 := $(word 1, $(subst ., ,$(LIBTRACEEVENT_VERSION)))
LIBTRACEEVENT_VERSION_2 := $(word 2, $(subst ., ,$(LIBTRACEEVENT_VERSION)))
LIBTRACEEVENT_VERSION_3 := $(word 3, $(subst ., ,$(LIBTRACEEVENT_VERSION)))
@ -1194,8 +1197,10 @@ ifneq ($(NO_LIBTRACEEVENT),1)
$(call feature_check,libtracefs)
ifeq ($(feature-libtracefs), 1)
EXTLIBS += -ltracefs
LIBTRACEFS_VERSION := $(shell $(PKG_CONFIG) --modversion libtracefs)
CFLAGS += $(shell $(PKG_CONFIG) --cflags libtracefs)
LDFLAGS += $(shell $(PKG_CONFIG) --libs-only-L libtracefs)
EXTLIBS += $(shell $(PKG_CONFIG) --libs-only-l libtracefs)
LIBTRACEFS_VERSION := $(shell $(PKG_CONFIG) --modversion libtracefs).0.0
LIBTRACEFS_VERSION_1 := $(word 1, $(subst ., ,$(LIBTRACEFS_VERSION)))
LIBTRACEFS_VERSION_2 := $(word 2, $(subst ., ,$(LIBTRACEFS_VERSION)))
LIBTRACEFS_VERSION_3 := $(word 3, $(subst ., ,$(LIBTRACEFS_VERSION)))
@ -1315,7 +1320,6 @@ ifeq ($(VF),1)
$(call print_var,LIBUNWIND_DIR)
$(call print_var,LIBDW_DIR)
$(call print_var,JDIR)
$(call print_var,LIBTRACEEVENT_DIR)
ifeq ($(dwarf-post-unwind),1)
$(call feature_print_text,"DWARF post unwind library", $(dwarf-post-unwind-text)) $(info $(MSG))

85
tools/perf/Makefile.perf
View File

@ -381,14 +381,6 @@ python-clean := $(call QUIET_CLEAN, python) $(RM) -r $(PYTHON_EXTBUILD) $(OUTPUT
# Use the detected configuration
-include $(OUTPUT).config-detected
ifeq ($(CONFIG_LIBTRACEEVENT),y)
PYTHON_EXT_SRCS := $(shell grep -v ^\# util/python-ext-sources)
else
PYTHON_EXT_SRCS := $(shell grep -v ^\#\\\|util/trace-event.c\\\|util/trace-event-parse.c util/python-ext-sources)
endif
PYTHON_EXT_DEPS := util/python-ext-sources util/setup.py $(LIBAPI)
SCRIPTS = $(patsubst %.sh,%,$(SCRIPT_SH))
PROGRAMS += $(OUTPUT)perf
@ -426,10 +418,27 @@ endif
export PERL_PATH
LIBPERF_BENCH_IN := $(OUTPUT)perf-bench-in.o
LIBPERF_BENCH := $(OUTPUT)libperf-bench.a
LIBPERF_TEST_IN := $(OUTPUT)perf-test-in.o
LIBPERF_TEST := $(OUTPUT)libperf-test.a
LIBPERF_UI_IN := $(OUTPUT)perf-ui-in.o
LIBPERF_UI := $(OUTPUT)libperf-ui.a
LIBPERF_UTIL_IN := $(OUTPUT)perf-util-in.o
LIBPERF_UTIL := $(OUTPUT)libperf-util.a
LIBPMU_EVENTS_IN := $(OUTPUT)pmu-events/pmu-events-in.o
LIBPMU_EVENTS := $(OUTPUT)libpmu-events.a
PERFLIBS = $(LIBAPI) $(LIBPERF) $(LIBSUBCMD) $(LIBSYMBOL)
ifdef LIBBPF_STATIC
PERFLIBS += $(LIBBPF)
endif
PERFLIBS += $(LIBPERF_BENCH) $(LIBPERF_TEST) $(LIBPERF_UI) $(LIBPERF_UTIL)
PERFLIBS += $(LIBPMU_EVENTS)
# We choose to avoid "if .. else if .. else .. endif endif"
# because maintaining the nesting to match is a pain. If
@ -699,9 +708,9 @@ all: shell_compatibility_test $(ALL_PROGRAMS) $(LANG_BINDINGS) $(OTHER_PROGRAMS)
# Create python binding output directory if not already present
$(shell [ -d '$(OUTPUT)python' ] || mkdir -p '$(OUTPUT)python')
$(OUTPUT)python/perf$(PYTHON_EXTENSION_SUFFIX): $(PYTHON_EXT_SRCS) $(PYTHON_EXT_DEPS) $(LIBPERF) $(LIBSUBCMD)
$(OUTPUT)python/perf$(PYTHON_EXTENSION_SUFFIX): util/python.c util/setup.py $(PERFLIBS)
$(QUIET_GEN)LDSHARED="$(CC) -pthread -shared" \
CFLAGS='$(CFLAGS)' LDFLAGS='$(LDFLAGS)' \
CFLAGS='$(CFLAGS)' LDFLAGS='$(LDFLAGS) $(LIBS)' \
$(PYTHON_WORD) util/setup.py \
--quiet build_ext; \
cp $(PYTHON_EXTBUILD_LIB)perf*.so $(OUTPUT)python/
@ -718,8 +727,6 @@ strip: $(PROGRAMS) $(OUTPUT)perf
$(STRIP) $(STRIP_OPTS) $(PROGRAMS) $(OUTPUT)perf
PERF_IN := $(OUTPUT)perf-in.o
PMU_EVENTS_IN := $(OUTPUT)pmu-events/pmu-events-in.o
export NO_JEVENTS
build := -f $(srctree)/tools/build/Makefile.build dir=. obj
@ -727,12 +734,39 @@ build := -f $(srctree)/tools/build/Makefile.build dir=. obj
$(PERF_IN): prepare FORCE
$(Q)$(MAKE) $(build)=perf
$(PMU_EVENTS_IN): FORCE prepare
$(LIBPMU_EVENTS_IN): FORCE prepare
$(Q)$(MAKE) -f $(srctree)/tools/build/Makefile.build dir=pmu-events obj=pmu-events
$(OUTPUT)perf: $(PERFLIBS) $(PERF_IN) $(PMU_EVENTS_IN)
$(LIBPMU_EVENTS): $(LIBPMU_EVENTS_IN)
$(QUIET_AR)$(RM) $@ && $(AR) rcs $@ $<
$(LIBPERF_BENCH_IN): FORCE prepare
$(Q)$(MAKE) $(build)=perf-bench
$(LIBPERF_BENCH): $(LIBPERF_BENCH_IN)
$(QUIET_AR)$(RM) $@ && $(AR) rcs $@ $<
$(LIBPERF_TEST_IN): FORCE prepare
$(Q)$(MAKE) $(build)=perf-test
$(LIBPERF_TEST): $(LIBPERF_TEST_IN)
$(QUIET_AR)$(RM) $@ && $(AR) rcs $@ $<
$(LIBPERF_UI_IN): FORCE prepare
$(Q)$(MAKE) $(build)=perf-ui
$(LIBPERF_UI): $(LIBPERF_UI_IN)
$(QUIET_AR)$(RM) $@ && $(AR) rcs $@ $<
$(LIBPERF_UTIL_IN): FORCE prepare
$(Q)$(MAKE) $(build)=perf-util
$(LIBPERF_UTIL): $(LIBPERF_UTIL_IN)
$(QUIET_AR)$(RM) $@ && $(AR) rcs $@ $<
$(OUTPUT)perf: $(PERFLIBS) $(PERF_IN)
$(QUIET_LINK)$(CC) $(CFLAGS) $(LDFLAGS) \
$(PERF_IN) $(PMU_EVENTS_IN) $(LIBS) -o $@
$(PERF_IN) $(LIBS) -o $@
$(GTK_IN): FORCE prepare
$(Q)$(MAKE) $(build)=gtk
@ -892,7 +926,7 @@ $(LIBAPI)-clean:
$(LIBBPF): FORCE | $(LIBBPF_OUTPUT)
$(Q)$(MAKE) -C $(LIBBPF_DIR) FEATURES_DUMP=$(FEATURE_DUMP_EXPORT) \
O= OUTPUT=$(LIBBPF_OUTPUT)/ DESTDIR=$(LIBBPF_DESTDIR) prefix= subdir= \
$@ install_headers
EXTRA_CFLAGS="-fPIC" $@ install_headers
$(LIBBPF)-clean:
$(call QUIET_CLEAN, libbpf)
@ -1094,7 +1128,7 @@ install-python_ext:
# 'make install-doc' should call 'make -C Documentation install'
$(INSTALL_DOC_TARGETS):
$(Q)$(MAKE) -C $(DOC_DIR) O=$(OUTPUT) $(@:-doc=) ASCIIDOC_EXTRA=$(ASCIIDOC_EXTRA)
$(Q)$(MAKE) -C $(DOC_DIR) O=$(OUTPUT) $(@:-doc=) ASCIIDOC_EXTRA=$(ASCIIDOC_EXTRA) subdir=
### Cleaning rules
@ -1202,12 +1236,19 @@ endif # CONFIG_PERF_BPF_SKEL
bpf-skel-clean:
$(call QUIET_CLEAN, bpf-skel) $(RM) -r $(SKEL_TMP_OUT) $(SKELETONS) $(SKEL_OUT)/vmlinux.h
clean:: $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clean $(LIBSYMBOL)-clean $(LIBPERF)-clean arm64-sysreg-defs-clean fixdep-clean python-clean bpf-skel-clean tests-coresight-targets-clean
$(call QUIET_CLEAN, core-objs) $(RM) $(LIBPERF_A) $(OUTPUT)perf-archive $(OUTPUT)perf-iostat $(LANG_BINDINGS)
$(Q)find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.cmd' -delete -o -name '\.*.d' -delete -o -name '*.shellcheck_log' -delete
clean:: $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clean $(LIBSYMBOL)-clean $(LIBPERF)-clean \
arm64-sysreg-defs-clean fixdep-clean python-clean bpf-skel-clean \
tests-coresight-targets-clean
$(call QUIET_CLEAN, core-objs) $(RM) $(LIBPERF_A) $(OUTPUT)perf-archive \
$(OUTPUT)perf-iostat $(LANG_BINDINGS)
$(Q)find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '*.a' -delete -o \
-name '\.*.cmd' -delete -o -name '\.*.d' -delete -o -name '*.shellcheck_log' -delete
$(Q)$(RM) $(OUTPUT).config-detected
$(call QUIET_CLEAN, core-progs) $(RM) $(ALL_PROGRAMS) perf perf-read-vdso32 perf-read-vdsox32 $(OUTPUT)$(LIBJVMTI).so
$(call QUIET_CLEAN, core-gen) $(RM) *.spec *.pyc *.pyo */*.pyc */*.pyo $(OUTPUT)common-cmds.h TAGS tags cscope* $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)FEATURE-DUMP $(OUTPUT)util/*-bison* $(OUTPUT)util/*-flex* \
$(call QUIET_CLEAN, core-progs) $(RM) $(ALL_PROGRAMS) perf perf-read-vdso32 \
perf-read-vdsox32 $(OUTPUT)$(LIBJVMTI).so
$(call QUIET_CLEAN, core-gen) $(RM) *.spec *.pyc *.pyo */*.pyc */*.pyo \
$(OUTPUT)common-cmds.h TAGS tags cscope* $(OUTPUT)PERF-VERSION-FILE \
$(OUTPUT)FEATURE-DUMP $(OUTPUT)util/*-bison* $(OUTPUT)util/*-flex* \
$(OUTPUT)util/intel-pt-decoder/inat-tables.c \
$(OUTPUT)tests/llvm-src-{base,kbuild,prologue,relocation}.c \
$(OUTPUT)pmu-events/pmu-events.c \

5
tools/perf/arch/Build
View File

@ -1,2 +1,3 @@
perf-y += common.o
perf-y += $(SRCARCH)/
perf-util-y += common.o
perf-test-y += $(SRCARCH)/
perf-util-y += $(SRCARCH)/

4
tools/perf/arch/arm/Build
View File

@ -1,2 +1,2 @@
perf-y += util/
perf-$(CONFIG_DWARF_UNWIND) += tests/
perf-util-y += util/
perf-test-$(CONFIG_DWARF_UNWIND) += tests/

8
tools/perf/arch/arm/tests/Build
View File

@ -1,5 +1,5 @@
perf-y += regs_load.o
perf-y += dwarf-unwind.o
perf-y += vectors-page.o
perf-test-y += regs_load.o
perf-test-y += dwarf-unwind.o
perf-test-y += vectors-page.o
perf-y += arch-tests.o
perf-test-y += arch-tests.o

10
tools/perf/arch/arm/util/Build
View File

@ -1,8 +1,8 @@
perf-y += perf_regs.o
perf-util-y += perf_regs.o
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-util-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
perf-util-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
perf-util-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
perf-$(CONFIG_AUXTRACE) += pmu.o auxtrace.o cs-etm.o
perf-util-$(CONFIG_AUXTRACE) += pmu.o auxtrace.o cs-etm.o

12
tools/perf/arch/arm/util/pmu.c
View File

@ -11,12 +11,15 @@
#include "arm-spe.h"
#include "hisi-ptt.h"
#include "../../../util/cpumap.h"
#include "../../../util/pmu.h"
#include "../../../util/cs-etm.h"
#include "../../arm64/util/mem-events.h"
void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused)
void perf_pmu__arch_init(struct perf_pmu *pmu)
{
struct perf_cpu_map *intersect;
#ifdef HAVE_AUXTRACE_SUPPORT
if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) {
/* add ETM default config here */
@ -27,12 +30,15 @@ void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused)
pmu->selectable = true;
pmu->is_uncore = false;
pmu->perf_event_attr_init_default = arm_spe_pmu_default_config;
if (!strcmp(pmu->name, "arm_spe_0"))
if (strstarts(pmu->name, "arm_spe_"))
pmu->mem_events = perf_mem_events_arm;
} else if (strstarts(pmu->name, HISI_PTT_PMU_NAME)) {
pmu->selectable = true;
#endif
}
#endif
/* Workaround some ARM PMU's failing to correctly set CPU maps for online processors. */
intersect = perf_cpu_map__intersect(cpu_map__online(), pmu->cpus);
perf_cpu_map__put(pmu->cpus);
pmu->cpus = intersect;
}

4
tools/perf/arch/arm64/Build
View File

@ -1,2 +1,2 @@
perf-y += util/
perf-y += tests/
perf-util-y += util/
perf-test-y += tests/

8
tools/perf/arch/arm64/tests/Build
View File

@ -1,5 +1,5 @@
perf-y += regs_load.o
perf-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o
perf-test-y += regs_load.o
perf-test-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o
perf-y += arch-tests.o
perf-y += cpuid-match.o
perf-test-y += arch-tests.o
perf-test-y += cpuid-match.o

20
tools/perf/arch/arm64/util/Build
View File

@ -1,14 +1,14 @@
perf-y += header.o
perf-y += machine.o
perf-y += perf_regs.o
perf-y += tsc.o
perf-y += pmu.o
perf-$(CONFIG_LIBTRACEEVENT) += kvm-stat.o
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
perf-util-y += header.o
perf-util-y += machine.o
perf-util-y += perf_regs.o
perf-util-y += tsc.o
perf-util-y += pmu.o
perf-util-$(CONFIG_LIBTRACEEVENT) += kvm-stat.o
perf-util-$(CONFIG_DWARF) += dwarf-regs.o
perf-util-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
perf-util-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
perf-$(CONFIG_AUXTRACE) += ../../arm/util/pmu.o \
perf-util-$(CONFIG_AUXTRACE) += ../../arm/util/pmu.o \
../../arm/util/auxtrace.o \
../../arm/util/cs-etm.o \
arm-spe.o mem-events.o hisi-ptt.o

2
tools/perf/arch/csky/Build
View File

@ -1 +1 @@
perf-y += util/
perf-util-y += util/

6
tools/perf/arch/csky/util/Build
View File

@ -1,4 +1,4 @@
perf-y += perf_regs.o
perf-util-y += perf_regs.o
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
perf-util-$(CONFIG_DWARF) += dwarf-regs.o
perf-util-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o

2
tools/perf/arch/loongarch/Build
View File

@ -1 +1 @@
perf-y += util/
perf-util-y += util/

8
tools/perf/arch/loongarch/util/Build
View File

@ -1,5 +1,5 @@
perf-y += perf_regs.o
perf-util-y += perf_regs.o
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
perf-util-$(CONFIG_DWARF) += dwarf-regs.o
perf-util-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
perf-util-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o

2
tools/perf/arch/mips/Build
View File

@ -1 +1 @@
perf-y += util/
perf-util-y += util/

6
tools/perf/arch/mips/util/Build
View File

@ -1,3 +1,3 @@
perf-y += perf_regs.o
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
perf-util-y += perf_regs.o
perf-util-$(CONFIG_DWARF) += dwarf-regs.o
perf-util-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o

4
tools/perf/arch/powerpc/Build
View File

@ -1,2 +1,2 @@
perf-y += util/
perf-y += tests/
perf-util-y += util/
perf-test-y += tests/

6
tools/perf/arch/powerpc/tests/Build
View File

@ -1,4 +1,4 @@
perf-$(CONFIG_DWARF_UNWIND) += regs_load.o
perf-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o
perf-test-$(CONFIG_DWARF_UNWIND) += regs_load.o
perf-test-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o
perf-y += arch-tests.o
perf-test-y += arch-tests.o

24
tools/perf/arch/powerpc/util/Build
View File

@ -1,14 +1,14 @@
perf-y += header.o
perf-$(CONFIG_LIBTRACEEVENT) += kvm-stat.o
perf-y += perf_regs.o
perf-y += mem-events.o
perf-y += pmu.o
perf-y += sym-handling.o
perf-y += evsel.o
perf-y += event.o
perf-util-y += header.o
perf-util-$(CONFIG_LIBTRACEEVENT) += kvm-stat.o
perf-util-y += perf_regs.o
perf-util-y += mem-events.o
perf-util-y += pmu.o
perf-util-y += sym-handling.o
perf-util-y += evsel.o
perf-util-y += event.o
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_DWARF) += skip-callchain-idx.o
perf-util-$(CONFIG_DWARF) += dwarf-regs.o
perf-util-$(CONFIG_DWARF) += skip-callchain-idx.o
perf-$(CONFIG_LIBUNWIND) += unwind-libunwind.o
perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
perf-util-$(CONFIG_LIBUNWIND) += unwind-libunwind.o
perf-util-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o

8
tools/perf/arch/powerpc/util/skip-callchain-idx.c
View File

@ -159,9 +159,9 @@ static int check_return_addr(struct dso *dso, u64 map_start, Dwarf_Addr pc)
Dwarf_Addr start = pc;
Dwarf_Addr end = pc;
bool signalp;
const char *exec_file = dso->long_name;
const char *exec_file = dso__long_name(dso);
dwfl = dso->dwfl;
dwfl = RC_CHK_ACCESS(dso)->dwfl;
if (!dwfl) {
dwfl = dwfl_begin(&offline_callbacks);
@ -183,7 +183,7 @@ static int check_return_addr(struct dso *dso, u64 map_start, Dwarf_Addr pc)
dwfl_end(dwfl);
goto out;
}
dso->dwfl = dwfl;
RC_CHK_ACCESS(dso)->dwfl = dwfl;
}
mod = dwfl_addrmodule(dwfl, pc);
@ -267,7 +267,7 @@ int arch_skip_callchain_idx(struct thread *thread, struct ip_callchain *chain)
rc = check_return_addr(dso, map__start(al.map), ip);
pr_debug("[DSO %s, sym %s, ip 0x%" PRIx64 "] rc %d\n",
dso->long_name, al.sym->name, ip, rc);
dso__long_name(dso), al.sym->name, ip, rc);
if (rc == 0) {
/*

2
tools/perf/arch/riscv/Build
View File

@ -1 +1 @@
perf-y += util/
perf-util-y += util/

8
tools/perf/arch/riscv/util/Build
View File

@ -1,5 +1,5 @@
perf-y += perf_regs.o
perf-y += header.o
perf-util-y += perf_regs.o
perf-util-y += header.o
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
perf-util-$(CONFIG_DWARF) += dwarf-regs.o
perf-util-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o

2
tools/perf/arch/s390/Build
View File

@ -1 +1 @@
perf-y += util/
perf-util-y += util/

16
tools/perf/arch/s390/util/Build
View File

@ -1,11 +1,11 @@
perf-y += header.o
perf-$(CONFIG_LIBTRACEEVENT) += kvm-stat.o
perf-y += perf_regs.o
perf-util-y += header.o
perf-util-$(CONFIG_LIBTRACEEVENT) += kvm-stat.o
perf-util-y += perf_regs.o
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
perf-util-$(CONFIG_DWARF) += dwarf-regs.o
perf-util-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
perf-y += machine.o
perf-y += pmu.o
perf-util-y += machine.o
perf-util-y += pmu.o
perf-$(CONFIG_AUXTRACE) += auxtrace.o
perf-util-$(CONFIG_AUXTRACE) += auxtrace.o

2
tools/perf/arch/sh/Build
View File

@ -1 +1 @@
perf-y += util/
perf-util-y += util/

2
tools/perf/arch/sh/util/Build
View File

@ -1 +1 @@
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-util-$(CONFIG_DWARF) += dwarf-regs.o

2
tools/perf/arch/sparc/Build
View File

@ -1 +1 @@
perf-y += util/
perf-util-y += util/

2
tools/perf/arch/sparc/util/Build
View File

@ -1 +1 @@
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-util-$(CONFIG_DWARF) += dwarf-regs.o

6
tools/perf/arch/x86/Build
View File

@ -1,5 +1,5 @@
perf-y += util/
perf-y += tests/
perf-util-y += util/
perf-test-y += tests/
ifdef SHELLCHECK
SHELL_TESTS := entry/syscalls/syscalltbl.sh
@ -13,4 +13,4 @@ $(OUTPUT)%.shellcheck_log: %
$(call rule_mkdir)
$(Q)$(call echo-cmd,test)shellcheck -a -S warning "$<" > $@ || (cat $@ && rm $@ && false)
perf-y += $(TEST_LOGS)
perf-test-y += $(TEST_LOGS)

4
tools/perf/arch/x86/entry/syscalls/syscalltbl.sh
View File

@ -24,7 +24,9 @@ sorted_table=$(mktemp /tmp/syscalltbl.XXXXXX)
grep '^[0-9]' "$in" | sort -n > $sorted_table
max_nr=0
while read nr _abi name entry _compat; do
# the params are: nr abi name entry compat
# use _ for intentionally unused variables according to SC2034
while read nr _ name _ _; do
if [ $nr -ge 512 ] ; then # discard compat sycalls
break
fi

20
tools/perf/arch/x86/tests/Build
View File

@ -1,15 +1,15 @@
perf-$(CONFIG_DWARF_UNWIND) += regs_load.o
perf-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o
perf-test-$(CONFIG_DWARF_UNWIND) += regs_load.o
perf-test-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o
perf-y += arch-tests.o
perf-y += sample-parsing.o
perf-y += hybrid.o
perf-$(CONFIG_AUXTRACE) += intel-pt-test.o
perf-test-y += arch-tests.o
perf-test-y += sample-parsing.o
perf-test-y += hybrid.o
perf-test-$(CONFIG_AUXTRACE) += intel-pt-test.o
ifeq ($(CONFIG_EXTRA_TESTS),y)
perf-$(CONFIG_AUXTRACE) += insn-x86.o
perf-test-$(CONFIG_AUXTRACE) += insn-x86.o
endif
perf-$(CONFIG_X86_64) += bp-modify.o
perf-y += amd-ibs-via-core-pmu.o
perf-test-$(CONFIG_X86_64) += bp-modify.o
perf-test-y += amd-ibs-via-core-pmu.o
ifdef SHELLCHECK
SHELL_TESTS := gen-insn-x86-dat.sh
@ -23,4 +23,4 @@ $(OUTPUT)%.shellcheck_log: %
$(call rule_mkdir)
$(Q)$(call echo-cmd,test)shellcheck -a -S warning "$<" > $@ || (cat $@ && rm $@ && false)
perf-y += $(TEST_LOGS)
perf-test-y += $(TEST_LOGS)

116
tools/perf/arch/x86/tests/insn-x86-dat-32.c
View File

@ -3107,6 +3107,122 @@
"62 f5 7c 08 2e ca \tvucomish %xmm2,%xmm1",},
{{0x62, 0xf5, 0x7c, 0x08, 0x2e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7c 08 2e 8c c8 78 56 34 12 \tvucomish 0x12345678(%eax,%ecx,8),%xmm1",},
{{0xf3, 0x0f, 0x38, 0xdc, 0xd1, }, 5, 0, "", "",
"f3 0f 38 dc d1 \tloadiwkey %xmm1,%xmm2",},
{{0xf3, 0x0f, 0x38, 0xfa, 0xd0, }, 5, 0, "", "",
"f3 0f 38 fa d0 \tencodekey128 %eax,%edx",},
{{0xf3, 0x0f, 0x38, 0xfb, 0xd0, }, 5, 0, "", "",
"f3 0f 38 fb d0 \tencodekey256 %eax,%edx",},
{{0xf3, 0x0f, 0x38, 0xdc, 0x5a, 0x77, }, 6, 0, "", "",
"f3 0f 38 dc 5a 77 \taesenc128kl 0x77(%edx),%xmm3",},
{{0xf3, 0x0f, 0x38, 0xde, 0x5a, 0x77, }, 6, 0, "", "",
"f3 0f 38 de 5a 77 \taesenc256kl 0x77(%edx),%xmm3",},
{{0xf3, 0x0f, 0x38, 0xdd, 0x5a, 0x77, }, 6, 0, "", "",
"f3 0f 38 dd 5a 77 \taesdec128kl 0x77(%edx),%xmm3",},
{{0xf3, 0x0f, 0x38, 0xdf, 0x5a, 0x77, }, 6, 0, "", "",
"f3 0f 38 df 5a 77 \taesdec256kl 0x77(%edx),%xmm3",},
{{0xf3, 0x0f, 0x38, 0xd8, 0x42, 0x77, }, 6, 0, "", "",
"f3 0f 38 d8 42 77 \taesencwide128kl 0x77(%edx)",},
{{0xf3, 0x0f, 0x38, 0xd8, 0x52, 0x77, }, 6, 0, "", "",
"f3 0f 38 d8 52 77 \taesencwide256kl 0x77(%edx)",},
{{0xf3, 0x0f, 0x38, 0xd8, 0x4a, 0x77, }, 6, 0, "", "",
"f3 0f 38 d8 4a 77 \taesdecwide128kl 0x77(%edx)",},
{{0xf3, 0x0f, 0x38, 0xd8, 0x5a, 0x77, }, 6, 0, "", "",
"f3 0f 38 d8 5a 77 \taesdecwide256kl 0x77(%edx)",},
{{0x0f, 0x38, 0xfc, 0x08, }, 4, 0, "", "",
"0f 38 fc 08 \taadd %ecx,(%eax)",},
{{0x0f, 0x38, 0xfc, 0x15, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 38 fc 15 78 56 34 12 \taadd %edx,0x12345678",},
{{0x0f, 0x38, 0xfc, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"0f 38 fc 94 c8 78 56 34 12 \taadd %edx,0x12345678(%eax,%ecx,8)",},
{{0x66, 0x0f, 0x38, 0xfc, 0x08, }, 5, 0, "", "",
"66 0f 38 fc 08 \taand %ecx,(%eax)",},
{{0x66, 0x0f, 0x38, 0xfc, 0x15, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 38 fc 15 78 56 34 12 \taand %edx,0x12345678",},
{{0x66, 0x0f, 0x38, 0xfc, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"66 0f 38 fc 94 c8 78 56 34 12 \taand %edx,0x12345678(%eax,%ecx,8)",},
{{0xf2, 0x0f, 0x38, 0xfc, 0x08, }, 5, 0, "", "",
"f2 0f 38 fc 08 \taor %ecx,(%eax)",},
{{0xf2, 0x0f, 0x38, 0xfc, 0x15, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 38 fc 15 78 56 34 12 \taor %edx,0x12345678",},
{{0xf2, 0x0f, 0x38, 0xfc, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"f2 0f 38 fc 94 c8 78 56 34 12 \taor %edx,0x12345678(%eax,%ecx,8)",},
{{0xf3, 0x0f, 0x38, 0xfc, 0x08, }, 5, 0, "", "",
"f3 0f 38 fc 08 \taxor %ecx,(%eax)",},
{{0xf3, 0x0f, 0x38, 0xfc, 0x15, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 38 fc 15 78 56 34 12 \taxor %edx,0x12345678",},
{{0xf3, 0x0f, 0x38, 0xfc, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"f3 0f 38 fc 94 c8 78 56 34 12 \taxor %edx,0x12345678(%eax,%ecx,8)",},
{{0xc4, 0xe2, 0x7a, 0xb1, 0x31, }, 5, 0, "", "",
"c4 e2 7a b1 31 \tvbcstnebf162ps (%ecx),%xmm6",},
{{0xc4, 0xe2, 0x79, 0xb1, 0x31, }, 5, 0, "", "",
"c4 e2 79 b1 31 \tvbcstnesh2ps (%ecx),%xmm6",},
{{0xc4, 0xe2, 0x7a, 0xb0, 0x31, }, 5, 0, "", "",
"c4 e2 7a b0 31 \tvcvtneebf162ps (%ecx),%xmm6",},
{{0xc4, 0xe2, 0x79, 0xb0, 0x31, }, 5, 0, "", "",
"c4 e2 79 b0 31 \tvcvtneeph2ps (%ecx),%xmm6",},
{{0xc4, 0xe2, 0x7b, 0xb0, 0x31, }, 5, 0, "", "",
"c4 e2 7b b0 31 \tvcvtneobf162ps (%ecx),%xmm6",},
{{0xc4, 0xe2, 0x78, 0xb0, 0x31, }, 5, 0, "", "",
"c4 e2 78 b0 31 \tvcvtneoph2ps (%ecx),%xmm6",},
{{0x62, 0xf2, 0x7e, 0x08, 0x72, 0xf1, }, 6, 0, "", "",
"62 f2 7e 08 72 f1 \tvcvtneps2bf16 %xmm1,%xmm6",},
{{0xc4, 0xe2, 0x6b, 0x50, 0xd9, }, 5, 0, "", "",
"c4 e2 6b 50 d9 \tvpdpbssd %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6b, 0x51, 0xd9, }, 5, 0, "", "",
"c4 e2 6b 51 d9 \tvpdpbssds %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6a, 0x50, 0xd9, }, 5, 0, "", "",
"c4 e2 6a 50 d9 \tvpdpbsud %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6a, 0x51, 0xd9, }, 5, 0, "", "",
"c4 e2 6a 51 d9 \tvpdpbsuds %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x68, 0x50, 0xd9, }, 5, 0, "", "",
"c4 e2 68 50 d9 \tvpdpbuud %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x68, 0x51, 0xd9, }, 5, 0, "", "",
"c4 e2 68 51 d9 \tvpdpbuuds %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6a, 0xd2, 0xd9, }, 5, 0, "", "",
"c4 e2 6a d2 d9 \tvpdpwsud %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6a, 0xd3, 0xd9, }, 5, 0, "", "",
"c4 e2 6a d3 d9 \tvpdpwsuds %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x69, 0xd2, 0xd9, }, 5, 0, "", "",
"c4 e2 69 d2 d9 \tvpdpwusd %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x69, 0xd3, 0xd9, }, 5, 0, "", "",
"c4 e2 69 d3 d9 \tvpdpwusds %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x68, 0xd2, 0xd9, }, 5, 0, "", "",
"c4 e2 68 d2 d9 \tvpdpwuud %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x68, 0xd3, 0xd9, }, 5, 0, "", "",
"c4 e2 68 d3 d9 \tvpdpwuuds %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0xed, 0x08, 0xb5, 0xd9, }, 6, 0, "", "",
"62 f2 ed 08 b5 d9 \tvpmadd52huq %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0xed, 0x08, 0xb4, 0xd9, }, 6, 0, "", "",
"62 f2 ed 08 b4 d9 \tvpmadd52luq %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x7f, 0xcc, 0xd1, }, 5, 0, "", "",
"c4 e2 7f cc d1 \tvsha512msg1 %xmm1,%ymm2",},
{{0xc4, 0xe2, 0x7f, 0xcd, 0xd1, }, 5, 0, "", "",
"c4 e2 7f cd d1 \tvsha512msg2 %ymm1,%ymm2",},
{{0xc4, 0xe2, 0x6f, 0xcb, 0xd9, }, 5, 0, "", "",
"c4 e2 6f cb d9 \tvsha512rnds2 %xmm1,%ymm2,%ymm3",},
{{0xc4, 0xe2, 0x68, 0xda, 0xd9, }, 5, 0, "", "",
"c4 e2 68 da d9 \tvsm3msg1 %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x69, 0xda, 0xd9, }, 5, 0, "", "",
"c4 e2 69 da d9 \tvsm3msg2 %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe3, 0x69, 0xde, 0xd9, 0xa1, }, 6, 0, "", "",
"c4 e3 69 de d9 a1 \tvsm3rnds2 $0xa1,%xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6a, 0xda, 0xd9, }, 5, 0, "", "",
"c4 e2 6a da d9 \tvsm4key4 %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6b, 0xda, 0xd9, }, 5, 0, "", "",
"c4 e2 6b da d9 \tvsm4rnds4 %xmm1,%xmm2,%xmm3",},
{{0x0f, 0x0d, 0x00, }, 3, 0, "", "",
"0f 0d 00 \tprefetch (%eax)",},
{{0x0f, 0x18, 0x08, }, 3, 0, "", "",
"0f 18 08 \tprefetcht0 (%eax)",},
{{0x0f, 0x18, 0x10, }, 3, 0, "", "",
"0f 18 10 \tprefetcht1 (%eax)",},
{{0x0f, 0x18, 0x18, }, 3, 0, "", "",
"0f 18 18 \tprefetcht2 (%eax)",},
{{0x0f, 0x18, 0x00, }, 3, 0, "", "",
"0f 18 00 \tprefetchnta (%eax)",},
{{0x0f, 0x01, 0xc6, }, 3, 0, "", "",
"0f 01 c6 \twrmsrns",},
{{0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x00, }, 6, 0, "", "",
"f3 0f 3a f0 c0 00 \threset $0x0",},
{{0x0f, 0x01, 0xe8, }, 3, 0, "", "",

1026
tools/perf/arch/x86/tests/insn-x86-dat-64.c
View File

File diff suppressed because it is too large Load Diff

597
tools/perf/arch/x86/tests/insn-x86-dat-src.c
View File

@ -2628,6 +2628,512 @@ int main(void)
asm volatile("vucomish 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vucomish 0x12345678(%eax,%ecx,8), %xmm1");
/* Key Locker */
asm volatile("loadiwkey %xmm1, %xmm2");
asm volatile("encodekey128 %eax, %edx");
asm volatile("encodekey256 %eax, %edx");
asm volatile("aesenc128kl 0x77(%rdx), %xmm3");
asm volatile("aesenc256kl 0x77(%rdx), %xmm3");
asm volatile("aesdec128kl 0x77(%rdx), %xmm3");
asm volatile("aesdec256kl 0x77(%rdx), %xmm3");
asm volatile("aesencwide128kl 0x77(%rdx)");
asm volatile("aesencwide256kl 0x77(%rdx)");
asm volatile("aesdecwide128kl 0x77(%rdx)");
asm volatile("aesdecwide256kl 0x77(%rdx)");
/* Remote Atomic Operations */
asm volatile("aadd %ecx,(%rax)");
asm volatile("aadd %edx,(%r8)");
asm volatile("aadd %edx,0x12345678(%rax,%rcx,8)");
asm volatile("aadd %edx,0x12345678(%r8,%rcx,8)");
asm volatile("aadd %rcx,(%rax)");
asm volatile("aadd %rdx,(%r8)");
asm volatile("aadd %rdx,(0x12345678)");
asm volatile("aadd %rdx,0x12345678(%rax,%rcx,8)");
asm volatile("aadd %rdx,0x12345678(%r8,%rcx,8)");
asm volatile("aand %ecx,(%rax)");
asm volatile("aand %edx,(%r8)");
asm volatile("aand %edx,0x12345678(%rax,%rcx,8)");
asm volatile("aand %edx,0x12345678(%r8,%rcx,8)");
asm volatile("aand %rcx,(%rax)");
asm volatile("aand %rdx,(%r8)");
asm volatile("aand %rdx,(0x12345678)");
asm volatile("aand %rdx,0x12345678(%rax,%rcx,8)");
asm volatile("aand %rdx,0x12345678(%r8,%rcx,8)");
asm volatile("aor %ecx,(%rax)");
asm volatile("aor %edx,(%r8)");
asm volatile("aor %edx,0x12345678(%rax,%rcx,8)");
asm volatile("aor %edx,0x12345678(%r8,%rcx,8)");
asm volatile("aor %rcx,(%rax)");
asm volatile("aor %rdx,(%r8)");
asm volatile("aor %rdx,(0x12345678)");
asm volatile("aor %rdx,0x12345678(%rax,%rcx,8)");
asm volatile("aor %rdx,0x12345678(%r8,%rcx,8)");
asm volatile("axor %ecx,(%rax)");
asm volatile("axor %edx,(%r8)");
asm volatile("axor %edx,0x12345678(%rax,%rcx,8)");
asm volatile("axor %edx,0x12345678(%r8,%rcx,8)");
asm volatile("axor %rcx,(%rax)");
asm volatile("axor %rdx,(%r8)");
asm volatile("axor %rdx,(0x12345678)");
asm volatile("axor %rdx,0x12345678(%rax,%rcx,8)");
asm volatile("axor %rdx,0x12345678(%r8,%rcx,8)");
/* VEX CMPxxXADD */
asm volatile("cmpbexadd %ebx,%ecx,(%r9)");
asm volatile("cmpbxadd %ebx,%ecx,(%r9)");
asm volatile("cmplexadd %ebx,%ecx,(%r9)");
asm volatile("cmplxadd %ebx,%ecx,(%r9)");
asm volatile("cmpnbexadd %ebx,%ecx,(%r9)");
asm volatile("cmpnbxadd %ebx,%ecx,(%r9)");
asm volatile("cmpnlexadd %ebx,%ecx,(%r9)");
asm volatile("cmpnlxadd %ebx,%ecx,(%r9)");
asm volatile("cmpnoxadd %ebx,%ecx,(%r9)");
asm volatile("cmpnpxadd %ebx,%ecx,(%r9)");
asm volatile("cmpnsxadd %ebx,%ecx,(%r9)");
asm volatile("cmpnzxadd %ebx,%ecx,(%r9)");
asm volatile("cmpoxadd %ebx,%ecx,(%r9)");
asm volatile("cmppxadd %ebx,%ecx,(%r9)");
asm volatile("cmpsxadd %ebx,%ecx,(%r9)");
asm volatile("cmpzxadd %ebx,%ecx,(%r9)");
/* Pre-fetch */
asm volatile("prefetch (%rax)");
asm volatile("prefetcht0 (%rax)");
asm volatile("prefetcht1 (%rax)");
asm volatile("prefetcht2 (%rax)");
asm volatile("prefetchnta (%rax)");
asm volatile("prefetchit0 0x12345678(%rip)");
asm volatile("prefetchit1 0x12345678(%rip)");
/* MSR List */
asm volatile("rdmsrlist");
asm volatile("wrmsrlist");
/* User Read/Write MSR */
asm volatile("urdmsr %rdx,%rax");
asm volatile("urdmsr %rdx,%r22");
asm volatile("urdmsr $0x7f,%r12");
asm volatile("uwrmsr %rax,%rdx");
asm volatile("uwrmsr %r22,%rdx");
asm volatile("uwrmsr %r12,$0x7f");
/* AVX NE Convert */
asm volatile("vbcstnebf162ps (%rcx),%xmm6");
asm volatile("vbcstnesh2ps (%rcx),%xmm6");
asm volatile("vcvtneebf162ps (%rcx),%xmm6");
asm volatile("vcvtneeph2ps (%rcx),%xmm6");
asm volatile("vcvtneobf162ps (%rcx),%xmm6");
asm volatile("vcvtneoph2ps (%rcx),%xmm6");
asm volatile("vcvtneps2bf16 %xmm1,%xmm6");
/* FRED */
asm volatile("erets"); /* Expecting: erets indirect 0 */
asm volatile("eretu"); /* Expecting: eretu indirect 0 */
/* AMX Complex */
asm volatile("tcmmimfp16ps %tmm1,%tmm2,%tmm3");
asm volatile("tcmmrlfp16ps %tmm1,%tmm2,%tmm3");
/* AMX FP16 */
asm volatile("tdpfp16ps %tmm1,%tmm2,%tmm3");
/* REX2 */
asm volatile("test $0x5, %r18b");
asm volatile("test $0x5, %r18d");
asm volatile("test $0x5, %r18");
asm volatile("test $0x5, %r18w");
asm volatile("imull %eax, %r14d");
asm volatile("imull %eax, %r17d");
asm volatile("punpckldq (%r18), %mm2");
asm volatile("leal (%rax), %r16d");
asm volatile("leal (%rax), %r31d");
asm volatile("leal (,%r16), %eax");
asm volatile("leal (,%r31), %eax");
asm volatile("leal (%r16), %eax");
asm volatile("leal (%r31), %eax");
asm volatile("leaq (%rax), %r15");
asm volatile("leaq (%rax), %r16");
asm volatile("leaq (%r15), %rax");
asm volatile("leaq (%r16), %rax");
asm volatile("leaq (,%r15), %rax");
asm volatile("leaq (,%r16), %rax");
asm volatile("add (%r16), %r8");
asm volatile("add (%r16), %r15");
asm volatile("mov (,%r9), %r16");
asm volatile("mov (,%r14), %r16");
asm volatile("sub (%r10), %r31");
asm volatile("sub (%r13), %r31");
asm volatile("leal 1(%r16, %r21), %eax");
asm volatile("leal 1(%r16, %r26), %r31d");
asm volatile("leal 129(%r21, %r9), %eax");
asm volatile("leal 129(%r26, %r9), %r31d");
/*
* Have to use .byte for jmpabs because gas does not support the
* mnemonic for some reason, but then it also gets the source line wrong
* with .byte, so the following is a workaround.
*/
asm volatile(""); /* Expecting: jmp indirect 0 */
asm volatile(".byte 0xd5, 0x00, 0xa1, 0xef, 0xcd, 0xab, 0x90, 0x78, 0x56, 0x34, 0x12");
asm volatile("pushp %rbx");
asm volatile("pushp %r16");
asm volatile("pushp %r31");
asm volatile("popp %r31");
asm volatile("popp %r16");
asm volatile("popp %rbx");
/* APX */
asm volatile("bextr %r25d,%edx,%r10d");
asm volatile("bextr %r25d,0x123(%r31,%rax,4),%edx");
asm volatile("bextr %r31,%r15,%r11");
asm volatile("bextr %r31,0x123(%r31,%rax,4),%r15");
asm volatile("blsi %r25d,%edx");
asm volatile("blsi %r31,%r15");
asm volatile("blsi 0x123(%r31,%rax,4),%r25d");
asm volatile("blsi 0x123(%r31,%rax,4),%r31");
asm volatile("blsmsk %r25d,%edx");
asm volatile("blsmsk %r31,%r15");
asm volatile("blsmsk 0x123(%r31,%rax,4),%r25d");
asm volatile("blsmsk 0x123(%r31,%rax,4),%r31");
asm volatile("blsr %r25d,%edx");
asm volatile("blsr %r31,%r15");
asm volatile("blsr 0x123(%r31,%rax,4),%r25d");
asm volatile("blsr 0x123(%r31,%rax,4),%r31");
asm volatile("bzhi %r25d,%edx,%r10d");
asm volatile("bzhi %r25d,0x123(%r31,%rax,4),%edx");
asm volatile("bzhi %r31,%r15,%r11");
asm volatile("bzhi %r31,0x123(%r31,%rax,4),%r15");
asm volatile("cmpbexadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpbexadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmpbxadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpbxadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmplxadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmplxadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmpnbexadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpnbexadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmpnbxadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpnbxadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmpnlexadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpnlexadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmpnlxadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpnlxadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmpnoxadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpnoxadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmpnpxadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpnpxadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmpnsxadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpnsxadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmpnzxadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpnzxadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmpoxadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpoxadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmppxadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmppxadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmpsxadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpsxadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("cmpzxadd %r25d,%edx,0x123(%r31,%rax,4)");
asm volatile("cmpzxadd %r31,%r15,0x123(%r31,%rax,4)");
asm volatile("crc32q %r31, %r22");
asm volatile("crc32q (%r31), %r22");
asm volatile("crc32b %r19b, %r17");
asm volatile("crc32b %r19b, %r21d");
asm volatile("crc32b (%r19),%ebx");
asm volatile("crc32l %r31d, %r23d");
asm volatile("crc32l (%r31), %r23d");
asm volatile("crc32w %r31w, %r21d");
asm volatile("crc32w (%r31),%r21d");
asm volatile("crc32 %rax, %r18");
asm volatile("enqcmd 0x123(%r31d,%eax,4),%r25d");
asm volatile("enqcmd 0x123(%r31,%rax,4),%r31");
asm volatile("enqcmds 0x123(%r31d,%eax,4),%r25d");
asm volatile("enqcmds 0x123(%r31,%rax,4),%r31");
asm volatile("invept 0x123(%r31,%rax,4),%r31");
asm volatile("invpcid 0x123(%r31,%rax,4),%r31");
asm volatile("invvpid 0x123(%r31,%rax,4),%r31");
asm volatile("kmovb %k5,%r25d");
asm volatile("kmovb %k5,0x123(%r31,%rax,4)");
asm volatile("kmovb %r25d,%k5");
asm volatile("kmovb 0x123(%r31,%rax,4),%k5");
asm volatile("kmovd %k5,%r25d");
asm volatile("kmovd %k5,0x123(%r31,%rax,4)");
asm volatile("kmovd %r25d,%k5");
asm volatile("kmovd 0x123(%r31,%rax,4),%k5");
asm volatile("kmovq %k5,%r31");
asm volatile("kmovq %k5,0x123(%r31,%rax,4)");
asm volatile("kmovq %r31,%k5");
asm volatile("kmovq 0x123(%r31,%rax,4),%k5");
asm volatile("kmovw %k5,%r25d");
asm volatile("kmovw %k5,0x123(%r31,%rax,4)");
asm volatile("kmovw %r25d,%k5");
asm volatile("kmovw 0x123(%r31,%rax,4),%k5");
asm volatile("ldtilecfg 0x123(%r31,%rax,4)");
asm volatile("movbe %r18w,%ax");
asm volatile("movbe %r15w,%ax");
asm volatile("movbe %r18w,0x123(%r16,%rax,4)");
asm volatile("movbe %r18w,0x123(%r31,%rax,4)");
asm volatile("movbe %r25d,%edx");
asm volatile("movbe %r15d,%edx");
asm volatile("movbe %r25d,0x123(%r16,%rax,4)");
asm volatile("movbe %r31,%r15");
asm volatile("movbe %r8,%r15");
asm volatile("movbe %r31,0x123(%r16,%rax,4)");
asm volatile("movbe %r31,0x123(%r31,%rax,4)");
asm volatile("movbe 0x123(%r16,%rax,4),%r31");
asm volatile("movbe 0x123(%r31,%rax,4),%r18w");
asm volatile("movbe 0x123(%r31,%rax,4),%r25d");
asm volatile("movdir64b 0x123(%r31d,%eax,4),%r25d");
asm volatile("movdir64b 0x123(%r31,%rax,4),%r31");
asm volatile("movdiri %r25d,0x123(%r31,%rax,4)");
asm volatile("movdiri %r31,0x123(%r31,%rax,4)");
asm volatile("pdep %r25d,%edx,%r10d");
asm volatile("pdep %r31,%r15,%r11");
asm volatile("pdep 0x123(%r31,%rax,4),%r25d,%edx");
asm volatile("pdep 0x123(%r31,%rax,4),%r31,%r15");
asm volatile("pext %r25d,%edx,%r10d");
asm volatile("pext %r31,%r15,%r11");
asm volatile("pext 0x123(%r31,%rax,4),%r25d,%edx");
asm volatile("pext 0x123(%r31,%rax,4),%r31,%r15");
asm volatile("shlx %r25d,%edx,%r10d");
asm volatile("shlx %r25d,0x123(%r31,%rax,4),%edx");
asm volatile("shlx %r31,%r15,%r11");
asm volatile("shlx %r31,0x123(%r31,%rax,4),%r15");
asm volatile("shrx %r25d,%edx,%r10d");
asm volatile("shrx %r25d,0x123(%r31,%rax,4),%edx");
asm volatile("shrx %r31,%r15,%r11");
asm volatile("shrx %r31,0x123(%r31,%rax,4),%r15");
asm volatile("sttilecfg 0x123(%r31,%rax,4)");
asm volatile("tileloadd 0x123(%r31,%rax,4),%tmm6");
asm volatile("tileloaddt1 0x123(%r31,%rax,4),%tmm6");
asm volatile("tilestored %tmm6,0x123(%r31,%rax,4)");
asm volatile("vbroadcastf128 (%r16),%ymm3");
asm volatile("vbroadcasti128 (%r16),%ymm3");
asm volatile("vextractf128 $1,%ymm3,(%r16)");
asm volatile("vextracti128 $1,%ymm3,(%r16)");
asm volatile("vinsertf128 $1,(%r16),%ymm3,%ymm8");
asm volatile("vinserti128 $1,(%r16),%ymm3,%ymm8");
asm volatile("vroundpd $1,(%r24),%xmm6");
asm volatile("vroundps $2,(%r24),%xmm6");
asm volatile("vroundsd $3,(%r24),%xmm6,%xmm3");
asm volatile("vroundss $4,(%r24),%xmm6,%xmm3");
asm volatile("wrssd %r25d,0x123(%r31,%rax,4)");
asm volatile("wrssq %r31,0x123(%r31,%rax,4)");
asm volatile("wrussd %r25d,0x123(%r31,%rax,4)");
asm volatile("wrussq %r31,0x123(%r31,%rax,4)");
/* APX new data destination */
asm volatile("adc $0x1234,%ax,%r30w");
asm volatile("adc %r15b,%r17b,%r18b");
asm volatile("adc %r15d,(%r8),%r18d");
asm volatile("adc (%r15,%rax,1),%r16b,%r8b");
asm volatile("adc (%r15,%rax,1),%r16w,%r8w");
asm volatile("adcl $0x11,(%r19,%rax,4),%r20d");
asm volatile("adcx %r15d,%r8d,%r18d");
asm volatile("adcx (%r15,%r31,1),%r8");
asm volatile("adcx (%r15,%r31,1),%r8d,%r18d");
asm volatile("add $0x1234,%ax,%r30w");
asm volatile("add $0x12344433,%r15,%r16");
asm volatile("add $0x34,%r13b,%r17b");
asm volatile("add $0xfffffffff4332211,%rax,%r8");
asm volatile("add %r31,%r8,%r16");
asm volatile("add %r31,(%r8),%r16");
asm volatile("add %r31,(%r8,%r16,8),%r16");
asm volatile("add %r31b,%r8b,%r16b");
asm volatile("add %r31d,%r8d,%r16d");
asm volatile("add %r31w,%r8w,%r16w");
asm volatile("add (%r31),%r8,%r16");
asm volatile("add 0x9090(%r31,%r16,1),%r8,%r16");
asm volatile("addb %r31b,%r8b,%r16b");
asm volatile("addl %r31d,%r8d,%r16d");
asm volatile("addl $0x11,(%r19,%rax,4),%r20d");
asm volatile("addq %r31,%r8,%r16");
asm volatile("addq $0x12344433,(%r15,%rcx,4),%r16");
asm volatile("addw %r31w,%r8w,%r16w");
asm volatile("adox %r15d,%r8d,%r18d");
asm volatile("{load} add %r31,%r8,%r16");
asm volatile("{store} add %r31,%r8,%r16");
asm volatile("adox (%r15,%r31,1),%r8");
asm volatile("adox (%r15,%r31,1),%r8d,%r18d");
asm volatile("and $0x1234,%ax,%r30w");
asm volatile("and %r15b,%r17b,%r18b");
asm volatile("and %r15d,(%r8),%r18d");
asm volatile("and (%r15,%rax,1),%r16b,%r8b");
asm volatile("and (%r15,%rax,1),%r16w,%r8w");
asm volatile("andl $0x11,(%r19,%rax,4),%r20d");
asm volatile("cmova 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovae 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovb 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovbe 0x90909090(%eax),%edx,%r8d");
asm volatile("cmove 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovg 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovge 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovl 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovle 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovne 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovno 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovnp 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovns 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovo 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovp 0x90909090(%eax),%edx,%r8d");
asm volatile("cmovs 0x90909090(%eax),%edx,%r8d");
asm volatile("dec %rax,%r17");
asm volatile("decb (%r31,%r12,1),%r8b");
asm volatile("imul 0x909(%rax,%r31,8),%rdx,%r25");
asm volatile("imul 0x90909(%eax),%edx,%r8d");
asm volatile("inc %r31,%r16");
asm volatile("inc %r31,%r8");
asm volatile("inc %rax,%rbx");
asm volatile("neg %rax,%r17");
asm volatile("negb (%r31,%r12,1),%r8b");
asm volatile("not %rax,%r17");
asm volatile("notb (%r31,%r12,1),%r8b");
asm volatile("or $0x1234,%ax,%r30w");
asm volatile("or %r15b,%r17b,%r18b");
asm volatile("or %r15d,(%r8),%r18d");
asm volatile("or (%r15,%rax,1),%r16b,%r8b");
asm volatile("or (%r15,%rax,1),%r16w,%r8w");
asm volatile("orl $0x11,(%r19,%rax,4),%r20d");
asm volatile("rcl $0x2,%r12b,%r31b");
asm volatile("rcl %cl,%r16b,%r8b");
asm volatile("rclb $0x1,(%rax),%r31b");
asm volatile("rcll $0x2,(%rax),%r31d");
asm volatile("rclw $0x1,(%rax),%r31w");
asm volatile("rclw %cl,(%r19,%rax,4),%r31w");
asm volatile("rcr $0x2,%r12b,%r31b");
asm volatile("rcr %cl,%r16b,%r8b");
asm volatile("rcrb $0x1,(%rax),%r31b");
asm volatile("rcrl $0x2,(%rax),%r31d");
asm volatile("rcrw $0x1,(%rax),%r31w");
asm volatile("rcrw %cl,(%r19,%rax,4),%r31w");
asm volatile("rol $0x2,%r12b,%r31b");
asm volatile("rol %cl,%r16b,%r8b");
asm volatile("rolb $0x1,(%rax),%r31b");
asm volatile("roll $0x2,(%rax),%r31d");
asm volatile("rolw $0x1,(%rax),%r31w");
asm volatile("rolw %cl,(%r19,%rax,4),%r31w");
asm volatile("ror $0x2,%r12b,%r31b");
asm volatile("ror %cl,%r16b,%r8b");
asm volatile("rorb $0x1,(%rax),%r31b");
asm volatile("rorl $0x2,(%rax),%r31d");
asm volatile("rorw $0x1,(%rax),%r31w");
asm volatile("rorw %cl,(%r19,%rax,4),%r31w");
asm volatile("sar $0x2,%r12b,%r31b");
asm volatile("sar %cl,%r16b,%r8b");
asm volatile("sarb $0x1,(%rax),%r31b");
asm volatile("sarl $0x2,(%rax),%r31d");
asm volatile("sarw $0x1,(%rax),%r31w");
asm volatile("sarw %cl,(%r19,%rax,4),%r31w");
asm volatile("sbb $0x1234,%ax,%r30w");
asm volatile("sbb %r15b,%r17b,%r18b");
asm volatile("sbb %r15d,(%r8),%r18d");
asm volatile("sbb (%r15,%rax,1),%r16b,%r8b");
asm volatile("sbb (%r15,%rax,1),%r16w,%r8w");
asm volatile("sbbl $0x11,(%r19,%rax,4),%r20d");
asm volatile("shl $0x2,%r12b,%r31b");
asm volatile("shl $0x2,%r12b,%r31b");
asm volatile("shl %cl,%r16b,%r8b");
asm volatile("shl %cl,%r16b,%r8b");
asm volatile("shlb $0x1,(%rax),%r31b");
asm volatile("shlb $0x1,(%rax),%r31b");
asm volatile("shld $0x1,%r12,(%rax),%r31");
asm volatile("shld $0x2,%r15d,(%rax),%r31d");
asm volatile("shld $0x2,%r8w,%r12w,%r31w");
asm volatile("shld %cl,%r12,%r16,%r8");
asm volatile("shld %cl,%r13w,(%r19,%rax,4),%r31w");
asm volatile("shld %cl,%r9w,(%rax),%r31w");
asm volatile("shll $0x2,(%rax),%r31d");
asm volatile("shll $0x2,(%rax),%r31d");
asm volatile("shlw $0x1,(%rax),%r31w");
asm volatile("shlw $0x1,(%rax),%r31w");
asm volatile("shlw %cl,(%r19,%rax,4),%r31w");
asm volatile("shlw %cl,(%r19,%rax,4),%r31w");
asm volatile("shr $0x2,%r12b,%r31b");
asm volatile("shr %cl,%r16b,%r8b");
asm volatile("shrb $0x1,(%rax),%r31b");
asm volatile("shrd $0x1,%r12,(%rax),%r31");
asm volatile("shrd $0x2,%r15d,(%rax),%r31d");
asm volatile("shrd $0x2,%r8w,%r12w,%r31w");
asm volatile("shrd %cl,%r12,%r16,%r8");
asm volatile("shrd %cl,%r13w,(%r19,%rax,4),%r31w");
asm volatile("shrd %cl,%r9w,(%rax),%r31w");
asm volatile("shrl $0x2,(%rax),%r31d");
asm volatile("shrw $0x1,(%rax),%r31w");
asm volatile("shrw %cl,(%r19,%rax,4),%r31w");
asm volatile("sub $0x1234,%ax,%r30w");
asm volatile("sub %r15b,%r17b,%r18b");
asm volatile("sub %r15d,(%r8),%r18d");
asm volatile("sub (%r15,%rax,1),%r16b,%r8b");
asm volatile("sub (%r15,%rax,1),%r16w,%r8w");
asm volatile("subl $0x11,(%r19,%rax,4),%r20d");
asm volatile("xor $0x1234,%ax,%r30w");
asm volatile("xor %r15b,%r17b,%r18b");
asm volatile("xor %r15d,(%r8),%r18d");
asm volatile("xor (%r15,%rax,1),%r16b,%r8b");
asm volatile("xor (%r15,%rax,1),%r16w,%r8w");
asm volatile("xorl $0x11,(%r19,%rax,4),%r20d");
/* APX suppress status flags */
asm volatile("{nf} add %bl,%dl,%r8b");
asm volatile("{nf} add %dx,%ax,%r9w");
asm volatile("{nf} add 0x123(%r8,%rax,4),%bl,%dl");
asm volatile("{nf} add 0x123(%r8,%rax,4),%dx,%ax");
asm volatile("{nf} or %bl,%dl,%r8b");
asm volatile("{nf} or %dx,%ax,%r9w");
asm volatile("{nf} or 0x123(%r8,%rax,4),%bl,%dl");
asm volatile("{nf} or 0x123(%r8,%rax,4),%dx,%ax");
asm volatile("{nf} and %bl,%dl,%r8b");
asm volatile("{nf} and %dx,%ax,%r9w");
asm volatile("{nf} and 0x123(%r8,%rax,4),%bl,%dl");
asm volatile("{nf} and 0x123(%r8,%rax,4),%dx,%ax");
asm volatile("{nf} shld $0x7b,%dx,%ax,%r9w");
asm volatile("{nf} sub %bl,%dl,%r8b");
asm volatile("{nf} sub %dx,%ax,%r9w");
asm volatile("{nf} sub 0x123(%r8,%rax,4),%bl,%dl");
asm volatile("{nf} sub 0x123(%r8,%rax,4),%dx,%ax");
asm volatile("{nf} shrd $0x7b,%dx,%ax,%r9w");
asm volatile("{nf} xor %bl,%dl,%r8b");
asm volatile("{nf} xor %r31,%r31");
asm volatile("{nf} xor 0x123(%r8,%rax,4),%bl,%dl");
asm volatile("{nf} xor 0x123(%r8,%rax,4),%dx,%ax");
asm volatile("{nf} imul $0xff90,%r9,%r15");
asm volatile("{nf} imul $0x7b,%r9,%r15");
asm volatile("{nf} xor $0x7b,%bl,%dl");
asm volatile("{nf} xor $0x7b,%dx,%ax");
asm volatile("{nf} popcnt %r9,%r31");
asm volatile("{nf} shld %cl,%dx,%ax,%r9w");
asm volatile("{nf} shrd %cl,%dx,%ax,%r9w");
asm volatile("{nf} imul %r9,%r31,%r11");
asm volatile("{nf} sar $0x7b,%bl,%dl");
asm volatile("{nf} sar $0x7b,%dx,%ax");
asm volatile("{nf} sar $1,%bl,%dl");
asm volatile("{nf} sar $1,%dx,%ax");
asm volatile("{nf} sar %cl,%bl,%dl");
asm volatile("{nf} sar %cl,%dx,%ax");
asm volatile("{nf} andn %r9,%r31,%r11");
asm volatile("{nf} blsi %r9,%r31");
asm volatile("{nf} tzcnt %r9,%r31");
asm volatile("{nf} lzcnt %r9,%r31");
asm volatile("{nf} idiv %bl");
asm volatile("{nf} idiv %dx");
asm volatile("{nf} dec %bl,%dl");
asm volatile("{nf} dec %dx,%ax");
#else /* #ifdef __x86_64__ */
/* bound r32, mem (same op code as EVEX prefix) */
@ -4848,6 +5354,97 @@ int main(void)
#endif /* #ifndef __x86_64__ */
/* Key Locker */
asm volatile(" loadiwkey %xmm1, %xmm2");
asm volatile(" encodekey128 %eax, %edx");
asm volatile(" encodekey256 %eax, %edx");
asm volatile(" aesenc128kl 0x77(%edx), %xmm3");
asm volatile(" aesenc256kl 0x77(%edx), %xmm3");
asm volatile(" aesdec128kl 0x77(%edx), %xmm3");
asm volatile(" aesdec256kl 0x77(%edx), %xmm3");
asm volatile(" aesencwide128kl 0x77(%edx)");
asm volatile(" aesencwide256kl 0x77(%edx)");
asm volatile(" aesdecwide128kl 0x77(%edx)");
asm volatile(" aesdecwide256kl 0x77(%edx)");
/* Remote Atomic Operations */
asm volatile("aadd %ecx,(%eax)");
asm volatile("aadd %edx,(0x12345678)");
asm volatile("aadd %edx,0x12345678(%eax,%ecx,8)");
asm volatile("aand %ecx,(%eax)");
asm volatile("aand %edx,(0x12345678)");
asm volatile("aand %edx,0x12345678(%eax,%ecx,8)");
asm volatile("aor %ecx,(%eax)");
asm volatile("aor %edx,(0x12345678)");
asm volatile("aor %edx,0x12345678(%eax,%ecx,8)");
asm volatile("axor %ecx,(%eax)");
asm volatile("axor %edx,(0x12345678)");
asm volatile("axor %edx,0x12345678(%eax,%ecx,8)");
/* AVX NE Convert */
asm volatile("vbcstnebf162ps (%ecx),%xmm6");
asm volatile("vbcstnesh2ps (%ecx),%xmm6");
asm volatile("vcvtneebf162ps (%ecx),%xmm6");
asm volatile("vcvtneeph2ps (%ecx),%xmm6");
asm volatile("vcvtneobf162ps (%ecx),%xmm6");
asm volatile("vcvtneoph2ps (%ecx),%xmm6");
asm volatile("vcvtneps2bf16 %xmm1,%xmm6");
/* AVX VNNI INT16 */
asm volatile("vpdpbssd %xmm1,%xmm2,%xmm3");
asm volatile("vpdpbssds %xmm1,%xmm2,%xmm3");
asm volatile("vpdpbsud %xmm1,%xmm2,%xmm3");
asm volatile("vpdpbsuds %xmm1,%xmm2,%xmm3");
asm volatile("vpdpbuud %xmm1,%xmm2,%xmm3");
asm volatile("vpdpbuuds %xmm1,%xmm2,%xmm3");
asm volatile("vpdpwsud %xmm1,%xmm2,%xmm3");
asm volatile("vpdpwsuds %xmm1,%xmm2,%xmm3");
asm volatile("vpdpwusd %xmm1,%xmm2,%xmm3");
asm volatile("vpdpwusds %xmm1,%xmm2,%xmm3");
asm volatile("vpdpwuud %xmm1,%xmm2,%xmm3");
asm volatile("vpdpwuuds %xmm1,%xmm2,%xmm3");
/* AVX IFMA */
asm volatile("vpmadd52huq %xmm1,%xmm2,%xmm3");
asm volatile("vpmadd52luq %xmm1,%xmm2,%xmm3");
/* AVX SHA512 */
asm volatile("vsha512msg1 %xmm1,%ymm2");
asm volatile("vsha512msg2 %ymm1,%ymm2");
asm volatile("vsha512rnds2 %xmm1,%ymm2,%ymm3");
/* AVX SM3 */
asm volatile("vsm3msg1 %xmm1,%xmm2,%xmm3");
asm volatile("vsm3msg2 %xmm1,%xmm2,%xmm3");
asm volatile("vsm3rnds2 $0xa1,%xmm1,%xmm2,%xmm3");
/* AVX SM4 */
asm volatile("vsm4key4 %xmm1,%xmm2,%xmm3");
asm volatile("vsm4rnds4 %xmm1,%xmm2,%xmm3");
/* Pre-fetch */
asm volatile("prefetch (%eax)");
asm volatile("prefetcht0 (%eax)");
asm volatile("prefetcht1 (%eax)");
asm volatile("prefetcht2 (%eax)");
asm volatile("prefetchnta (%eax)");
/* Non-serializing write MSR */
asm volatile("wrmsrns");
/* Prediction history reset */
asm volatile("hreset $0");

42
tools/perf/arch/x86/util/Build
View File

@ -1,24 +1,24 @@
perf-y += header.o
perf-y += tsc.o
perf-y += pmu.o
perf-$(CONFIG_LIBTRACEEVENT) += kvm-stat.o
perf-y += perf_regs.o
perf-y += topdown.o
perf-y += machine.o
perf-y += event.o
perf-y += evlist.o
perf-y += mem-events.o
perf-y += evsel.o
perf-y += iostat.o
perf-y += env.o
perf-util-y += header.o
perf-util-y += tsc.o
perf-util-y += pmu.o
perf-util-$(CONFIG_LIBTRACEEVENT) += kvm-stat.o
perf-util-y += perf_regs.o
perf-util-y += topdown.o
perf-util-y += machine.o
perf-util-y += event.o
perf-util-y += evlist.o
perf-util-y += mem-events.o
perf-util-y += evsel.o
perf-util-y += iostat.o
perf-util-y += env.o
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_BPF_PROLOGUE) += dwarf-regs.o
perf-util-$(CONFIG_DWARF) += dwarf-regs.o
perf-util-$(CONFIG_BPF_PROLOGUE) += dwarf-regs.o
perf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
perf-util-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
perf-util-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
perf-$(CONFIG_AUXTRACE) += auxtrace.o
perf-$(CONFIG_AUXTRACE) += archinsn.o
perf-$(CONFIG_AUXTRACE) += intel-pt.o
perf-$(CONFIG_AUXTRACE) += intel-bts.o
perf-util-$(CONFIG_AUXTRACE) += auxtrace.o
perf-util-$(CONFIG_AUXTRACE) += archinsn.o
perf-util-$(CONFIG_AUXTRACE) += intel-pt.o
perf-util-$(CONFIG_AUXTRACE) += intel-bts.o

15
tools/perf/arch/x86/util/intel-pt.c
View File

@ -32,6 +32,7 @@
#include "../../../util/tsc.h"
#include <internal/lib.h> // page_size
#include "../../../util/intel-pt.h"
#include <api/fs/fs.h>
#define KiB(x) ((x) * 1024)
#define MiB(x) ((x) * 1024 * 1024)
@ -428,6 +429,16 @@ static int intel_pt_track_switches(struct evlist *evlist)
}
#endif
static bool intel_pt_exclude_guest(void)
{
int pt_mode;
if (sysfs__read_int("module/kvm_intel/parameters/pt_mode", &pt_mode))
pt_mode = 0;
return pt_mode == 1;
}
static void intel_pt_valid_str(char *str, size_t len, u64 valid)
{
unsigned int val, last = 0, state = 1;
@ -620,6 +631,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr,
}
evsel->core.attr.freq = 0;
evsel->core.attr.sample_period = 1;
evsel->core.attr.exclude_guest = intel_pt_exclude_guest();
evsel->no_aux_samples = true;
evsel->needs_auxtrace_mmap = true;
intel_pt_evsel = evsel;
@ -758,7 +770,8 @@ static int intel_pt_recording_options(struct auxtrace_record *itr,
}
if (!opts->auxtrace_snapshot_mode && !opts->auxtrace_sample_mode) {
u32 aux_watermark = opts->auxtrace_mmap_pages * page_size / 4;
size_t aw = opts->auxtrace_mmap_pages * (size_t)page_size / 4;
u32 aux_watermark = aw > UINT_MAX ? UINT_MAX : aw;
intel_pt_evsel->core.attr.aux_watermark = aux_watermark;
}

2
tools/perf/arch/xtensa/Build
View File

@ -1 +1 @@
perf-y += util/
perf-util-y += util/

46
tools/perf/bench/Build
View File

@ -1,25 +1,25 @@
perf-y += sched-messaging.o
perf-y += sched-pipe.o
perf-y += sched-seccomp-notify.o
perf-y += syscall.o
perf-y += mem-functions.o
perf-y += futex-hash.o
perf-y += futex-wake.o
perf-y += futex-wake-parallel.o
perf-y += futex-requeue.o
perf-y += futex-lock-pi.o
perf-y += epoll-wait.o
perf-y += epoll-ctl.o
perf-y += synthesize.o
perf-y += kallsyms-parse.o
perf-y += find-bit-bench.o
perf-y += inject-buildid.o
perf-y += evlist-open-close.o
perf-y += breakpoint.o
perf-y += pmu-scan.o
perf-y += uprobe.o
perf-bench-y += sched-messaging.o
perf-bench-y += sched-pipe.o
perf-bench-y += sched-seccomp-notify.o
perf-bench-y += syscall.o
perf-bench-y += mem-functions.o
perf-bench-y += futex-hash.o
perf-bench-y += futex-wake.o
perf-bench-y += futex-wake-parallel.o
perf-bench-y += futex-requeue.o
perf-bench-y += futex-lock-pi.o
perf-bench-y += epoll-wait.o
perf-bench-y += epoll-ctl.o
perf-bench-y += synthesize.o
perf-bench-y += kallsyms-parse.o
perf-bench-y += find-bit-bench.o
perf-bench-y += inject-buildid.o
perf-bench-y += evlist-open-close.o
perf-bench-y += breakpoint.o
perf-bench-y += pmu-scan.o
perf-bench-y += uprobe.o
perf-$(CONFIG_X86_64) += mem-memcpy-x86-64-asm.o
perf-$(CONFIG_X86_64) += mem-memset-x86-64-asm.o
perf-bench-$(CONFIG_X86_64) += mem-memcpy-x86-64-asm.o
perf-bench-$(CONFIG_X86_64) += mem-memset-x86-64-asm.o
perf-$(CONFIG_NUMA) += numa.o
perf-bench-$(CONFIG_NUMA) += numa.o

2
tools/perf/bench/epoll-ctl.c
View File

@ -232,7 +232,7 @@ static int do_threads(struct worker *worker, struct perf_cpu_map *cpu)
if (!noaffinity)
pthread_attr_init(&thread_attr);
nrcpus = perf_cpu_map__nr(cpu);
nrcpus = cpu__max_cpu().cpu;
cpuset = CPU_ALLOC(nrcpus);
BUG_ON(!cpuset);
size = CPU_ALLOC_SIZE(nrcpus);

2
tools/perf/bench/epoll-wait.c
View File

@ -309,7 +309,7 @@ static int do_threads(struct worker *worker, struct perf_cpu_map *cpu)
if (!noaffinity)
pthread_attr_init(&thread_attr);
nrcpus = perf_cpu_map__nr(cpu);
nrcpus = cpu__max_cpu().cpu;
cpuset = CPU_ALLOC(nrcpus);
BUG_ON(!cpuset);
size = CPU_ALLOC_SIZE(nrcpus);

2
tools/perf/bench/futex-hash.c
View File

@ -174,7 +174,7 @@ int bench_futex_hash(int argc, const char **argv)
pthread_attr_init(&thread_attr);
gettimeofday(&bench__start, NULL);
nrcpus = perf_cpu_map__nr(cpu);
nrcpus = cpu__max_cpu().cpu;
cpuset = CPU_ALLOC(nrcpus);
BUG_ON(!cpuset);
size = CPU_ALLOC_SIZE(nrcpus);

2
tools/perf/bench/futex-lock-pi.c
View File

@ -122,7 +122,7 @@ static void create_threads(struct worker *w, struct perf_cpu_map *cpu)
{
cpu_set_t *cpuset;
unsigned int i;
int nrcpus = perf_cpu_map__nr(cpu);
int nrcpus = cpu__max_cpu().cpu;
size_t size;
threads_starting = params.nthreads;

2
tools/perf/bench/futex-requeue.c
View File

@ -125,7 +125,7 @@ static void block_threads(pthread_t *w, struct perf_cpu_map *cpu)
{
cpu_set_t *cpuset;
unsigned int i;
int nrcpus = perf_cpu_map__nr(cpu);
int nrcpus = cpu__max_cpu().cpu;
size_t size;
threads_starting = params.nthreads;

4
tools/perf/bench/futex-wake-parallel.c
View File

@ -149,7 +149,7 @@ static void block_threads(pthread_t *w, struct perf_cpu_map *cpu)
{
cpu_set_t *cpuset;
unsigned int i;
int nrcpus = perf_cpu_map__nr(cpu);
int nrcpus = cpu__max_cpu().cpu;
size_t size;
threads_starting = params.nthreads;
@ -318,7 +318,7 @@ int bench_futex_wake_parallel(int argc, const char **argv)
cond_broadcast(&thread_worker);
mutex_unlock(&thread_lock);
usleep(100000);
usleep(200000);
/* Ok, all threads are patiently blocked, start waking folks up */
wakeup_threads(waking_worker);

2
tools/perf/bench/futex-wake.c
View File

@ -100,7 +100,7 @@ static void block_threads(pthread_t *w, struct perf_cpu_map *cpu)
cpu_set_t *cpuset;
unsigned int i;
size_t size;
int nrcpus = perf_cpu_map__nr(cpu);
int nrcpus = cpu__max_cpu().cpu;
threads_starting = params.nthreads;
cpuset = CPU_ALLOC(nrcpus);

4
tools/perf/builtin-annotate.c
View File

@ -571,8 +571,8 @@ static int __cmd_annotate(struct perf_annotate *ann)
goto out;
if (dump_trace) {
perf_session__fprintf_nr_events(session, stdout, false);
evlist__fprintf_nr_events(session->evlist, stdout, false);
perf_session__fprintf_nr_events(session, stdout);
evlist__fprintf_nr_events(session->evlist, stdout);
goto out;
}

23
tools/perf/builtin-list.c
View File

@ -162,7 +162,11 @@ static void default_print_event(void *ps, const char *pmu_name, const char *topi
} else
fputc('\n', fp);
if (desc && print_state->desc) {
if (long_desc && print_state->long_desc) {
fprintf(fp, "%*s", 8, "[");
wordwrap(fp, long_desc, 8, pager_get_columns(), 0);
fprintf(fp, "]\n");
} else if (desc && print_state->desc) {
char *desc_with_unit = NULL;
int desc_len = -1;
@ -178,12 +182,6 @@ static void default_print_event(void *ps, const char *pmu_name, const char *topi
fprintf(fp, "]\n");
free(desc_with_unit);
}
long_desc = long_desc ?: desc;
if (long_desc && print_state->long_desc) {
fprintf(fp, "%*s", 8, "[");
wordwrap(fp, long_desc, 8, pager_get_columns(), 0);
fprintf(fp, "]\n");
}
if (print_state->detailed && encoding_desc) {
fprintf(fp, "%*s", 8, "");
@ -256,15 +254,14 @@ static void default_print_metric(void *ps,
}
fprintf(fp, " %s\n", name);
if (desc && print_state->desc) {
fprintf(fp, "%*s", 8, "[");
wordwrap(fp, desc, 8, pager_get_columns(), 0);
fprintf(fp, "]\n");
}
if (long_desc && print_state->long_desc) {
fprintf(fp, "%*s", 8, "[");
wordwrap(fp, long_desc, 8, pager_get_columns(), 0);
fprintf(fp, "]\n");
} else if (desc && print_state->desc) {
fprintf(fp, "%*s", 8, "[");
wordwrap(fp, desc, 8, pager_get_columns(), 0);
fprintf(fp, "]\n");
}
if (expr && print_state->detailed) {
fprintf(fp, "%*s", 8, "[");
@ -507,6 +504,7 @@ int cmd_list(int argc, const char **argv)
int i, ret = 0;
struct print_state default_ps = {
.fp = stdout,
.desc = true,
};
struct print_state json_ps = {
.fp = stdout,
@ -579,7 +577,6 @@ int cmd_list(int argc, const char **argv)
};
ps = &json_ps;
} else {
default_ps.desc = !default_ps.long_desc;
default_ps.last_topic = strdup("");
assert(default_ps.last_topic);
default_ps.visited_metrics = strlist__new(NULL, NULL);

29
tools/perf/builtin-lock.c
View File

@ -1477,20 +1477,16 @@ static void dump_map(void)
fprintf(lock_output, " %#llx: %s\n", (unsigned long long)st->addr, st->name);
}
static int dump_info(void)
static void dump_info(void)
{
int rc = 0;
if (info_threads)
dump_threads();
else if (info_map)
dump_map();
else {
rc = -1;
pr_err("Unknown type of information\n");
}
return rc;
if (info_map) {
if (info_threads)
fputc('\n', lock_output);
dump_map();
}
}
static const struct evsel_str_handler lock_tracepoints[] = {
@ -1992,7 +1988,7 @@ static int __cmd_report(bool display_info)
setup_pager();
if (display_info) /* used for info subcommand */
err = dump_info();
dump_info();
else {
combine_result();
sort_result();
@ -2568,9 +2564,9 @@ int cmd_lock(int argc, const char **argv)
const struct option info_options[] = {
OPT_BOOLEAN('t', "threads", &info_threads,
"dump thread list in perf.data"),
"dump the thread list in perf.data"),
OPT_BOOLEAN('m', "map", &info_map,
"map of lock instances (address:name table)"),
"dump the map of lock instances (address:name table)"),
OPT_PARENT(lock_options)
};
@ -2684,6 +2680,13 @@ int cmd_lock(int argc, const char **argv)
if (argc)
usage_with_options(info_usage, info_options);
}
/* If neither threads nor map requested, display both */
if (!info_threads && !info_map) {
info_threads = true;
info_map = true;
}
/* recycling report_lock_ops */
trace_handler = &report_lock_ops;
rc = __cmd_report(true);

32
tools/perf/builtin-record.c
View File

@ -1926,7 +1926,7 @@ static void __record__save_lost_samples(struct record *rec, struct evsel *evsel,
static void record__read_lost_samples(struct record *rec)
{
struct perf_session *session = rec->session;
struct perf_record_lost_samples *lost = NULL;
struct perf_record_lost_samples_and_ids lost;
struct evsel *evsel;
/* there was an error during record__open */
@ -1951,19 +1951,13 @@ static void record__read_lost_samples(struct record *rec)
if (perf_evsel__read(&evsel->core, x, y, &count) < 0) {
pr_debug("read LOST count failed\n");
goto out;
return;
}
if (count.lost) {
if (!lost) {
lost = zalloc(PERF_SAMPLE_MAX_SIZE);
if (!lost) {
pr_debug("Memory allocation failed\n");
return;
}
lost->header.type = PERF_RECORD_LOST_SAMPLES;
}
__record__save_lost_samples(rec, evsel, lost,
memset(&lost, 0, sizeof(lost));
lost.lost.header.type = PERF_RECORD_LOST_SAMPLES;
__record__save_lost_samples(rec, evsel, &lost.lost,
x, y, count.lost, 0);
}
}
@ -1971,20 +1965,12 @@ static void record__read_lost_samples(struct record *rec)
lost_count = perf_bpf_filter__lost_count(evsel);
if (lost_count) {
if (!lost) {
lost = zalloc(PERF_SAMPLE_MAX_SIZE);
if (!lost) {
pr_debug("Memory allocation failed\n");
return;
}
lost->header.type = PERF_RECORD_LOST_SAMPLES;
}
__record__save_lost_samples(rec, evsel, lost, 0, 0, lost_count,
memset(&lost, 0, sizeof(lost));
lost.lost.header.type = PERF_RECORD_LOST_SAMPLES;
__record__save_lost_samples(rec, evsel, &lost.lost, 0, 0, lost_count,
PERF_RECORD_MISC_LOST_SAMPLES_BPF);
}
}
out:
free(lost);
}
static volatile sig_atomic_t workload_exec_errno;
@ -3196,7 +3182,7 @@ static int switch_output_setup(struct record *rec)
unsigned long val;
/*
* If we're using --switch-output-events, then we imply its
* If we're using --switch-output-events, then we imply its
* --switch-output=signal, as we'll send a SIGUSR2 from the side band
* thread to its parent.
*/

11
tools/perf/builtin-report.c
View File

@ -810,8 +810,8 @@ static int stats_print(struct report *rep)
{
struct perf_session *session = rep->session;
perf_session__fprintf_nr_events(session, stdout, rep->skip_empty);
evlist__fprintf_nr_events(session->evlist, stdout, rep->skip_empty);
perf_session__fprintf_nr_events(session, stdout);
evlist__fprintf_nr_events(session->evlist, stdout);
return 0;
}
@ -1089,10 +1089,7 @@ static int __cmd_report(struct report *rep)
perf_session__fprintf_dsos(session, stdout);
if (dump_trace) {
perf_session__fprintf_nr_events(session, stdout,
rep->skip_empty);
evlist__fprintf_nr_events(session->evlist, stdout,
rep->skip_empty);
stats_print(rep);
return 0;
}
}
@ -1562,6 +1559,8 @@ int cmd_report(int argc, const char **argv)
data.path = input_name;
data.force = symbol_conf.force;
symbol_conf.skip_empty = report.skip_empty;
repeat:
session = perf_session__new(&data, &report.tool);
if (IS_ERR(session)) {

195
tools/perf/builtin-sched.c
View File

@ -156,6 +156,9 @@ struct perf_sched_map {
const char *color_pids_str;
struct perf_cpu_map *color_cpus;
const char *color_cpus_str;
const char *task_name;
struct strlist *task_names;
bool fuzzy;
struct perf_cpu_map *cpus;
const char *cpus_str;
};
@ -177,6 +180,7 @@ struct perf_sched {
struct perf_cpu max_cpu;
u32 *curr_pid;
struct thread **curr_thread;
struct thread **curr_out_thread;
char next_shortname1;
char next_shortname2;
unsigned int replay_repeat;
@ -1538,23 +1542,91 @@ map__findnew_thread(struct perf_sched *sched, struct machine *machine, pid_t pid
return thread;
}
static bool sched_match_task(struct perf_sched *sched, const char *comm_str)
{
bool fuzzy_match = sched->map.fuzzy;
struct strlist *task_names = sched->map.task_names;
struct str_node *node;
strlist__for_each_entry(node, task_names) {
bool match_found = fuzzy_match ? !!strstr(comm_str, node->s) :
!strcmp(comm_str, node->s);
if (match_found)
return true;
}
return false;
}
static void print_sched_map(struct perf_sched *sched, struct perf_cpu this_cpu, int cpus_nr,
const char *color, bool sched_out)
{
for (int i = 0; i < cpus_nr; i++) {
struct perf_cpu cpu = {
.cpu = sched->map.comp ? sched->map.comp_cpus[i].cpu : i,
};
struct thread *curr_thread = sched->curr_thread[cpu.cpu];
struct thread *curr_out_thread = sched->curr_out_thread[cpu.cpu];
struct thread_runtime *curr_tr;
const char *pid_color = color;
const char *cpu_color = color;
char symbol = ' ';
struct thread *thread_to_check = sched_out ? curr_out_thread : curr_thread;
if (thread_to_check && thread__has_color(thread_to_check))
pid_color = COLOR_PIDS;
if (sched->map.color_cpus && perf_cpu_map__has(sched->map.color_cpus, cpu))
cpu_color = COLOR_CPUS;
if (cpu.cpu == this_cpu.cpu)
symbol = '*';
color_fprintf(stdout, cpu.cpu != this_cpu.cpu ? color : cpu_color, "%c", symbol);
thread_to_check = sched_out ? sched->curr_out_thread[cpu.cpu] :
sched->curr_thread[cpu.cpu];
if (thread_to_check) {
curr_tr = thread__get_runtime(thread_to_check);
if (curr_tr == NULL)
return;
if (sched_out) {
if (cpu.cpu == this_cpu.cpu)
color_fprintf(stdout, color, "- ");
else {
curr_tr = thread__get_runtime(sched->curr_thread[cpu.cpu]);
if (curr_tr != NULL)
color_fprintf(stdout, pid_color, "%2s ",
curr_tr->shortname);
}
} else
color_fprintf(stdout, pid_color, "%2s ", curr_tr->shortname);
} else
color_fprintf(stdout, color, " ");
}
}
static int map_switch_event(struct perf_sched *sched, struct evsel *evsel,
struct perf_sample *sample, struct machine *machine)
{
const u32 next_pid = evsel__intval(evsel, sample, "next_pid");
struct thread *sched_in;
const u32 prev_pid = evsel__intval(evsel, sample, "prev_pid");
struct thread *sched_in, *sched_out;
struct thread_runtime *tr;
int new_shortname;
u64 timestamp0, timestamp = sample->time;
s64 delta;
int i;
struct perf_cpu this_cpu = {
.cpu = sample->cpu,
};
int cpus_nr;
int proceed;
bool new_cpu = false;
const char *color = PERF_COLOR_NORMAL;
char stimestamp[32];
const char *str;
BUG_ON(this_cpu.cpu >= MAX_CPUS || this_cpu.cpu < 0);
@ -1583,7 +1655,8 @@ static int map_switch_event(struct perf_sched *sched, struct evsel *evsel,
}
sched_in = map__findnew_thread(sched, machine, -1, next_pid);
if (sched_in == NULL)
sched_out = map__findnew_thread(sched, machine, -1, prev_pid);
if (sched_in == NULL || sched_out == NULL)
return -1;
tr = thread__get_runtime(sched_in);
@ -1593,9 +1666,9 @@ static int map_switch_event(struct perf_sched *sched, struct evsel *evsel,
}
sched->curr_thread[this_cpu.cpu] = thread__get(sched_in);
sched->curr_out_thread[this_cpu.cpu] = thread__get(sched_out);
printf(" ");
str = thread__comm_str(sched_in);
new_shortname = 0;
if (!tr->shortname[0]) {
if (!strcmp(thread__comm_str(sched_in), "swapper")) {
@ -1605,7 +1678,7 @@ static int map_switch_event(struct perf_sched *sched, struct evsel *evsel,
*/
tr->shortname[0] = '.';
tr->shortname[1] = ' ';
} else {
} else if (!sched->map.task_name || sched_match_task(sched, str)) {
tr->shortname[0] = sched->next_shortname1;
tr->shortname[1] = sched->next_shortname2;
@ -1618,47 +1691,38 @@ static int map_switch_event(struct perf_sched *sched, struct evsel *evsel,
else
sched->next_shortname2 = '0';
}
} else {
tr->shortname[0] = '-';
tr->shortname[1] = ' ';
}
new_shortname = 1;
}
for (i = 0; i < cpus_nr; i++) {
struct perf_cpu cpu = {
.cpu = sched->map.comp ? sched->map.comp_cpus[i].cpu : i,
};
struct thread *curr_thread = sched->curr_thread[cpu.cpu];
struct thread_runtime *curr_tr;
const char *pid_color = color;
const char *cpu_color = color;
if (curr_thread && thread__has_color(curr_thread))
pid_color = COLOR_PIDS;
if (sched->map.cpus && !perf_cpu_map__has(sched->map.cpus, cpu))
continue;
if (sched->map.color_cpus && perf_cpu_map__has(sched->map.color_cpus, cpu))
cpu_color = COLOR_CPUS;
if (cpu.cpu != this_cpu.cpu)
color_fprintf(stdout, color, " ");
else
color_fprintf(stdout, cpu_color, "*");
if (sched->curr_thread[cpu.cpu]) {
curr_tr = thread__get_runtime(sched->curr_thread[cpu.cpu]);
if (curr_tr == NULL) {
thread__put(sched_in);
return -1;
}
color_fprintf(stdout, pid_color, "%2s ", curr_tr->shortname);
} else
color_fprintf(stdout, color, " ");
}
if (sched->map.cpus && !perf_cpu_map__has(sched->map.cpus, this_cpu))
goto out;
proceed = 0;
str = thread__comm_str(sched_in);
/*
* Check which of sched_in and sched_out matches the passed --task-name
* arguments and call the corresponding print_sched_map.
*/
if (sched->map.task_name && !sched_match_task(sched, str)) {
if (!sched_match_task(sched, thread__comm_str(sched_out)))
goto out;
else
goto sched_out;
} else {
str = thread__comm_str(sched_out);
if (!(sched->map.task_name && !sched_match_task(sched, str)))
proceed = 1;
}
printf(" ");
print_sched_map(sched, this_cpu, cpus_nr, color, false);
timestamp__scnprintf_usec(timestamp, stimestamp, sizeof(stimestamp));
color_fprintf(stdout, color, " %12s secs ", stimestamp);
if (new_shortname || tr->comm_changed || (verbose > 0 && thread__tid(sched_in))) {
@ -1675,9 +1739,32 @@ static int map_switch_event(struct perf_sched *sched, struct evsel *evsel,
if (sched->map.comp && new_cpu)
color_fprintf(stdout, color, " (CPU %d)", this_cpu);
out:
if (proceed != 1) {
color_fprintf(stdout, color, "\n");
goto out;
}
sched_out:
if (sched->map.task_name) {
tr = thread__get_runtime(sched->curr_out_thread[this_cpu.cpu]);
if (strcmp(tr->shortname, "") == 0)
goto out;
if (proceed == 1)
color_fprintf(stdout, color, "\n");
printf(" ");
print_sched_map(sched, this_cpu, cpus_nr, color, true);
timestamp__scnprintf_usec(timestamp, stimestamp, sizeof(stimestamp));
color_fprintf(stdout, color, " %12s secs ", stimestamp);
}
color_fprintf(stdout, color, "\n");
out:
if (sched->map.task_name)
thread__put(sched_out);
thread__put(sched_in);
return 0;
@ -2659,7 +2746,10 @@ out:
tr->last_state = state;
/* sched out event for task so reset ready to run time */
tr->ready_to_run = 0;
if (state == 'R')
tr->ready_to_run = t;
else
tr->ready_to_run = 0;
}
evsel__save_time(evsel, sample->time, sample->cpu);
@ -3307,6 +3397,10 @@ static int perf_sched__map(struct perf_sched *sched)
if (!sched->curr_thread)
return rc;
sched->curr_out_thread = calloc(MAX_CPUS, sizeof(*(sched->curr_out_thread)));
if (!sched->curr_out_thread)
return rc;
if (setup_cpus_switch_event(sched))
goto out_free_curr_thread;
@ -3383,6 +3477,9 @@ static int perf_sched__replay(struct perf_sched *sched)
sched->thread_funcs_exit = false;
create_tasks(sched);
printf("------------------------------------------------------------\n");
if (sched->replay_repeat == 0)
sched->replay_repeat = UINT_MAX;
for (i = 0; i < sched->replay_repeat; i++)
run_one_test(sched);
@ -3548,7 +3645,7 @@ int cmd_sched(int argc, const char **argv)
};
const struct option replay_options[] = {
OPT_UINTEGER('r', "repeat", &sched.replay_repeat,
"repeat the workload replay N times (-1: infinite)"),
"repeat the workload replay N times (0: infinite)"),
OPT_PARENT(sched_options)
};
const struct option map_options[] = {
@ -3560,6 +3657,10 @@ int cmd_sched(int argc, const char **argv)
"highlight given CPUs in map"),
OPT_STRING(0, "cpus", &sched.map.cpus_str, "cpus",
"display given CPUs in map"),
OPT_STRING(0, "task-name", &sched.map.task_name, "task",
"map output only for the given task name(s)."),
OPT_BOOLEAN(0, "fuzzy-name", &sched.map.fuzzy,
"given command name can be partially matched (fuzzy matching)"),
OPT_PARENT(sched_options)
};
const struct option timehist_options[] = {
@ -3658,6 +3759,14 @@ int cmd_sched(int argc, const char **argv)
argc = parse_options(argc, argv, map_options, map_usage, 0);
if (argc)
usage_with_options(map_usage, map_options);
if (sched.map.task_name) {
sched.map.task_names = strlist__new(sched.map.task_name, NULL);
if (sched.map.task_names == NULL) {
fprintf(stderr, "Failed to parse task names\n");
return -1;
}
}
}
sched.tp_handler = &map_ops;
setup_sorting(&sched, latency_options, latency_usage);

399
tools/perf/builtin-stat.c
View File

@ -164,6 +164,35 @@ static struct perf_stat_config stat_config = {
.iostat_run = false,
};
/* Options set from the command line. */
struct opt_aggr_mode {
bool node, socket, die, cluster, cache, core, thread, no_aggr;
};
/* Turn command line option into most generic aggregation mode setting. */
static enum aggr_mode opt_aggr_mode_to_aggr_mode(struct opt_aggr_mode *opt_mode)
{
enum aggr_mode mode = AGGR_GLOBAL;
if (opt_mode->node)
mode = AGGR_NODE;
if (opt_mode->socket)
mode = AGGR_SOCKET;
if (opt_mode->die)
mode = AGGR_DIE;
if (opt_mode->cluster)
mode = AGGR_CLUSTER;
if (opt_mode->cache)
mode = AGGR_CACHE;
if (opt_mode->core)
mode = AGGR_CORE;
if (opt_mode->thread)
mode = AGGR_THREAD;
if (opt_mode->no_aggr)
mode = AGGR_NONE;
return mode;
}
static void evlist__check_cpu_maps(struct evlist *evlist)
{
struct evsel *evsel, *warned_leader = NULL;
@ -255,45 +284,38 @@ static int evsel__write_stat_event(struct evsel *counter, int cpu_map_idx, u32 t
process_synthesized_event, NULL);
}
static int read_single_counter(struct evsel *counter, int cpu_map_idx,
int thread, struct timespec *rs)
static int read_single_counter(struct evsel *counter, int cpu_map_idx, int thread)
{
switch(counter->tool_event) {
case PERF_TOOL_DURATION_TIME: {
u64 val = rs->tv_nsec + rs->tv_sec*1000000000ULL;
struct perf_counts_values *count =
perf_counts(counter->counts, cpu_map_idx, thread);
count->ena = count->run = val;
count->val = val;
return 0;
}
case PERF_TOOL_USER_TIME:
case PERF_TOOL_SYSTEM_TIME: {
u64 val;
struct perf_counts_values *count =
perf_counts(counter->counts, cpu_map_idx, thread);
if (counter->tool_event == PERF_TOOL_USER_TIME)
val = ru_stats.ru_utime_usec_stat.mean;
else
val = ru_stats.ru_stime_usec_stat.mean;
count->ena = count->run = val;
count->val = val;
return 0;
}
default:
case PERF_TOOL_NONE:
return evsel__read_counter(counter, cpu_map_idx, thread);
case PERF_TOOL_MAX:
/* This should never be reached */
return 0;
int err = evsel__read_counter(counter, cpu_map_idx, thread);
/*
* Reading user and system time will fail when the process
* terminates. Use the wait4 values in that case.
*/
if (err && cpu_map_idx == 0 &&
(counter->tool_event == PERF_TOOL_USER_TIME ||
counter->tool_event == PERF_TOOL_SYSTEM_TIME)) {
u64 val, *start_time;
struct perf_counts_values *count =
perf_counts(counter->counts, cpu_map_idx, thread);
start_time = xyarray__entry(counter->start_times, cpu_map_idx, thread);
if (counter->tool_event == PERF_TOOL_USER_TIME)
val = ru_stats.ru_utime_usec_stat.mean;
else
val = ru_stats.ru_stime_usec_stat.mean;
count->ena = count->run = *start_time + val;
count->val = val;
return 0;
}
return err;
}
/*
* Read out the results of a single counter:
* do not aggregate counts across CPUs in system-wide mode
*/
static int read_counter_cpu(struct evsel *counter, struct timespec *rs, int cpu_map_idx)
static int read_counter_cpu(struct evsel *counter, int cpu_map_idx)
{
int nthreads = perf_thread_map__nr(evsel_list->core.threads);
int thread;
@ -311,7 +333,7 @@ static int read_counter_cpu(struct evsel *counter, struct timespec *rs, int cpu_
* (via evsel__read_counter()) and sets their count->loaded.
*/
if (!perf_counts__is_loaded(counter->counts, cpu_map_idx, thread) &&
read_single_counter(counter, cpu_map_idx, thread, rs)) {
read_single_counter(counter, cpu_map_idx, thread)) {
counter->counts->scaled = -1;
perf_counts(counter->counts, cpu_map_idx, thread)->ena = 0;
perf_counts(counter->counts, cpu_map_idx, thread)->run = 0;
@ -340,7 +362,7 @@ static int read_counter_cpu(struct evsel *counter, struct timespec *rs, int cpu_
return 0;
}
static int read_affinity_counters(struct timespec *rs)
static int read_affinity_counters(void)
{
struct evlist_cpu_iterator evlist_cpu_itr;
struct affinity saved_affinity, *affinity;
@ -361,10 +383,8 @@ static int read_affinity_counters(struct timespec *rs)
if (evsel__is_bpf(counter))
continue;
if (!counter->err) {
counter->err = read_counter_cpu(counter, rs,
evlist_cpu_itr.cpu_map_idx);
}
if (!counter->err)
counter->err = read_counter_cpu(counter, evlist_cpu_itr.cpu_map_idx);
}
if (affinity)
affinity__cleanup(&saved_affinity);
@ -388,11 +408,11 @@ static int read_bpf_map_counters(void)
return 0;
}
static int read_counters(struct timespec *rs)
static int read_counters(void)
{
if (!stat_config.stop_read_counter) {
if (read_bpf_map_counters() ||
read_affinity_counters(rs))
read_affinity_counters())
return -1;
}
return 0;
@ -423,7 +443,7 @@ static void process_interval(void)
evlist__reset_aggr_stats(evsel_list);
if (read_counters(&rs) == 0)
if (read_counters() == 0)
process_counters();
if (STAT_RECORD) {
@ -911,7 +931,7 @@ try_again_reset:
* avoid arbitrary skew, we must read all counters before closing any
* group leaders.
*/
if (read_counters(&(struct timespec) { .tv_nsec = t1-t0 }) == 0)
if (read_counters() == 0)
process_counters();
/*
@ -1096,7 +1116,7 @@ static int parse_cache_level(const struct option *opt,
int unset __maybe_unused)
{
int level;
u32 *aggr_mode = (u32 *)opt->value;
struct opt_aggr_mode *opt_aggr_mode = (struct opt_aggr_mode *)opt->value;
u32 *aggr_level = (u32 *)opt->data;
/*
@ -1135,155 +1155,11 @@ static int parse_cache_level(const struct option *opt,
return -EINVAL;
}
out:
*aggr_mode = AGGR_CACHE;
opt_aggr_mode->cache = true;
*aggr_level = level;
return 0;
}
static struct option stat_options[] = {
OPT_BOOLEAN('T', "transaction", &transaction_run,
"hardware transaction statistics"),
OPT_CALLBACK('e', "event", &parse_events_option_args, "event",
"event selector. use 'perf list' to list available events",
parse_events_option),
OPT_CALLBACK(0, "filter", &evsel_list, "filter",
"event filter", parse_filter),
OPT_BOOLEAN('i', "no-inherit", &stat_config.no_inherit,
"child tasks do not inherit counters"),
OPT_STRING('p', "pid", &target.pid, "pid",
"stat events on existing process id"),
OPT_STRING('t', "tid", &target.tid, "tid",
"stat events on existing thread id"),
#ifdef HAVE_BPF_SKEL
OPT_STRING('b', "bpf-prog", &target.bpf_str, "bpf-prog-id",
"stat events on existing bpf program id"),
OPT_BOOLEAN(0, "bpf-counters", &target.use_bpf,
"use bpf program to count events"),
OPT_STRING(0, "bpf-attr-map", &target.attr_map, "attr-map-path",
"path to perf_event_attr map"),
#endif
OPT_BOOLEAN('a', "all-cpus", &target.system_wide,
"system-wide collection from all CPUs"),
OPT_BOOLEAN(0, "scale", &stat_config.scale,
"Use --no-scale to disable counter scaling for multiplexing"),
OPT_INCR('v', "verbose", &verbose,
"be more verbose (show counter open errors, etc)"),
OPT_INTEGER('r', "repeat", &stat_config.run_count,
"repeat command and print average + stddev (max: 100, forever: 0)"),
OPT_BOOLEAN(0, "table", &stat_config.walltime_run_table,
"display details about each run (only with -r option)"),
OPT_BOOLEAN('n', "null", &stat_config.null_run,
"null run - dont start any counters"),
OPT_INCR('d', "detailed", &detailed_run,
"detailed run - start a lot of events"),
OPT_BOOLEAN('S', "sync", &sync_run,
"call sync() before starting a run"),
OPT_CALLBACK_NOOPT('B', "big-num", NULL, NULL,
"print large numbers with thousands\' separators",
stat__set_big_num),
OPT_STRING('C', "cpu", &target.cpu_list, "cpu",
"list of cpus to monitor in system-wide"),
OPT_SET_UINT('A', "no-aggr", &stat_config.aggr_mode,
"disable aggregation across CPUs or PMUs", AGGR_NONE),
OPT_SET_UINT(0, "no-merge", &stat_config.aggr_mode,
"disable aggregation the same as -A or -no-aggr", AGGR_NONE),
OPT_BOOLEAN(0, "hybrid-merge", &stat_config.hybrid_merge,
"Merge identical named hybrid events"),
OPT_STRING('x', "field-separator", &stat_config.csv_sep, "separator",
"print counts with custom separator"),
OPT_BOOLEAN('j', "json-output", &stat_config.json_output,
"print counts in JSON format"),
OPT_CALLBACK('G', "cgroup", &evsel_list, "name",
"monitor event in cgroup name only", parse_stat_cgroups),
OPT_STRING(0, "for-each-cgroup", &stat_config.cgroup_list, "name",
"expand events for each cgroup"),
OPT_STRING('o', "output", &output_name, "file", "output file name"),
OPT_BOOLEAN(0, "append", &append_file, "append to the output file"),
OPT_INTEGER(0, "log-fd", &output_fd,
"log output to fd, instead of stderr"),
OPT_STRING(0, "pre", &pre_cmd, "command",
"command to run prior to the measured command"),
OPT_STRING(0, "post", &post_cmd, "command",
"command to run after to the measured command"),
OPT_UINTEGER('I', "interval-print", &stat_config.interval,
"print counts at regular interval in ms "
"(overhead is possible for values <= 100ms)"),
OPT_INTEGER(0, "interval-count", &stat_config.times,
"print counts for fixed number of times"),
OPT_BOOLEAN(0, "interval-clear", &stat_config.interval_clear,
"clear screen in between new interval"),
OPT_UINTEGER(0, "timeout", &stat_config.timeout,
"stop workload and print counts after a timeout period in ms (>= 10ms)"),
OPT_SET_UINT(0, "per-socket", &stat_config.aggr_mode,
"aggregate counts per processor socket", AGGR_SOCKET),
OPT_SET_UINT(0, "per-die", &stat_config.aggr_mode,
"aggregate counts per processor die", AGGR_DIE),
OPT_SET_UINT(0, "per-cluster", &stat_config.aggr_mode,
"aggregate counts per processor cluster", AGGR_CLUSTER),
OPT_CALLBACK_OPTARG(0, "per-cache", &stat_config.aggr_mode, &stat_config.aggr_level,
"cache level", "aggregate count at this cache level (Default: LLC)",
parse_cache_level),
OPT_SET_UINT(0, "per-core", &stat_config.aggr_mode,
"aggregate counts per physical processor core", AGGR_CORE),
OPT_SET_UINT(0, "per-thread", &stat_config.aggr_mode,
"aggregate counts per thread", AGGR_THREAD),
OPT_SET_UINT(0, "per-node", &stat_config.aggr_mode,
"aggregate counts per numa node", AGGR_NODE),
OPT_INTEGER('D', "delay", &target.initial_delay,
"ms to wait before starting measurement after program start (-1: start with events disabled)"),
OPT_CALLBACK_NOOPT(0, "metric-only", &stat_config.metric_only, NULL,
"Only print computed metrics. No raw values", enable_metric_only),
OPT_BOOLEAN(0, "metric-no-group", &stat_config.metric_no_group,
"don't group metric events, impacts multiplexing"),
OPT_BOOLEAN(0, "metric-no-merge", &stat_config.metric_no_merge,
"don't try to share events between metrics in a group"),
OPT_BOOLEAN(0, "metric-no-threshold", &stat_config.metric_no_threshold,
"disable adding events for the metric threshold calculation"),
OPT_BOOLEAN(0, "topdown", &topdown_run,
"measure top-down statistics"),
OPT_UINTEGER(0, "td-level", &stat_config.topdown_level,
"Set the metrics level for the top-down statistics (0: max level)"),
OPT_BOOLEAN(0, "smi-cost", &smi_cost,
"measure SMI cost"),
OPT_CALLBACK('M', "metrics", &evsel_list, "metric/metric group list",
"monitor specified metrics or metric groups (separated by ,)",
append_metric_groups),
OPT_BOOLEAN_FLAG(0, "all-kernel", &stat_config.all_kernel,
"Configure all used events to run in kernel space.",
PARSE_OPT_EXCLUSIVE),
OPT_BOOLEAN_FLAG(0, "all-user", &stat_config.all_user,
"Configure all used events to run in user space.",
PARSE_OPT_EXCLUSIVE),
OPT_BOOLEAN(0, "percore-show-thread", &stat_config.percore_show_thread,
"Use with 'percore' event qualifier to show the event "
"counts of one hardware thread by sum up total hardware "
"threads of same physical core"),
OPT_BOOLEAN(0, "summary", &stat_config.summary,
"print summary for interval mode"),
OPT_BOOLEAN(0, "no-csv-summary", &stat_config.no_csv_summary,
"don't print 'summary' for CSV summary output"),
OPT_BOOLEAN(0, "quiet", &quiet,
"don't print any output, messages or warnings (useful with record)"),
OPT_CALLBACK(0, "cputype", &evsel_list, "hybrid cpu type",
"Only enable events on applying cpu with this type "
"for hybrid platform (e.g. core or atom)",
parse_cputype),
#ifdef HAVE_LIBPFM
OPT_CALLBACK(0, "pfm-events", &evsel_list, "event",
"libpfm4 event selector. use 'perf list' to list available events",
parse_libpfm_events_option),
#endif
OPT_CALLBACK(0, "control", &stat_config, "fd:ctl-fd[,ack-fd] or fifo:ctl-fifo[,ack-fifo]",
"Listen on ctl-fd descriptor for command to control measurement ('enable': enable events, 'disable': disable events).\n"
"\t\t\t Optionally send control command completion ('ack\\n') to ack-fd descriptor.\n"
"\t\t\t Alternatively, ctl-fifo / ack-fifo will be opened and used as ctl-fd / ack-fd.",
parse_control_option),
OPT_CALLBACK_OPTARG(0, "iostat", &evsel_list, &stat_config, "default",
"measure I/O performance metrics provided by arch/platform",
iostat_parse),
OPT_END()
};
/**
* Calculate the cache instance ID from the map in
* /sys/devices/system/cpu/cpuX/cache/indexY/shared_cpu_list
@ -2245,13 +2121,15 @@ static void init_features(struct perf_session *session)
perf_header__clear_feat(&session->header, HEADER_AUXTRACE);
}
static int __cmd_record(int argc, const char **argv)
static int __cmd_record(const struct option stat_options[], struct opt_aggr_mode *opt_mode,
int argc, const char **argv)
{
struct perf_session *session;
struct perf_data *data = &perf_stat.data;
argc = parse_options(argc, argv, stat_options, stat_record_usage,
PARSE_OPT_STOP_AT_NON_OPTION);
stat_config.aggr_mode = opt_aggr_mode_to_aggr_mode(opt_mode);
if (output_name)
data->path = output_name;
@ -2494,6 +2372,147 @@ static void setup_system_wide(int forks)
int cmd_stat(int argc, const char **argv)
{
struct opt_aggr_mode opt_mode = {};
struct option stat_options[] = {
OPT_BOOLEAN('T', "transaction", &transaction_run,
"hardware transaction statistics"),
OPT_CALLBACK('e', "event", &parse_events_option_args, "event",
"event selector. use 'perf list' to list available events",
parse_events_option),
OPT_CALLBACK(0, "filter", &evsel_list, "filter",
"event filter", parse_filter),
OPT_BOOLEAN('i', "no-inherit", &stat_config.no_inherit,
"child tasks do not inherit counters"),
OPT_STRING('p', "pid", &target.pid, "pid",
"stat events on existing process id"),
OPT_STRING('t', "tid", &target.tid, "tid",
"stat events on existing thread id"),
#ifdef HAVE_BPF_SKEL
OPT_STRING('b', "bpf-prog", &target.bpf_str, "bpf-prog-id",
"stat events on existing bpf program id"),
OPT_BOOLEAN(0, "bpf-counters", &target.use_bpf,
"use bpf program to count events"),
OPT_STRING(0, "bpf-attr-map", &target.attr_map, "attr-map-path",
"path to perf_event_attr map"),
#endif
OPT_BOOLEAN('a', "all-cpus", &target.system_wide,
"system-wide collection from all CPUs"),
OPT_BOOLEAN(0, "scale", &stat_config.scale,
"Use --no-scale to disable counter scaling for multiplexing"),
OPT_INCR('v', "verbose", &verbose,
"be more verbose (show counter open errors, etc)"),
OPT_INTEGER('r', "repeat", &stat_config.run_count,
"repeat command and print average + stddev (max: 100, forever: 0)"),
OPT_BOOLEAN(0, "table", &stat_config.walltime_run_table,
"display details about each run (only with -r option)"),
OPT_BOOLEAN('n', "null", &stat_config.null_run,
"null run - dont start any counters"),
OPT_INCR('d', "detailed", &detailed_run,
"detailed run - start a lot of events"),
OPT_BOOLEAN('S', "sync", &sync_run,
"call sync() before starting a run"),
OPT_CALLBACK_NOOPT('B', "big-num", NULL, NULL,
"print large numbers with thousands\' separators",
stat__set_big_num),
OPT_STRING('C', "cpu", &target.cpu_list, "cpu",
"list of cpus to monitor in system-wide"),
OPT_BOOLEAN('A', "no-aggr", &opt_mode.no_aggr,
"disable aggregation across CPUs or PMUs"),
OPT_BOOLEAN(0, "no-merge", &opt_mode.no_aggr,
"disable aggregation the same as -A or -no-aggr"),
OPT_BOOLEAN(0, "hybrid-merge", &stat_config.hybrid_merge,
"Merge identical named hybrid events"),
OPT_STRING('x', "field-separator", &stat_config.csv_sep, "separator",
"print counts with custom separator"),
OPT_BOOLEAN('j', "json-output", &stat_config.json_output,
"print counts in JSON format"),
OPT_CALLBACK('G', "cgroup", &evsel_list, "name",
"monitor event in cgroup name only", parse_stat_cgroups),
OPT_STRING(0, "for-each-cgroup", &stat_config.cgroup_list, "name",
"expand events for each cgroup"),
OPT_STRING('o', "output", &output_name, "file", "output file name"),
OPT_BOOLEAN(0, "append", &append_file, "append to the output file"),
OPT_INTEGER(0, "log-fd", &output_fd,
"log output to fd, instead of stderr"),
OPT_STRING(0, "pre", &pre_cmd, "command",
"command to run prior to the measured command"),
OPT_STRING(0, "post", &post_cmd, "command",
"command to run after to the measured command"),
OPT_UINTEGER('I', "interval-print", &stat_config.interval,
"print counts at regular interval in ms "
"(overhead is possible for values <= 100ms)"),
OPT_INTEGER(0, "interval-count", &stat_config.times,
"print counts for fixed number of times"),
OPT_BOOLEAN(0, "interval-clear", &stat_config.interval_clear,
"clear screen in between new interval"),
OPT_UINTEGER(0, "timeout", &stat_config.timeout,
"stop workload and print counts after a timeout period in ms (>= 10ms)"),
OPT_BOOLEAN(0, "per-socket", &opt_mode.socket,
"aggregate counts per processor socket"),
OPT_BOOLEAN(0, "per-die", &opt_mode.die, "aggregate counts per processor die"),
OPT_BOOLEAN(0, "per-cluster", &opt_mode.cluster,
"aggregate counts per processor cluster"),
OPT_CALLBACK_OPTARG(0, "per-cache", &opt_mode, &stat_config.aggr_level,
"cache level", "aggregate count at this cache level (Default: LLC)",
parse_cache_level),
OPT_BOOLEAN(0, "per-core", &opt_mode.core,
"aggregate counts per physical processor core"),
OPT_BOOLEAN(0, "per-thread", &opt_mode.thread, "aggregate counts per thread"),
OPT_BOOLEAN(0, "per-node", &opt_mode.node, "aggregate counts per numa node"),
OPT_INTEGER('D', "delay", &target.initial_delay,
"ms to wait before starting measurement after program start (-1: start with events disabled)"),
OPT_CALLBACK_NOOPT(0, "metric-only", &stat_config.metric_only, NULL,
"Only print computed metrics. No raw values", enable_metric_only),
OPT_BOOLEAN(0, "metric-no-group", &stat_config.metric_no_group,
"don't group metric events, impacts multiplexing"),
OPT_BOOLEAN(0, "metric-no-merge", &stat_config.metric_no_merge,
"don't try to share events between metrics in a group"),
OPT_BOOLEAN(0, "metric-no-threshold", &stat_config.metric_no_threshold,
"disable adding events for the metric threshold calculation"),
OPT_BOOLEAN(0, "topdown", &topdown_run,
"measure top-down statistics"),
OPT_UINTEGER(0, "td-level", &stat_config.topdown_level,
"Set the metrics level for the top-down statistics (0: max level)"),
OPT_BOOLEAN(0, "smi-cost", &smi_cost,
"measure SMI cost"),
OPT_CALLBACK('M', "metrics", &evsel_list, "metric/metric group list",
"monitor specified metrics or metric groups (separated by ,)",
append_metric_groups),
OPT_BOOLEAN_FLAG(0, "all-kernel", &stat_config.all_kernel,
"Configure all used events to run in kernel space.",
PARSE_OPT_EXCLUSIVE),
OPT_BOOLEAN_FLAG(0, "all-user", &stat_config.all_user,
"Configure all used events to run in user space.",
PARSE_OPT_EXCLUSIVE),
OPT_BOOLEAN(0, "percore-show-thread", &stat_config.percore_show_thread,
"Use with 'percore' event qualifier to show the event "
"counts of one hardware thread by sum up total hardware "
"threads of same physical core"),
OPT_BOOLEAN(0, "summary", &stat_config.summary,
"print summary for interval mode"),
OPT_BOOLEAN(0, "no-csv-summary", &stat_config.no_csv_summary,
"don't print 'summary' for CSV summary output"),
OPT_BOOLEAN(0, "quiet", &quiet,
"don't print any output, messages or warnings (useful with record)"),
OPT_CALLBACK(0, "cputype", &evsel_list, "hybrid cpu type",
"Only enable events on applying cpu with this type "
"for hybrid platform (e.g. core or atom)",
parse_cputype),
#ifdef HAVE_LIBPFM
OPT_CALLBACK(0, "pfm-events", &evsel_list, "event",
"libpfm4 event selector. use 'perf list' to list available events",
parse_libpfm_events_option),
#endif
OPT_CALLBACK(0, "control", &stat_config, "fd:ctl-fd[,ack-fd] or fifo:ctl-fifo[,ack-fifo]",
"Listen on ctl-fd descriptor for command to control measurement ('enable': enable events, 'disable': disable events).\n"
"\t\t\t Optionally send control command completion ('ack\\n') to ack-fd descriptor.\n"
"\t\t\t Alternatively, ctl-fifo / ack-fifo will be opened and used as ctl-fd / ack-fd.",
parse_control_option),
OPT_CALLBACK_OPTARG(0, "iostat", &evsel_list, &stat_config, "default",
"measure I/O performance metrics provided by arch/platform",
iostat_parse),
OPT_END()
};
const char * const stat_usage[] = {
"perf stat [<options>] [<command>]",
NULL
@ -2522,6 +2541,8 @@ int cmd_stat(int argc, const char **argv)
(const char **) stat_usage,
PARSE_OPT_STOP_AT_NON_OPTION);
stat_config.aggr_mode = opt_aggr_mode_to_aggr_mode(&opt_mode);
if (stat_config.csv_sep) {
stat_config.csv_output = true;
if (!strcmp(stat_config.csv_sep, "\\t"))
@ -2530,7 +2551,7 @@ int cmd_stat(int argc, const char **argv)
stat_config.csv_sep = DEFAULT_SEPARATOR;
if (argc && strlen(argv[0]) > 2 && strstarts("record", argv[0])) {
argc = __cmd_record(argc, argv);
argc = __cmd_record(stat_options, &opt_mode, argc, argv);
if (argc < 0)
return -1;
} else if (argc && strlen(argv[0]) > 2 && strstarts("report", argv[0]))

9
tools/perf/builtin-top.c
View File

@ -1055,6 +1055,13 @@ try_again:
}
}
if (evlist__apply_filters(evlist, &counter)) {
pr_err("failed to set filter \"%s\" on event %s with %d (%s)\n",
counter->filter ?: "BPF", evsel__name(counter), errno,
str_error_r(errno, msg, sizeof(msg)));
goto out_err;
}
if (evlist__mmap(evlist, opts->mmap_pages) < 0) {
ui__error("Failed to mmap with %d (%s)\n",
errno, str_error_r(errno, msg, sizeof(msg)));
@ -1462,6 +1469,8 @@ int cmd_top(int argc, const char **argv)
OPT_CALLBACK('e', "event", &parse_events_option_args, "event",
"event selector. use 'perf list' to list available events",
parse_events_option),
OPT_CALLBACK(0, "filter", &top.evlist, "filter",
"event filter", parse_filter),
OPT_U64('c', "count", &opts->user_interval, "event period to sample"),
OPT_STRING('p', "pid", &target->pid, "pid",
"profile events on existing process id"),

49
tools/perf/builtin-trace.c
View File

@ -1033,7 +1033,7 @@ static const struct syscall_fmt syscall_fmts[] = {
#if defined(__s390x__)
.alias = "old_mmap",
#endif
.arg = { [2] = { .scnprintf = SCA_MMAP_PROT, /* prot */ },
.arg = { [2] = { .scnprintf = SCA_MMAP_PROT, .show_zero = true, /* prot */ },
[3] = { .scnprintf = SCA_MMAP_FLAGS, /* flags */
.strtoul = STUL_STRARRAY_FLAGS,
.parm = &strarray__mmap_flags, },
@ -1050,7 +1050,7 @@ static const struct syscall_fmt syscall_fmts[] = {
[4] = { .scnprintf = SCA_MOVE_MOUNT_FLAGS, /* flags */ }, }, },
{ .name = "mprotect",
.arg = { [0] = { .scnprintf = SCA_HEX, /* start */ },
[2] = { .scnprintf = SCA_MMAP_PROT, /* prot */ }, }, },
[2] = { .scnprintf = SCA_MMAP_PROT, .show_zero = true, /* prot */ }, }, },
{ .name = "mq_unlink",
.arg = { [0] = { .scnprintf = SCA_FILENAME, /* u_name */ }, }, },
{ .name = "mremap", .hexret = true,
@ -1084,7 +1084,7 @@ static const struct syscall_fmt syscall_fmts[] = {
.arg = { [0] = { .scnprintf = SCA_INT, /* key */ }, }, },
{ .name = "pkey_mprotect",
.arg = { [0] = { .scnprintf = SCA_HEX, /* start */ },
[2] = { .scnprintf = SCA_MMAP_PROT, /* prot */ },
[2] = { .scnprintf = SCA_MMAP_PROT, .show_zero = true, /* prot */ },
[3] = { .scnprintf = SCA_INT, /* pkey */ }, }, },
{ .name = "poll", .timeout = true, },
{ .name = "ppoll", .timeout = true, },
@ -2091,17 +2091,11 @@ static size_t syscall__scnprintf_args(struct syscall *sc, char *bf, size_t size,
val = syscall_arg_fmt__mask_val(&sc->arg_fmt[arg.idx], &arg, val);
/*
* Suppress this argument if its value is zero and
* and we don't have a string associated in an
* strarray for it.
*/
if (val == 0 &&
!trace->show_zeros &&
!(sc->arg_fmt &&
(sc->arg_fmt[arg.idx].show_zero ||
sc->arg_fmt[arg.idx].scnprintf == SCA_STRARRAY ||
sc->arg_fmt[arg.idx].scnprintf == SCA_STRARRAYS) &&
sc->arg_fmt[arg.idx].parm))
* Suppress this argument if its value is zero and show_zero
* property isn't set.
*/
if (val == 0 && !trace->show_zeros &&
!(sc->arg_fmt && sc->arg_fmt[arg.idx].show_zero))
continue;
printed += scnprintf(bf + printed, size - printed, "%s", printed ? ", " : "");
@ -2796,17 +2790,8 @@ static size_t trace__fprintf_tp_fields(struct trace *trace, struct evsel *evsel,
*/
val = syscall_arg_fmt__mask_val(arg, &syscall_arg, val);
/*
* Suppress this argument if its value is zero and
* we don't have a string associated in an
* strarray for it.
*/
if (val == 0 &&
!trace->show_zeros &&
!((arg->show_zero ||
arg->scnprintf == SCA_STRARRAY ||
arg->scnprintf == SCA_STRARRAYS) &&
arg->parm))
/* Suppress this argument if its value is zero and show_zero property isn't set. */
if (val == 0 && !trace->show_zeros && !arg->show_zero)
continue;
printed += scnprintf(bf + printed, size - printed, "%s", printed ? ", " : "");
@ -3369,8 +3354,6 @@ static int trace__bpf_prog_sys_exit_fd(struct trace *trace, int id)
static struct bpf_program *trace__find_usable_bpf_prog_entry(struct trace *trace, struct syscall *sc)
{
struct tep_format_field *field, *candidate_field;
int id;
/*
* We're only interested in syscalls that have a pointer:
*/
@ -3382,7 +3365,8 @@ static struct bpf_program *trace__find_usable_bpf_prog_entry(struct trace *trace
return NULL;
try_to_find_pair:
for (id = 0; id < trace->sctbl->syscalls.nr_entries; ++id) {
for (int i = 0; i < trace->sctbl->syscalls.nr_entries; ++i) {
int id = syscalltbl__id_at_idx(trace->sctbl, i);
struct syscall *pair = trace__syscall_info(trace, NULL, id);
struct bpf_program *pair_prog;
bool is_candidate = false;
@ -3471,10 +3455,10 @@ static int trace__init_syscalls_bpf_prog_array_maps(struct trace *trace)
{
int map_enter_fd = bpf_map__fd(trace->skel->maps.syscalls_sys_enter);
int map_exit_fd = bpf_map__fd(trace->skel->maps.syscalls_sys_exit);
int err = 0, key;
int err = 0;
for (key = 0; key < trace->sctbl->syscalls.nr_entries; ++key) {
int prog_fd;
for (int i = 0; i < trace->sctbl->syscalls.nr_entries; ++i) {
int prog_fd, key = syscalltbl__id_at_idx(trace->sctbl, i);
if (!trace__syscall_enabled(trace, key))
continue;
@ -3520,7 +3504,8 @@ static int trace__init_syscalls_bpf_prog_array_maps(struct trace *trace)
* first and second arg (this one on the raw_syscalls:sys_exit prog
* array tail call, then that one will be used.
*/
for (key = 0; key < trace->sctbl->syscalls.nr_entries; ++key) {
for (int i = 0; i < trace->sctbl->syscalls.nr_entries; ++i) {
int key = syscalltbl__id_at_idx(trace->sctbl, i);
struct syscall *sc = trace__syscall_info(trace, NULL, key);
struct bpf_program *pair_prog;
int prog_fd;

9
tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/ddrc.json Normal file
View File

@ -0,0 +1,9 @@
[
{
"BriefDescription": "ddr cycles event",
"EventCode": "0x00",
"EventName": "imx93_ddr.cycles",
"Unit": "imx9_ddr",
"Compat": "imx93"
}
]

26
tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/metrics.json Normal file
View File

@ -0,0 +1,26 @@
[
{
"BriefDescription": "bandwidth usage for lpddr4x evk board",
"MetricName": "imx93_bandwidth_usage.lpddr4x",
"MetricExpr": "(((( imx9_ddr0@ddrc_pm_0@ ) * 2 * 8 ) + (( imx9_ddr0@ddrc_pm_3@ + imx9_ddr0@ddrc_pm_5@ + imx9_ddr0@ddrc_pm_7@ + imx9_ddr0@ddrc_pm_9@ - imx9_ddr0@ddrc_pm_2@ - imx9_ddr0@ddrc_pm_4@ - imx9_ddr0@ddrc_pm_6@ - imx9_ddr0@ddrc_pm_8@ ) * 32 )) / duration_time) / (3733 * 1000000 * 2)",
"ScaleUnit": "1e2%",
"Unit": "imx9_ddr",
"Compat": "imx93"
},
{
"BriefDescription": "bytes all masters read from ddr",
"MetricName": "imx93_ddr_read.all",
"MetricExpr": "( imx9_ddr0@ddrc_pm_0@ ) * 2 * 8",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx93"
},
{
"BriefDescription": "bytes all masters write to ddr",
"MetricName": "imx93_ddr_write.all",
"MetricExpr": "( imx9_ddr0@ddrc_pm_3@ + imx9_ddr0@ddrc_pm_5@ + imx9_ddr0@ddrc_pm_7@ + imx9_ddr0@ddrc_pm_9@ - imx9_ddr0@ddrc_pm_2@ - imx9_ddr0@ddrc_pm_4@ - imx9_ddr0@ddrc_pm_6@ - imx9_ddr0@ddrc_pm_8@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx93"
}
]

9
tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json Normal file
View File

@ -0,0 +1,9 @@
[
{
"BriefDescription": "ddr cycles event",
"EventCode": "0x00",
"EventName": "imx95_ddr.cycles",
"Unit": "imx9_ddr",
"Compat": "imx95"
}
]

874
tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json Normal file
View File

@ -0,0 +1,874 @@
[
{
"BriefDescription": "bandwidth usage for lpddr5 evk board",
"MetricName": "imx95_bandwidth_usage.lpddr5",
"MetricExpr": "(( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32 / duration_time) / (6400 * 1000000 * 4)",
"ScaleUnit": "1e2%",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all masters read from ddr",
"MetricName": "imx95_ddr_read.all",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all masters write to ddr",
"MetricName": "imx95_ddr_write.all",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all a55 read from ddr",
"MetricName": "imx95_ddr_read.a55_all",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all a55 write to ddr (part1)",
"MetricName": "imx95_ddr_write.a55_all_1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all a55 write to ddr (part2)",
"MetricName": "imx95_ddr_write.a55_all_2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of a55 core 0 read from ddr",
"MetricName": "imx95_ddr_read.a55_0",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of a55 core 0 write to ddr",
"MetricName": "imx95_ddr_write.a55_0",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of a55 core 1 read from ddr",
"MetricName": "imx95_ddr_read.a55_1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of a55 core 1 write to ddr",
"MetricName": "imx95_ddr_write.a55_1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of a55 core 2 read from ddr",
"MetricName": "imx95_ddr_read.a55_2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of a55 core 2 write to ddr",
"MetricName": "imx95_ddr_write.a55_2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of a55 core 3 read from ddr",
"MetricName": "imx95_ddr_read.a55_3",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of a55 core 3 write to ddr",
"MetricName": "imx95_ddr_write.a55_3",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of a55 core 4 read from ddr",
"MetricName": "imx95_ddr_read.a55_4",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of a55 core 4 write to ddr",
"MetricName": "imx95_ddr_write.a55_4",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of a55 core 5 read from ddr",
"MetricName": "imx95_ddr_read.a55_5",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of a55 core 5 write to ddr",
"MetricName": "imx95_ddr_write.a55_5",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions read from ddr",
"MetricName": "imx95_ddr_read.cortexa_dsu_l3",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions write to ddr",
"MetricName": "imx95_ddr_write.cortexa_dsu_l3",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of m33 read from ddr",
"MetricName": "imx95_ddr_read.m33",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of m33 write to ddr",
"MetricName": "imx95_ddr_write.m33",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of m7 read from ddr",
"MetricName": "imx95_ddr_read.m7",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of m7 write to ddr",
"MetricName": "imx95_ddr_write.m7",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of sentinel read from ddr",
"MetricName": "imx95_ddr_read.sentinel",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of sentinel write to ddr",
"MetricName": "imx95_ddr_write.sentinel",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of edma1 read from ddr",
"MetricName": "imx95_ddr_read.edma1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of edma1 write to ddr",
"MetricName": "imx95_ddr_write.edma1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of edma2 read from ddr",
"MetricName": "imx95_ddr_read.edma2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of edma2 write to ddr",
"MetricName": "imx95_ddr_write.edma2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of netc read from ddr",
"MetricName": "imx95_ddr_read.netc",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of netc write to ddr",
"MetricName": "imx95_ddr_write.netc",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of npu read from ddr",
"MetricName": "imx95_ddr_read.npu",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of npu write to ddr",
"MetricName": "imx95_ddr_write.npu",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of gpu read from ddr",
"MetricName": "imx95_ddr_read.gpu",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of gpu write to ddr",
"MetricName": "imx95_ddr_write.gpu",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of usdhc1 read from ddr",
"MetricName": "imx95_ddr_read.usdhc1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of usdhc1 write to ddr",
"MetricName": "imx95_ddr_write.usdhc1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of usdhc2 read from ddr",
"MetricName": "imx95_ddr_read.usdhc2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of usdhc2 write to ddr",
"MetricName": "imx95_ddr_write.usdhc2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of usdhc3 read from ddr",
"MetricName": "imx95_ddr_read.usdhc3",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of usdhc3 write to ddr",
"MetricName": "imx95_ddr_write.usdhc3",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of xspi read from ddr",
"MetricName": "imx95_ddr_read.xspi",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of xspi write to ddr",
"MetricName": "imx95_ddr_write.xspi",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of pcie1 read from ddr",
"MetricName": "imx95_ddr_read.pcie1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of pcie1 write to ddr",
"MetricName": "imx95_ddr_write.pcie1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of pcie2 read from ddr",
"MetricName": "imx95_ddr_read.pcie2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of pcie2 write to ddr",
"MetricName": "imx95_ddr_write.pcie2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of pcie3 read from ddr",
"MetricName": "imx95_ddr_read.pcie3",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of pcie3 write to ddr",
"MetricName": "imx95_ddr_write.pcie3",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of pcie4 read from ddr",
"MetricName": "imx95_ddr_read.pcie4",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of pcie4 write to ddr",
"MetricName": "imx95_ddr_write.pcie4",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of usb1 read from ddr",
"MetricName": "imx95_ddr_read.usb1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of usb1 write to ddr",
"MetricName": "imx95_ddr_write.usb1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of usb2 read from ddr",
"MetricName": "imx95_ddr_read.usb2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of usb2 write to ddr",
"MetricName": "imx95_ddr_write.usb2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of vpu codec primary bus read from ddr",
"MetricName": "imx95_ddr_read.vpu_primy",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of vpu codec primary bus write to ddr",
"MetricName": "imx95_ddr_write.vpu_primy",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of vpu codec secondary bus read from ddr",
"MetricName": "imx95_ddr_read.vpu_secndy",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of vpu codec secondary bus write to ddr",
"MetricName": "imx95_ddr_write.vpu_secndy",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of jpeg decoder read from ddr",
"MetricName": "imx95_ddr_read.jpeg_dec",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of jpeg decoder write to ddr",
"MetricName": "imx95_ddr_write.jpeg_dec",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of jpeg encoder read from ddr",
"MetricName": "imx95_ddr_read.jpeg_dec",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of jpeg encoder write to ddr",
"MetricName": "imx95_ddr_write.jpeg_enc",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all vpu submodules read from ddr",
"MetricName": "imx95_ddr_read.vpu_all",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all vpu submodules write to ddr",
"MetricName": "imx95_ddr_write.vpu_all",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of cortex m0+ read from ddr",
"MetricName": "imx95_ddr_read.m0",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of cortex m0+ write to ddr",
"MetricName": "imx95_ddr_write.m0",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of camera edma read from ddr",
"MetricName": "imx95_ddr_read.camera_edma",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of camera edma write to ddr",
"MetricName": "imx95_ddr_write.camera_edma",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isi rd read from ddr",
"MetricName": "imx95_ddr_read.isi_rd",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isi rd write to ddr",
"MetricName": "imx95_ddr_write.isi_rd",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isi wr y read from ddr",
"MetricName": "imx95_ddr_read.isi_wr_y",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isi wr y write to ddr",
"MetricName": "imx95_ddr_write.isi_wr_y",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isi wr u read from ddr",
"MetricName": "imx95_ddr_read.isi_wr_u",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isi wr u write to ddr",
"MetricName": "imx95_ddr_write.isi_wr_u",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isi wr v read from ddr",
"MetricName": "imx95_ddr_read.isi_wr_v",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isi wr v write to ddr",
"MetricName": "imx95_ddr_write.isi_wr_v",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isp input dma1 read from ddr",
"MetricName": "imx95_ddr_read.isp_in_dma1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isp input dma1 write to ddr",
"MetricName": "imx95_ddr_write.isp_in_dma1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isp input dma2 read from ddr",
"MetricName": "imx95_ddr_read.isp_in_dma2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isp input dma2 write to ddr",
"MetricName": "imx95_ddr_write.isp_in_dma2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isp output dma1 read from ddr",
"MetricName": "imx95_ddr_read.isp_out_dma1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isp output dma1 write to ddr",
"MetricName": "imx95_ddr_write.isp_out_dma1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isp output dma2 read from ddr",
"MetricName": "imx95_ddr_read.isp_out_dma2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of isp output dma2 write to ddr",
"MetricName": "imx95_ddr_write.isp_out_dma2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all camera submodules read from ddr",
"MetricName": "imx95_ddr_read.camera_all",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x380\\,axi_id\\=0x200@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ + imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all camera submodules write to ddr (part1)",
"MetricName": "imx95_ddr_write.camera_all_1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x200@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all camera submodules write to ddr (part2)",
"MetricName": "imx95_ddr_write.camera_all_2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all camera submodules write to ddr (part3)",
"MetricName": "imx95_ddr_write.camera_all_3",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display layer0 read from ddr",
"MetricName": "imx95_ddr_read.disp_layer0",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x2f0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display layer0 write to ddr",
"MetricName": "imx95_ddr_write.disp_layer0",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2f0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display layer1 read from ddr",
"MetricName": "imx95_ddr_read.disp_layer1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x300@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display layer1 write to ddr",
"MetricName": "imx95_ddr_write.disp_layer1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x300@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display layer2 read from ddr",
"MetricName": "imx95_ddr_read.disp_layer2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x310@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display layer2 write to ddr",
"MetricName": "imx95_ddr_write.disp_layer2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x310@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display layer3 read from ddr",
"MetricName": "imx95_ddr_read.disp_layer3",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x320@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display layer3 write to ddr",
"MetricName": "imx95_ddr_write.disp_layer3",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x320@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display layer4 read from ddr",
"MetricName": "imx95_ddr_read.disp_layer4",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x330@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display layer4 write to ddr",
"MetricName": "imx95_ddr_write.disp_layer4",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x330@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display layer5 read from ddr",
"MetricName": "imx95_ddr_read.disp_layer5",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x340@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display layer5 write to ddr",
"MetricName": "imx95_ddr_write.disp_layer5",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x340@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display blitter read from ddr",
"MetricName": "imx95_ddr_read.disp_blit",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x350@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display blitter write to ddr",
"MetricName": "imx95_ddr_write.disp_blit",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x350@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display command sequencer read from ddr",
"MetricName": "imx95_ddr_read.disp_cmd",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x360@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of display command sequencer write to ddr",
"MetricName": "imx95_ddr_write.disp_cmd",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x360@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all display submodules read from ddr",
"MetricName": "imx95_ddr_read.disp_all",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x300\\,axi_id\\=0x300@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all display submodules write to ddr (part1)",
"MetricName": "imx95_ddr_write.disp_all_1",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x300\\,axi_id\\=0x300@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
},
{
"BriefDescription": "bytes of all display submodules write to ddr (part2)",
"MetricName": "imx95_ddr_write.disp_all_2",
"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32",
"ScaleUnit": "9.765625e-4KB",
"Unit": "imx9_ddr",
"Compat": "imx95"
}
]

1084
tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json
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184
tools/perf/pmu-events/arch/x86/alderlake/cache.json
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@ -1,6 +1,7 @@
[
{
"BriefDescription": "L1D.HWPF_MISS",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.HWPF_MISS",
"SampleAfterValue": "1000003",
@ -9,6 +10,7 @@
},
{
"BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@ -18,6 +20,7 @@
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
"Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
@ -27,6 +30,7 @@
},
{
"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x48",
@ -38,6 +42,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS",
"Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALL",
@ -47,6 +52,7 @@
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
"Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALLS",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
@ -56,6 +62,7 @@
},
{
"BriefDescription": "Number of L1D misses that are outstanding",
"Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@ -65,6 +72,7 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@ -75,6 +83,7 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
"Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@ -84,6 +93,7 @@
},
{
"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.USELESS_HWPF",
"PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
@ -93,6 +103,7 @@
},
{
"BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.ALL",
"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]",
@ -102,6 +113,7 @@
},
{
"BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS]",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.MISS",
"PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]",
@ -111,6 +123,7 @@
},
{
"BriefDescription": "L2 code requests",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts the total number of L2 code requests.",
@ -120,6 +133,7 @@
},
{
"BriefDescription": "Demand Data Read access L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
@ -129,6 +143,7 @@
},
{
"BriefDescription": "Demand requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"PublicDescription": "Counts demand requests that miss L2 cache.",
@ -138,6 +153,7 @@
},
{
"BriefDescription": "L2_RQSTS.ALL_HWPF",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_HWPF",
"SampleAfterValue": "200003",
@ -146,6 +162,7 @@
},
{
"BriefDescription": "RFO requests to L2 cache.",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@ -155,6 +172,7 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
@ -164,6 +182,7 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
@ -173,6 +192,7 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
@ -182,6 +202,7 @@
},
{
"BriefDescription": "Demand Data Read miss L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",
@ -191,6 +212,7 @@
},
{
"BriefDescription": "L2_RQSTS.HWPF_MISS",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.HWPF_MISS",
"SampleAfterValue": "200003",
@ -199,6 +221,7 @@
},
{
"BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.MISS]",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]",
@ -208,6 +231,7 @@
},
{
"BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]",
@ -217,6 +241,7 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache.",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
@ -226,6 +251,7 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
@ -235,6 +261,7 @@
},
{
"BriefDescription": "SW prefetch requests that hit L2 cache.",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_HIT",
"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
@ -244,6 +271,7 @@
},
{
"BriefDescription": "SW prefetch requests that miss L2 cache.",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_MISS",
"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
@ -251,17 +279,29 @@
"UMask": "0x28",
"Unit": "cpu_core"
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "Counts L2 writebacks that access L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x40",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x41",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
@ -271,15 +311,17 @@
},
{
"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x4f",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
@ -289,6 +331,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
@ -298,6 +341,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",
@ -307,6 +351,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
@ -316,6 +361,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
@ -325,6 +371,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD",
"SampleAfterValue": "200003",
@ -333,6 +380,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
"SampleAfterValue": "200003",
@ -341,6 +389,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
"SampleAfterValue": "200003",
@ -349,6 +398,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
"PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
@ -358,6 +408,7 @@
},
{
"BriefDescription": "Retired load instructions.",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
@ -369,6 +420,7 @@
},
{
"BriefDescription": "Retired store instructions.",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
@ -380,6 +432,7 @@
},
{
"BriefDescription": "All retired memory instructions.",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ANY",
@ -391,6 +444,7 @@
},
{
"BriefDescription": "Retired load instructions with locked access.",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
@ -402,6 +456,7 @@
},
{
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
@ -413,6 +468,7 @@
},
{
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
@ -424,6 +480,7 @@
},
{
"BriefDescription": "Retired load instructions that miss the STLB.",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
@ -435,6 +492,7 @@
},
{
"BriefDescription": "Retired store instructions that miss the STLB.",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
@ -446,6 +504,7 @@
},
{
"BriefDescription": "Completed demand load uops that miss the L1 d-cache.",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY",
"PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)",
@ -455,6 +514,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
@ -466,6 +526,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
@ -477,6 +538,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
@ -488,6 +550,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@ -499,6 +562,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
@ -510,6 +574,7 @@
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
@ -521,6 +586,7 @@
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
@ -532,6 +598,7 @@
},
{
"BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd4",
"EventName": "MEM_LOAD_MISC_RETIRED.UC",
@ -543,6 +610,7 @@
},
{
"BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
@ -554,6 +622,7 @@
},
{
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
@ -565,6 +634,7 @@
},
{
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
@ -576,6 +646,7 @@
},
{
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
@ -587,6 +658,7 @@
},
{
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
@ -598,6 +670,7 @@
},
{
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
@ -609,6 +682,7 @@
},
{
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
@ -620,6 +694,7 @@
},
{
"BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
@ -630,6 +705,7 @@
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
@ -640,6 +716,7 @@
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
@ -650,6 +727,7 @@
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.ALL",
"SampleAfterValue": "20003",
@ -658,6 +736,7 @@
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",
"SampleAfterValue": "20003",
@ -666,6 +745,7 @@
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.RSV",
"SampleAfterValue": "20003",
@ -674,6 +754,7 @@
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",
"SampleAfterValue": "20003",
@ -682,6 +763,7 @@
},
{
"BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
"Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "MEM_STORE_RETIRED.L2_HIT",
"SampleAfterValue": "200003",
@ -690,6 +772,7 @@
},
{
"BriefDescription": "Counts the number of load uops retired.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
@ -701,6 +784,7 @@
},
{
"BriefDescription": "Counts the number of store uops retired.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
@ -712,6 +796,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
@ -725,6 +810,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
@ -738,6 +824,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
@ -751,6 +838,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
@ -764,6 +852,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
@ -777,6 +866,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
@ -790,6 +880,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
@ -803,6 +894,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
@ -814,8 +906,20 @@
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of load uops retired that performed one or more locks.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x21",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of retired split load uops.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
@ -826,6 +930,7 @@
},
{
"BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
@ -837,6 +942,7 @@
},
{
"BriefDescription": "Retired memory uops for any access",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe5",
"EventName": "MEM_UOP_RETIRED.ANY",
"PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses",
@ -846,6 +952,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@ -856,6 +963,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@ -866,6 +974,7 @@
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@ -876,6 +985,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@ -886,6 +996,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@ -896,6 +1007,7 @@
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@ -906,6 +1018,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@ -916,6 +1029,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@ -926,6 +1040,7 @@
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@ -936,6 +1051,7 @@
},
{
"BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
"SampleAfterValue": "100003",
@ -944,6 +1060,7 @@
},
{
"BriefDescription": "Demand and prefetch data reads",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.DATA_RD",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@ -951,8 +1068,19 @@
"UMask": "0x8",
"Unit": "cpu_core"
},
{
"BriefDescription": "Cacheable and noncacheable code read requests",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
"SampleAfterValue": "100003",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@ -960,8 +1088,19 @@
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
"SampleAfterValue": "100003",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
"Counter": "0,1,2,3",
"Deprecated": "1",
"Errata": "ADL038",
"EventCode": "0x20",
@ -972,6 +1111,7 @@
},
{
"BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
"Counter": "0,1,2,3",
"CounterMask": "1",
"Errata": "ADL038",
"EventCode": "0x20",
@ -980,8 +1120,20 @@
"UMask": "0x8",
"Unit": "cpu_core"
},
{
"BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
"PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
"BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@ -991,6 +1143,7 @@
},
{
"BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@ -1001,6 +1154,7 @@
},
{
"BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
"Counter": "0,1,2,3",
"Errata": "ADL038",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
@ -1008,8 +1162,19 @@
"UMask": "0x8",
"Unit": "cpu_core"
},
{
"BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
"PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
"BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
@ -1019,6 +1184,7 @@
},
{
"BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",
"Counter": "0,1,2,3",
"EventCode": "0x2c",
"EventName": "SQ_MISC.BUS_LOCK",
"PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.",
@ -1026,8 +1192,18 @@
"UMask": "0x10",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.ANY",
"SampleAfterValue": "100003",
"UMask": "0xf",
"Unit": "cpu_core"
},
{
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.NTA",
"PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
@ -1037,6 +1213,7 @@
},
{
"BriefDescription": "Number of PREFETCHW instructions executed.",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
"PublicDescription": "Counts the number of PREFETCHW instructions executed.",
@ -1046,6 +1223,7 @@
},
{
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.T0",
"PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
@ -1055,6 +1233,7 @@
},
{
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
"PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
@ -1064,6 +1243,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ICACHE",
"SampleAfterValue": "1000003",

20
tools/perf/pmu-events/arch/x86/alderlake/floating-point.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "ARITH.FPDIV_ACTIVE",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb0",
"EventName": "ARITH.FPDIV_ACTIVE",
@ -10,6 +11,7 @@
},
{
"BriefDescription": "Counts all microcode FP assists.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.FP",
"PublicDescription": "Counts all microcode Floating Point assists.",
@ -19,6 +21,7 @@
},
{
"BriefDescription": "ASSISTS.SSE_AVX_MIX",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.SSE_AVX_MIX",
"SampleAfterValue": "1000003",
@ -27,6 +30,7 @@
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_0",
"SampleAfterValue": "2000003",
@ -35,6 +39,7 @@
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_1",
"SampleAfterValue": "2000003",
@ -43,6 +48,7 @@
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_5",
"SampleAfterValue": "2000003",
@ -51,6 +57,7 @@
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.V0",
"SampleAfterValue": "2000003",
@ -59,6 +66,7 @@
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.V1",
"SampleAfterValue": "2000003",
@ -67,6 +75,7 @@
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.V2",
"SampleAfterValue": "2000003",
@ -75,6 +84,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -84,6 +94,7 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -93,6 +104,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -102,6 +114,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -111,6 +124,7 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -120,6 +134,7 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -129,6 +144,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -138,6 +154,7 @@
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -147,6 +164,7 @@
},
{
"BriefDescription": "Number of any Vector retired FP arithmetic instructions",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.VECTOR",
"PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -156,6 +174,7 @@
},
{
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
@ -165,6 +184,7 @@
},
{
"BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.FPDIV",
"PEBS": "1",

56
tools/perf/pmu-events/arch/x86/alderlake/frontend.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
@ -10,6 +11,7 @@
},
{
"BriefDescription": "Clears due to Unknown Branches.",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
@ -19,6 +21,7 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "DECODE.LCP",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
@ -28,6 +31,7 @@
},
{
"BriefDescription": "Cycles the Microcode Sequencer is busy.",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "DECODE.MS_BUSY",
"SampleAfterValue": "500009",
@ -36,6 +40,7 @@
},
{
"BriefDescription": "DSB-to-MITE switch true penalty cycles.",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
@ -45,6 +50,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced DSB miss.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7",
@ -57,6 +63,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7",
@ -69,6 +76,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7",
@ -81,6 +89,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7",
@ -93,6 +102,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7",
@ -105,6 +115,7 @@
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7",
@ -117,6 +128,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7",
@ -129,6 +141,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7",
@ -141,6 +154,7 @@
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7",
@ -153,6 +167,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7",
@ -165,6 +180,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7",
@ -177,6 +193,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
@ -189,6 +206,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7",
@ -201,6 +219,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7",
@ -213,6 +232,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
@ -225,6 +245,7 @@
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7",
@ -237,6 +258,7 @@
},
{
"BriefDescription": "FRONTEND_RETIRED.MS_FLOWS",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.MS_FLOWS",
"MSRIndex": "0x3F7",
@ -248,6 +270,7 @@
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7",
@ -260,6 +283,7 @@
},
{
"BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
"MSRIndex": "0x3F7",
@ -271,6 +295,7 @@
},
{
"BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
@ -280,6 +305,7 @@
},
{
"BriefDescription": "Counts the number of instruction cache misses.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
@ -289,6 +315,7 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE_DATA.STALLS",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.",
@ -296,8 +323,20 @@
"UMask": "0x4",
"Unit": "cpu_core"
},
{
"BriefDescription": "ICACHE_DATA.STALL_PERIODS",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x80",
"EventName": "ICACHE_DATA.STALL_PERIODS",
"SampleAfterValue": "500009",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_TAG.STALLS",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
@ -307,6 +346,7 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_ANY",
@ -317,16 +357,18 @@
},
{
"BriefDescription": "Cycles DSB is delivering optimal number of Uops",
"Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.",
"SampleAfterValue": "2000003",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
@ -336,6 +378,7 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_ANY",
@ -346,6 +389,7 @@
},
{
"BriefDescription": "Cycles MITE is delivering optimal number of Uops",
"Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_OK",
@ -356,6 +400,7 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@ -365,6 +410,7 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES_ANY",
@ -375,6 +421,7 @@
},
{
"BriefDescription": "Number of switches from DSB or MITE to the MS",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@ -386,6 +433,7 @@
},
{
"BriefDescription": "Uops delivered to IDQ while MS is busy",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS).",
@ -395,6 +443,7 @@
},
{
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x9c",
"EventName": "IDQ_BUBBLES.CORE",
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]",
@ -404,6 +453,7 @@
},
{
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x9c",
"EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE",
@ -414,6 +464,7 @@
},
{
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9c",
"EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK",
@ -425,6 +476,7 @@
},
{
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CORE]",
@ -434,6 +486,7 @@
},
{
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@ -444,6 +497,7 @@
},
{
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",

44
tools/perf/pmu-events/arch/x86/alderlake/memory.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
@ -10,6 +11,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.ANY_AT_RET",
"SampleAfterValue": "1000003",
@ -18,6 +20,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.L1_BOUND_AT_RET",
"SampleAfterValue": "1000003",
@ -26,6 +29,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.L1_MISS_AT_RET",
"SampleAfterValue": "1000003",
@ -34,6 +38,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.OTHER_AT_RET",
"PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.",
@ -43,6 +48,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.PGWALK_AT_RET",
"SampleAfterValue": "1000003",
@ -51,6 +57,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.ST_ADDR_AT_RET",
"SampleAfterValue": "1000003",
@ -59,6 +66,7 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "20003",
@ -67,6 +75,7 @@
},
{
"BriefDescription": "Number of machine clears due to memory ordering conflicts.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
@ -76,6 +85,7 @@
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",
@ -85,6 +95,7 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",
@ -94,6 +105,7 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",
@ -104,6 +116,7 @@
},
{
"BriefDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "9",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",
@ -112,8 +125,23 @@
"UMask": "0x9",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024",
"MSRIndex": "0x3F6",
"MSRValue": "0x400",
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "53",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@ -127,6 +155,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@ -140,6 +169,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@ -153,6 +183,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@ -166,6 +197,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@ -179,6 +211,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@ -192,6 +225,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@ -205,6 +239,7 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@ -218,6 +253,7 @@
},
{
"BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
"Counter": "0",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
@ -229,6 +265,7 @@
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@ -239,6 +276,7 @@
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@ -249,6 +287,7 @@
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@ -259,6 +298,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@ -269,6 +309,7 @@
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@ -279,6 +320,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@ -289,6 +331,7 @@
},
{
"BriefDescription": "Counts demand data read requests that miss the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
"SampleAfterValue": "100003",
@ -297,6 +340,7 @@
},
{
"BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
"PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache.",

23
tools/perf/pmu-events/arch/x86/alderlake/metricgroups.json
View File

@ -5,8 +5,21 @@
"BigFootprint": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Branches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"C0Wait": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"CacheHits": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Compute": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
@ -22,14 +35,17 @@
"Frontend": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"HPC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"IcMiss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Ifetch": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"InsType": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"IntVector": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"L2Evicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"LSD": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Load_Store_Miss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"MachineClears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Machine_Clears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Mem": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"MemOffcore": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Mem_Exec": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"MemoryBW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"MemoryBound": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"MemoryLat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
@ -60,6 +76,7 @@
"TopdownL4": "Metrics for top-down breakdown at level 4",
"TopdownL5": "Metrics for top-down breakdown at level 5",
"TopdownL6": "Metrics for top-down breakdown at level 6",
"load_store_bound": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"tma_L1_group": "Metrics for top-down breakdown at level 1",
"tma_L2_group": "Metrics for top-down breakdown at level 2",
"tma_L3_group": "Metrics for top-down breakdown at level 3",
@ -68,10 +85,8 @@
"tma_L6_group": "Metrics for top-down breakdown at level 6",
"tma_alu_op_utilization_group": "Metrics contributing to tma_alu_op_utilization category",
"tma_assists_group": "Metrics contributing to tma_assists category",
"tma_backend_bound_aux_group": "Metrics contributing to tma_backend_bound_aux category",
"tma_backend_bound_group": "Metrics contributing to tma_backend_bound category",
"tma_bad_speculation_group": "Metrics contributing to tma_bad_speculation category",
"tma_base_group": "Metrics contributing to tma_base category",
"tma_branch_mispredicts_group": "Metrics contributing to tma_branch_mispredicts category",
"tma_branch_resteers_group": "Metrics contributing to tma_branch_resteers category",
"tma_core_bound_group": "Metrics contributing to tma_core_bound category",
@ -84,6 +99,8 @@
"tma_fp_vector_group": "Metrics contributing to tma_fp_vector category",
"tma_frontend_bound_group": "Metrics contributing to tma_frontend_bound category",
"tma_heavy_operations_group": "Metrics contributing to tma_heavy_operations category",
"tma_ifetch_bandwidth_group": "Metrics contributing to tma_ifetch_bandwidth category",
"tma_ifetch_latency_group": "Metrics contributing to tma_ifetch_latency category",
"tma_int_operations_group": "Metrics contributing to tma_int_operations category",
"tma_issue2P": "Metrics related by the issue $issue2P",
"tma_issueBM": "Metrics related by the issue $issueBM",
@ -110,11 +127,9 @@
"tma_load_op_utilization_group": "Metrics contributing to tma_load_op_utilization category",
"tma_machine_clears_group": "Metrics contributing to tma_machine_clears category",
"tma_mem_latency_group": "Metrics contributing to tma_mem_latency category",
"tma_mem_scheduler_group": "Metrics contributing to tma_mem_scheduler category",
"tma_memory_bound_group": "Metrics contributing to tma_memory_bound category",
"tma_microcode_sequencer_group": "Metrics contributing to tma_microcode_sequencer category",
"tma_mite_group": "Metrics contributing to tma_mite category",
"tma_nuke_group": "Metrics contributing to tma_nuke category",
"tma_other_light_ops_group": "Metrics contributing to tma_other_light_ops category",
"tma_ports_utilization_group": "Metrics contributing to tma_ports_utilization category",
"tma_ports_utilized_0_group": "Metrics contributing to tma_ports_utilized_0 category",

37
tools/perf/pmu-events/arch/x86/alderlake/other.json
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@ -1,6 +1,7 @@
[
{
"BriefDescription": "ASSISTS.HARDWARE",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.HARDWARE",
"SampleAfterValue": "100003",
@ -9,6 +10,7 @@
},
{
"BriefDescription": "ASSISTS.PAGE_FAULT",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.PAGE_FAULT",
"SampleAfterValue": "1000003",
@ -17,6 +19,7 @@
},
{
"BriefDescription": "CORE_POWER.LICENSE_1",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LICENSE_1",
"SampleAfterValue": "200003",
@ -25,6 +28,7 @@
},
{
"BriefDescription": "CORE_POWER.LICENSE_2",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LICENSE_2",
"SampleAfterValue": "200003",
@ -33,6 +37,7 @@
},
{
"BriefDescription": "CORE_POWER.LICENSE_3",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LICENSE_3",
"SampleAfterValue": "200003",
@ -41,6 +46,7 @@
},
{
"BriefDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0xe4",
"EventName": "LBR_INSERTS.ANY",
@ -51,6 +57,7 @@
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.COREWB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@ -61,6 +68,7 @@
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@ -71,6 +79,7 @@
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@ -81,6 +90,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
@ -91,6 +101,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@ -101,6 +112,7 @@
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@ -111,6 +123,7 @@
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@ -121,6 +134,7 @@
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@ -131,6 +145,7 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa5",
"EventName": "RS.EMPTY",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)",
@ -140,6 +155,7 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xa5",
@ -150,8 +166,18 @@
"UMask": "0x7",
"Unit": "cpu_core"
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty due to a resource in the back-end",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa5",
"EventName": "RS.EMPTY_RESOURCE",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Deprecated": "1",
"EdgeDetect": "1",
@ -164,6 +190,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY",
"Counter": "0,1,2,3,4,5,6,7",
"Deprecated": "1",
"EventCode": "0xa5",
"EventName": "RS_EMPTY.CYCLES",
@ -171,8 +198,18 @@
"UMask": "0x7",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state)",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x75",
"EventName": "SERIALIZATION.C01_MS_SCB",
"SampleAfterValue": "200003",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Cycles the uncore cannot take further requests",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x2d",
"EventName": "XQ.FULL_CYCLES",

214
tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
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19
tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json
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@ -1,6 +1,7 @@
[
{
"BriefDescription": "Number of requests allocated in Coherency Tracker.",
"Counter": "0,1",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
@ -9,56 +10,69 @@
},
{
"BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
"Counter": "0",
"EventCode": "0x85",
"EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
"Counter": "0",
"EventCode": "0x85",
"EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD",
"Counter": "0,1",
"Deprecated": "1",
"EventCode": "0x81",
"EventName": "UNC_ARB_DAT_REQUESTS.RD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
"Counter": "0",
"Deprecated": "1",
"EventCode": "0x85",
"EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]",
"Counter": "0",
"EventCode": "0x80",
"EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
"Counter": "0",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
@ -67,14 +81,17 @@
},
{
"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]",
"Counter": "0",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.RD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
@ -83,8 +100,10 @@
},
{
"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.RD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"

25
tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json
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@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).",
"Counter": "0",
"EventCode": "0xff",
"EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
"PerPkg": "1",
@ -10,6 +11,7 @@
},
{
"BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
"Counter": "1",
"EventCode": "0xff",
"EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
"PerPkg": "1",
@ -18,6 +20,7 @@
},
{
"BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).",
"Counter": "3",
"EventCode": "0xff",
"EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
"PerPkg": "1",
@ -27,6 +30,7 @@
},
{
"BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
"Counter": "4",
"EventCode": "0xff",
"EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
"PerPkg": "1",
@ -35,6 +39,7 @@
},
{
"BriefDescription": "ACT command for a read request sent to DRAM",
"Counter": "0,1,2,3,4",
"EventCode": "0x24",
"EventName": "UNC_M_ACT_COUNT_RD",
"PerPkg": "1",
@ -42,6 +47,7 @@
},
{
"BriefDescription": "ACT command sent to DRAM",
"Counter": "0,1,2,3,4",
"EventCode": "0x26",
"EventName": "UNC_M_ACT_COUNT_TOTAL",
"PerPkg": "1",
@ -49,6 +55,7 @@
},
{
"BriefDescription": "ACT command for a write request sent to DRAM",
"Counter": "0,1,2,3,4",
"EventCode": "0x25",
"EventName": "UNC_M_ACT_COUNT_WR",
"PerPkg": "1",
@ -56,6 +63,7 @@
},
{
"BriefDescription": "Read CAS command sent to DRAM",
"Counter": "0,1,2,3,4",
"EventCode": "0x22",
"EventName": "UNC_M_CAS_COUNT_RD",
"PerPkg": "1",
@ -63,6 +71,7 @@
},
{
"BriefDescription": "Write CAS command sent to DRAM",
"Counter": "0,1,2,3,4",
"EventCode": "0x23",
"EventName": "UNC_M_CAS_COUNT_WR",
"PerPkg": "1",
@ -70,6 +79,7 @@
},
{
"BriefDescription": "Number of clocks",
"Counter": "0,1,2,3,4",
"EventCode": "0x01",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
@ -77,6 +87,7 @@
},
{
"BriefDescription": "incoming read request page status is Page Empty",
"Counter": "0,1,2,3,4",
"EventCode": "0x1D",
"EventName": "UNC_M_DRAM_PAGE_EMPTY_RD",
"PerPkg": "1",
@ -84,6 +95,7 @@
},
{
"BriefDescription": "incoming write request page status is Page Empty",
"Counter": "0,1,2,3,4",
"EventCode": "0x20",
"EventName": "UNC_M_DRAM_PAGE_EMPTY_WR",
"PerPkg": "1",
@ -91,6 +103,7 @@
},
{
"BriefDescription": "incoming read request page status is Page Hit",
"Counter": "0,1,2,3,4",
"EventCode": "0x1C",
"EventName": "UNC_M_DRAM_PAGE_HIT_RD",
"PerPkg": "1",
@ -98,6 +111,7 @@
},
{
"BriefDescription": "incoming write request page status is Page Hit",
"Counter": "0,1,2,3,4",
"EventCode": "0x1F",
"EventName": "UNC_M_DRAM_PAGE_HIT_WR",
"PerPkg": "1",
@ -105,6 +119,7 @@
},
{
"BriefDescription": "incoming read request page status is Page Miss",
"Counter": "0,1,2,3,4",
"EventCode": "0x1E",
"EventName": "UNC_M_DRAM_PAGE_MISS_RD",
"PerPkg": "1",
@ -112,6 +127,7 @@
},
{
"BriefDescription": "incoming write request page status is Page Miss",
"Counter": "0,1,2,3,4",
"EventCode": "0x21",
"EventName": "UNC_M_DRAM_PAGE_MISS_WR",
"PerPkg": "1",
@ -119,6 +135,7 @@
},
{
"BriefDescription": "Any Rank at Hot state",
"Counter": "0,1,2,3,4",
"EventCode": "0x19",
"EventName": "UNC_M_DRAM_THERMAL_HOT",
"PerPkg": "1",
@ -126,6 +143,7 @@
},
{
"BriefDescription": "Any Rank at Warm state",
"Counter": "0,1,2,3,4",
"EventCode": "0x1A",
"EventName": "UNC_M_DRAM_THERMAL_WARM",
"PerPkg": "1",
@ -133,6 +151,7 @@
},
{
"BriefDescription": "Incoming read prefetch request from IA.",
"Counter": "0,1,2,3,4",
"EventCode": "0x0A",
"EventName": "UNC_M_PREFETCH_RD",
"PerPkg": "1",
@ -140,6 +159,7 @@
},
{
"BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration",
"Counter": "0,1,2,3,4",
"EventCode": "0x28",
"EventName": "UNC_M_PRE_COUNT_IDLE",
"PerPkg": "1",
@ -147,6 +167,7 @@
},
{
"BriefDescription": "PRE command sent to DRAM for a read/write request",
"Counter": "0,1,2,3,4",
"EventCode": "0x27",
"EventName": "UNC_M_PRE_COUNT_PAGE_MISS",
"PerPkg": "1",
@ -154,6 +175,7 @@
},
{
"BriefDescription": "Incoming VC0 read request",
"Counter": "0,1,2,3,4",
"EventCode": "0x02",
"EventName": "UNC_M_VC0_REQUESTS_RD",
"PerPkg": "1",
@ -161,6 +183,7 @@
},
{
"BriefDescription": "Incoming VC0 write request",
"Counter": "0,1,2,3,4",
"EventCode": "0x03",
"EventName": "UNC_M_VC0_REQUESTS_WR",
"PerPkg": "1",
@ -168,6 +191,7 @@
},
{
"BriefDescription": "Incoming VC1 read request",
"Counter": "0,1,2,3,4",
"EventCode": "0x04",
"EventName": "UNC_M_VC1_REQUESTS_RD",
"PerPkg": "1",
@ -175,6 +199,7 @@
},
{
"BriefDescription": "Incoming VC1 write request",
"Counter": "0,1,2,3,4",
"EventCode": "0x05",
"EventName": "UNC_M_VC1_REQUESTS_WR",
"PerPkg": "1",

1
tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json
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@ -1,6 +1,7 @@
[
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Counter": "FIXED",
"EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1",

26
tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json
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@ -1,6 +1,7 @@
[
{
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
@ -10,6 +11,7 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
@ -20,6 +22,7 @@
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
@ -29,6 +32,7 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -38,6 +42,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -47,6 +52,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -56,6 +62,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -65,6 +72,7 @@
},
{
"BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
@ -74,6 +82,7 @@
},
{
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
@ -83,6 +92,7 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
@ -93,6 +103,7 @@
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
@ -102,6 +113,7 @@
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -111,6 +123,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -120,6 +133,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -129,6 +143,7 @@
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -138,6 +153,7 @@
},
{
"BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
@ -147,6 +163,7 @@
},
{
"BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSED_WALK",
"SampleAfterValue": "1000003",
@ -155,6 +172,7 @@
},
{
"BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.PDE_CACHE_MISS",
"SampleAfterValue": "2000003",
@ -163,6 +181,7 @@
},
{
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.STLB_HIT",
"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
@ -172,6 +191,7 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
@ -182,6 +202,7 @@
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
@ -191,6 +212,7 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@ -200,6 +222,7 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@ -209,6 +232,7 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@ -218,6 +242,7 @@
},
{
"BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_PENDING",
"PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
@ -227,6 +252,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.DTLB_MISS_AT_RET",
"SampleAfterValue": "1000003",

704
tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json
View File

@ -85,39 +85,28 @@
"ScaleUnit": "1SMI#"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.",
"MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / tma_info_core_slots",
"MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
"MetricName": "tma_alloc_restriction",
"MetricThreshold": "tma_alloc_restriction > 0.1",
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions",
"MetricExpr": "tma_core_bound",
"MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
"MetricName": "tma_allocation_restriction",
"MetricThreshold": "tma_allocation_restriction > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.1)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls",
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls",
"DefaultMetricgroupName": "TopdownL1",
"MetricExpr": "TOPDOWN_BE_BOUND.ALL / tma_info_core_slots",
"MetricExpr": "TOPDOWN_BE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "Default;TopdownL1;tma_L1_group",
"MetricName": "tma_backend_bound",
"MetricThreshold": "tma_backend_bound > 0.1",
"MetricgroupNoGroup": "TopdownL1;Default",
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls",
"DefaultMetricgroupName": "TopdownL1",
"MetricExpr": "tma_backend_bound",
"MetricGroup": "Default;TopdownL1;tma_L1_group",
"MetricName": "tma_backend_bound_aux",
"MetricThreshold": "tma_backend_bound_aux > 0.2",
"MetricgroupNoGroup": "TopdownL1;Default",
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation.",
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear",
"DefaultMetricgroupName": "TopdownL1",
"MetricExpr": "(tma_info_core_slots - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / tma_info_core_slots",
"MetricExpr": "(5 * CPU_CLK_UNHALTED.CORE - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "Default;TopdownL1;tma_L1_group",
"MetricName": "tma_bad_speculation",
"MetricThreshold": "tma_bad_speculation > 0.15",
@ -126,127 +115,68 @@
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of uops that are not from the microsequencer.",
"MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / tma_info_core_slots",
"MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group",
"MetricName": "tma_base",
"MetricThreshold": "tma_base > 0.6",
"MetricgroupNoGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend",
"MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / tma_info_core_slots",
"MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group",
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend",
"MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
"MetricName": "tma_branch_detect",
"MetricThreshold": "tma_branch_detect > 0.05",
"PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"MetricThreshold": "tma_branch_detect > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
"PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts.",
"MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / tma_info_core_slots",
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts",
"MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"MetricThreshold": "tma_branch_mispredicts > 0.05",
"MetricThreshold": "tma_branch_mispredicts > 0.05 & tma_bad_speculation > 0.15",
"MetricgroupNoGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
"MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / tma_info_core_slots",
"MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group",
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
"MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
"MetricName": "tma_branch_resteer",
"MetricThreshold": "tma_branch_resteer > 0.05",
"MetricThreshold": "tma_branch_resteer > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).",
"MetricExpr": "TOPDOWN_FE_BOUND.CISC / tma_info_core_slots",
"MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).",
"MetricExpr": "TOPDOWN_FE_BOUND.CISC / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
"MetricName": "tma_cisc",
"MetricThreshold": "tma_cisc > 0.05",
"MetricThreshold": "tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls.",
"MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
"BriefDescription": "Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation",
"MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_core_bound",
"MetricThreshold": "tma_core_bound > 0.1",
"MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.1",
"MetricgroupNoGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.",
"MetricExpr": "TOPDOWN_FE_BOUND.DECODE / tma_info_core_slots",
"MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.",
"MetricExpr": "TOPDOWN_FE_BOUND.DECODE / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
"MetricName": "tma_decode",
"MetricThreshold": "tma_decode > 0.05",
"MetricThreshold": "tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory disambiguation.",
"MetricExpr": "tma_nuke * (MACHINE_CLEARS.DISAMBIGUATION / MACHINE_CLEARS.SLOW)",
"MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group",
"MetricName": "tma_disambiguation",
"MetricThreshold": "tma_disambiguation > 0.02",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
"MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks, 0) * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD",
"MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"MetricThreshold": "tma_dram_bound > 0.1",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear classified as a fast nuke due to memory ordering, memory disambiguation and memory renaming.",
"MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / tma_info_core_slots",
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming",
"MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group",
"MetricName": "tma_fast_nuke",
"MetricThreshold": "tma_fast_nuke > 0.05",
"MetricThreshold": "tma_fast_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
"MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / tma_info_core_slots",
"MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group",
"MetricName": "tma_fetch_bandwidth",
"MetricThreshold": "tma_fetch_bandwidth > 0.1",
"MetricgroupNoGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
"MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / tma_info_core_slots",
"MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group",
"MetricName": "tma_fetch_latency",
"MetricThreshold": "tma_fetch_latency > 0.15",
"MetricgroupNoGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to FP assists.",
"MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEARS.SLOW)",
"MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group",
"MetricName": "tma_fp_assist",
"MetricThreshold": "tma_fp_assist > 0.02",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of floating point divide operations per uop.",
"MetricExpr": "UOPS_RETIRED.FPDIV / tma_info_core_slots",
"MetricGroup": "TopdownL3;tma_L3_group;tma_base_group",
"MetricName": "tma_fpdiv_uops",
"MetricThreshold": "tma_fpdiv_uops > 0.2",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.",
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.",
"DefaultMetricgroupName": "TopdownL1",
"MetricExpr": "TOPDOWN_FE_BOUND.ALL / tma_info_core_slots",
"MetricExpr": "TOPDOWN_FE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "Default;TopdownL1;tma_L1_group",
"MetricName": "tma_frontend_bound",
"MetricThreshold": "tma_frontend_bound > 0.2",
@ -254,172 +184,282 @@
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.",
"MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / tma_info_core_slots",
"MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group",
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.",
"MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
"MetricName": "tma_icache_misses",
"MetricThreshold": "tma_icache_misses > 0.05",
"MetricThreshold": "tma_icache_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "",
"MetricExpr": "CPU_CLK_UNHALTED.CORE",
"MetricName": "tma_info_core_clks"
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
"MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group",
"MetricName": "tma_ifetch_bandwidth",
"MetricThreshold": "tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2",
"MetricgroupNoGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"BriefDescription": "",
"MetricExpr": "CPU_CLK_UNHALTED.CORE_P",
"MetricName": "tma_info_core_clks_p"
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations.",
"MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group",
"MetricName": "tma_ifetch_latency",
"MetricThreshold": "tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2",
"MetricgroupNoGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Percentage of time that retirement is stalled due to a first level data TLB miss",
"MetricExpr": "100 * (LD_HEAD.DTLB_MISS_AT_RET + LD_HEAD.PGWALK_AT_RET) / CPU_CLK_UNHALTED.CORE",
"MetricName": "tma_info_bottleneck_%_dtlb_miss_bound_cycles"
},
{
"BriefDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH / CPU_CLK_UNHALTED.CORE",
"MetricGroup": "Ifetch",
"MetricName": "tma_info_bottleneck_%_ifetch_miss_bound_cycles",
"PublicDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound"
},
{
"BriefDescription": "Percentage of time that retirement is stalled due to an L1 miss",
"MetricExpr": "100 * MEM_BOUND_STALLS.LOAD / CPU_CLK_UNHALTED.CORE",
"MetricGroup": "Load_Store_Miss",
"MetricName": "tma_info_bottleneck_%_load_miss_bound_cycles",
"PublicDescription": "Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound"
},
{
"BriefDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall",
"MetricExpr": "100 * LD_HEAD.ANY_AT_RET / CPU_CLK_UNHALTED.CORE",
"MetricGroup": "Mem_Exec",
"MetricName": "tma_info_bottleneck_%_mem_exec_bound_cycles",
"PublicDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound"
},
{
"BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
"MetricName": "tma_info_br_inst_mix_ipbranch"
},
{
"BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL",
"MetricName": "tma_info_br_inst_mix_ipcall"
},
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricName": "tma_info_br_inst_mix_ipfarbranch"
},
{
"BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken",
"MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN)",
"MetricName": "tma_info_br_inst_mix_ipmisp_cond_ntaken"
},
{
"BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was taken",
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN",
"MetricName": "tma_info_br_inst_mix_ipmisp_cond_taken"
},
{
"BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction",
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT",
"MetricName": "tma_info_br_inst_mix_ipmisp_indirect"
},
{
"BriefDescription": "Instructions per retired return Branch Misprediction",
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN",
"MetricName": "tma_info_br_inst_mix_ipmisp_ret"
},
{
"BriefDescription": "Instructions per retired Branch Misprediction",
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricName": "tma_info_br_inst_mix_ipmispredict"
},
{
"BriefDescription": "Ratio of all branches which mispredict",
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES",
"MetricName": "tma_info_br_mispredict_bound_branch_mispredict_ratio"
},
{
"BriefDescription": "Ratio between Mispredicted branches and unknown branches",
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY",
"MetricName": "tma_info_br_mispredict_bound_branch_mispredict_to_unknown_branch_ratio"
},
{
"BriefDescription": "Percentage of time that allocation is stalled due to load buffer full",
"MetricExpr": "100 * MEM_SCHEDULER_BLOCK.LD_BUF / CPU_CLK_UNHALTED.CORE",
"MetricName": "tma_info_buffer_stalls_%_load_buffer_stall_cycles"
},
{
"BriefDescription": "Percentage of time that allocation is stalled due to memory reservation stations full",
"MetricExpr": "100 * MEM_SCHEDULER_BLOCK.RSV / CPU_CLK_UNHALTED.CORE",
"MetricName": "tma_info_buffer_stalls_%_mem_rsv_stall_cycles"
},
{
"BriefDescription": "Percentage of time that allocation is stalled due to store buffer full",
"MetricExpr": "100 * MEM_SCHEDULER_BLOCK.ST_BUF / CPU_CLK_UNHALTED.CORE",
"MetricName": "tma_info_buffer_stalls_%_store_buffer_stall_cycles"
},
{
"BriefDescription": "Cycles Per Instruction",
"MetricExpr": "tma_info_core_clks / INST_RETIRED.ANY",
"MetricExpr": "CPU_CLK_UNHALTED.CORE / INST_RETIRED.ANY",
"MetricName": "tma_info_core_cpi"
},
{
"BriefDescription": "Instructions Per Cycle",
"MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks",
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.CORE",
"MetricName": "tma_info_core_ipc"
},
{
"BriefDescription": "",
"MetricExpr": "5 * tma_info_core_clks",
"MetricName": "tma_info_core_slots"
},
{
"BriefDescription": "Uops Per Instruction",
"MetricExpr": "UOPS_RETIRED.ALL / INST_RETIRED.ANY",
"MetricName": "tma_info_core_upi"
},
{
"BriefDescription": "Percent of instruction miss cost that hit in DRAM",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH",
"MetricName": "tma_info_frontend_inst_miss_cost_dramhit_percent"
},
{
"BriefDescription": "Percent of instruction miss cost that hit in the L2",
"BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH",
"MetricName": "tma_info_frontend_inst_miss_cost_l2hit_percent"
"MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2hit"
},
{
"BriefDescription": "Percent of instruction miss cost that hit in the L3",
"BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH",
"MetricName": "tma_info_frontend_inst_miss_cost_l3hit_percent"
"MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3hit"
},
{
"BriefDescription": "Ratio of all branches which mispredict",
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES",
"MetricName": "tma_info_inst_mix_branch_mispredict_ratio"
"BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss subsequently misses in the L3",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH",
"MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3miss"
},
{
"BriefDescription": "Ratio between Mispredicted branches and unknown branches",
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY",
"MetricName": "tma_info_inst_mix_branch_mispredict_to_unknown_branch_ratio"
"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2",
"MetricExpr": "100 * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD",
"MetricGroup": "load_store_bound",
"MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l2hit"
},
{
"BriefDescription": "Percentage of all uops which are FPDiv uops",
"MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL",
"MetricName": "tma_info_inst_mix_fpdiv_uop_ratio"
"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3",
"MetricExpr": "100 * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD",
"MetricGroup": "load_store_bound",
"MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l3hit"
},
{
"BriefDescription": "Percentage of all uops which are IDiv uops",
"MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL",
"MetricName": "tma_info_inst_mix_idiv_uop_ratio"
"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses the L3",
"MetricExpr": "100 * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD",
"MetricGroup": "load_store_bound",
"MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l3miss"
},
{
"BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
"MetricName": "tma_info_inst_mix_ipbranch"
"BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a pipeline block",
"MetricExpr": "100 * LD_HEAD.L1_BOUND_AT_RET / CPU_CLK_UNHALTED.CORE",
"MetricGroup": "load_store_bound",
"MetricName": "tma_info_load_store_bound_l1_bound"
},
{
"BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL",
"MetricName": "tma_info_inst_mix_ipcall"
"BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement",
"MetricExpr": "100 * (LD_HEAD.L1_BOUND_AT_RET + MEM_BOUND_STALLS.LOAD) / CPU_CLK_UNHALTED.CORE",
"MetricGroup": "load_store_bound",
"MetricName": "tma_info_load_store_bound_load_bound"
},
{
"BriefDescription": "Instructions per Far Branch",
"MetricExpr": "INST_RETIRED.ANY / (BR_INST_RETIRED.FAR_BRANCH / 2)",
"MetricName": "tma_info_inst_mix_ipfarbranch"
"BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full",
"MetricExpr": "100 * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL) * tma_mem_scheduler",
"MetricGroup": "load_store_bound",
"MetricName": "tma_info_load_store_bound_store_bound"
},
{
"BriefDescription": "Instructions per Load",
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
"MetricName": "tma_info_inst_mix_ipload"
"BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to memory disambiguation",
"MetricExpr": "1e3 * MACHINE_CLEARS.DISAMBIGUATION / INST_RETIRED.ANY",
"MetricName": "tma_info_machine_clear_bound_machine_clears_disamb_pki"
},
{
"BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken",
"MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN)",
"MetricName": "tma_info_inst_mix_ipmisp_cond_ntaken"
"BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to floating point assists",
"MetricExpr": "1e3 * MACHINE_CLEARS.FP_ASSIST / INST_RETIRED.ANY",
"MetricName": "tma_info_machine_clear_bound_machine_clears_fp_assist_pki"
},
{
"BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was taken",
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN",
"MetricName": "tma_info_inst_mix_ipmisp_cond_taken"
"BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to memory ordering",
"MetricExpr": "1e3 * MACHINE_CLEARS.MEMORY_ORDERING / INST_RETIRED.ANY",
"MetricName": "tma_info_machine_clear_bound_machine_clears_monuke_pki"
},
{
"BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction",
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT",
"MetricName": "tma_info_inst_mix_ipmisp_indirect"
"BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to memory renaming",
"MetricExpr": "1e3 * MACHINE_CLEARS.MRN_NUKE / INST_RETIRED.ANY",
"MetricName": "tma_info_machine_clear_bound_machine_clears_mrn_pki"
},
{
"BriefDescription": "Instructions per retired return Branch Misprediction",
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN",
"MetricName": "tma_info_inst_mix_ipmisp_ret"
"BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to page faults",
"MetricExpr": "1e3 * MACHINE_CLEARS.PAGE_FAULT / INST_RETIRED.ANY",
"MetricName": "tma_info_machine_clear_bound_machine_clears_page_fault_pki"
},
{
"BriefDescription": "Instructions per retired Branch Misprediction",
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricName": "tma_info_inst_mix_ipmispredict"
"BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to self-modifying code",
"MetricExpr": "1e3 * MACHINE_CLEARS.SMC / INST_RETIRED.ANY",
"MetricName": "tma_info_machine_clear_bound_machine_clears_smc_pki"
},
{
"BriefDescription": "Instructions per Store",
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
"MetricName": "tma_info_inst_mix_ipstore"
},
{
"BriefDescription": "Percentage of all uops which are ucode ops",
"MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL",
"MetricName": "tma_info_inst_mix_microcode_uop_ratio"
},
{
"BriefDescription": "Percentage of all uops which are x87 uops",
"MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL",
"MetricName": "tma_info_inst_mix_x87_uop_ratio"
},
{
"BriefDescription": "Percentage of total non-speculative loads with a address aliasing block",
"BriefDescription": "Percentage of total non-speculative loads with an address aliasing block",
"MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS",
"MetricName": "tma_info_l1_bound_address_alias_blocks"
},
{
"BriefDescription": "Percentage of total non-speculative loads that are splits",
"MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS",
"MetricName": "tma_info_l1_bound_load_splits"
"MetricName": "tma_info_mem_exec_blocks_%_loads_with_adressaliasing"
},
{
"BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block",
"MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS",
"MetricName": "tma_info_l1_bound_store_fwd_blocks"
"MetricName": "tma_info_mem_exec_blocks_%_loads_with_storefwdblk"
},
{
"BriefDescription": "Cycle cost per DRAM hit",
"MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
"MetricName": "tma_info_memory_cycles_per_demand_load_dram_hit"
"BriefDescription": "Percentage of Memory Execution Bound due to a first level data cache miss",
"MetricExpr": "100 * LD_HEAD.L1_MISS_AT_RET / LD_HEAD.ANY_AT_RET",
"MetricName": "tma_info_mem_exec_bound_%_loadhead_with_l1miss"
},
{
"BriefDescription": "Cycle cost per L2 hit",
"MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRED.L2_HIT",
"MetricName": "tma_info_memory_cycles_per_demand_load_l2_hit"
"BriefDescription": "Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc",
"MetricExpr": "100 * LD_HEAD.OTHER_AT_RET / LD_HEAD.ANY_AT_RET",
"MetricName": "tma_info_mem_exec_bound_%_loadhead_with_otherpipelineblks"
},
{
"BriefDescription": "Cycle cost per LLC hit",
"MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIRED.L3_HIT",
"MetricName": "tma_info_memory_cycles_per_demand_load_l3_hit"
"BriefDescription": "Percentage of Memory Execution Bound due to a pagewalk",
"MetricExpr": "100 * LD_HEAD.PGWALK_AT_RET / LD_HEAD.ANY_AT_RET",
"MetricName": "tma_info_mem_exec_bound_%_loadhead_with_pagewalk"
},
{
"BriefDescription": "load ops retired per 1000 instruction",
"MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
"MetricName": "tma_info_memory_memloadpki"
"BriefDescription": "Percentage of Memory Execution Bound due to a second level TLB miss",
"MetricExpr": "100 * LD_HEAD.DTLB_MISS_AT_RET / LD_HEAD.ANY_AT_RET",
"MetricName": "tma_info_mem_exec_bound_%_loadhead_with_stlbhit"
},
{
"BriefDescription": "Percentage of Memory Execution Bound due to a store forward address match",
"MetricExpr": "100 * LD_HEAD.ST_ADDR_AT_RET / LD_HEAD.ANY_AT_RET",
"MetricName": "tma_info_mem_exec_bound_%_loadhead_with_storefwding"
},
{
"BriefDescription": "Instructions per Load",
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
"MetricName": "tma_info_mem_mix_ipload"
},
{
"BriefDescription": "Instructions per Store",
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
"MetricName": "tma_info_mem_mix_ipstore"
},
{
"BriefDescription": "Percentage of total non-speculative loads that perform one or more locks",
"MetricExpr": "100 * MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_LOADS",
"MetricName": "tma_info_mem_mix_load_locks_ratio"
},
{
"BriefDescription": "Percentage of total non-speculative loads that are splits",
"MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS",
"MetricName": "tma_info_mem_mix_load_splits_ratio"
},
{
"BriefDescription": "Ratio of mem load uops to all uops",
"MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / UOPS_RETIRED.ALL",
"MetricName": "tma_info_mem_mix_memload_ratio"
},
{
"BriefDescription": "Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction",
"MetricExpr": "100 * SERIALIZATION.C01_MS_SCB / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricName": "tma_info_serialization _%_tpause_cycles"
},
{
"BriefDescription": "Average CPU Utilization",
@ -428,194 +468,122 @@
},
{
"BriefDescription": "Fraction of cycles spent in Kernel mode",
"MetricExpr": "cpu@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE",
"MetricExpr": "cpu@CPU_CLK_UNHALTED.CORE_P@k / CPU_CLK_UNHALTED.CORE",
"MetricGroup": "Summary",
"MetricName": "tma_info_system_kernel_utilization"
},
{
"BriefDescription": "Average Frequency Utilization relative nominal frequency",
"MetricExpr": "tma_info_core_clks / CPU_CLK_UNHALTED.REF_TSC",
"MetricExpr": "CPU_CLK_UNHALTED.CORE / CPU_CLK_UNHALTED.REF_TSC",
"MetricGroup": "Power",
"MetricName": "tma_info_system_turbo_utilization"
},
{
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
"MetricExpr": "TOPDOWN_FE_BOUND.ITLB / tma_info_core_slots",
"MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group",
"BriefDescription": "Percentage of all uops which are FPDiv uops",
"MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL",
"MetricName": "tma_info_uop_mix_fpdiv_uop_ratio"
},
{
"BriefDescription": "Percentage of all uops which are IDiv uops",
"MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL",
"MetricName": "tma_info_uop_mix_idiv_uop_ratio"
},
{
"BriefDescription": "Percentage of all uops which are microcode ops",
"MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL",
"MetricName": "tma_info_uop_mix_microcode_uop_ratio"
},
{
"BriefDescription": "Percentage of all uops which are x87 uops",
"MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL",
"MetricName": "tma_info_uop_mix_x87_uop_ratio"
},
{
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
"MetricExpr": "TOPDOWN_FE_BOUND.ITLB / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
"MetricName": "tma_itlb_misses",
"MetricThreshold": "tma_itlb_misses > 0.05",
"MetricThreshold": "tma_itlb_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block.",
"MetricExpr": "LD_HEAD.L1_BOUND_AT_RET / tma_info_core_clks",
"MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group",
"MetricName": "tma_l1_bound",
"MetricThreshold": "tma_l1_bound > 0.1",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.",
"MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks, 0) * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD",
"MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group",
"MetricName": "tma_l2_bound",
"MetricThreshold": "tma_l2_bound > 0.1",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
"MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks, 0) * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD",
"MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group",
"MetricName": "tma_l3_bound",
"MetricThreshold": "tma_l3_bound > 0.1",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to load buffer full",
"MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.LD_BUF / MEM_SCHEDULER_BLOCK.ALL",
"MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group",
"MetricName": "tma_ld_buffer",
"MetricThreshold": "tma_ld_buffer > 0.05",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
"MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / tma_info_core_slots",
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation",
"MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_machine_clears",
"MetricThreshold": "tma_machine_clears > 0.05",
"MetricThreshold": "tma_machine_clears > 0.05 & tma_bad_speculation > 0.15",
"MetricgroupNoGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
"MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / tma_info_core_slots",
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops",
"MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
"MetricName": "tma_mem_scheduler",
"MetricThreshold": "tma_mem_scheduler > 0.1",
"MetricThreshold": "tma_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads.",
"MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_info_core_clks + tma_store_bound)",
"MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"MetricThreshold": "tma_memory_bound > 0.2",
"MetricgroupNoGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory ordering.",
"MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.SLOW)",
"MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group",
"MetricName": "tma_memory_ordering",
"MetricThreshold": "tma_memory_ordering > 0.02",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)",
"MetricExpr": "UOPS_RETIRED.MS / tma_info_core_slots",
"MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group",
"MetricName": "tma_ms_uops",
"MetricThreshold": "tma_ms_uops > 0.05",
"MetricgroupNoGroup": "TopdownL2",
"PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
"MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / tma_info_core_slots",
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops",
"MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
"MetricName": "tma_non_mem_scheduler",
"MetricThreshold": "tma_non_mem_scheduler > 0.1",
"MetricThreshold": "tma_non_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear (slow nuke).",
"MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / tma_info_core_slots",
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)",
"MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group",
"MetricName": "tma_nuke",
"MetricThreshold": "tma_nuke > 0.05",
"MetricThreshold": "tma_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.",
"MetricExpr": "TOPDOWN_FE_BOUND.OTHER / tma_info_core_slots",
"MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.",
"MetricExpr": "TOPDOWN_FE_BOUND.OTHER / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
"MetricName": "tma_other_fb",
"MetricThreshold": "tma_other_fb > 0.05",
"MetricThreshold": "tma_other_fb > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a number of other load blocks.",
"MetricExpr": "LD_HEAD.OTHER_AT_RET / tma_info_core_clks",
"MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
"MetricName": "tma_other_l1",
"MetricThreshold": "tma_other_l1 > 0.05",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer.",
"MetricExpr": "max(0, tma_memory_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))",
"MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group",
"MetricName": "tma_other_load_store",
"MetricThreshold": "tma_other_load_store > 0.1",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of uops retired excluding ms and fp div uops.",
"MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV) / tma_info_core_slots",
"MetricGroup": "TopdownL3;tma_L3_group;tma_base_group",
"MetricName": "tma_other_ret",
"MetricThreshold": "tma_other_ret > 0.3",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to page faults.",
"MetricExpr": "tma_nuke * (MACHINE_CLEARS.PAGE_FAULT / MACHINE_CLEARS.SLOW)",
"MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group",
"MetricName": "tma_page_fault",
"MetricThreshold": "tma_page_fault > 0.02",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.",
"MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / tma_info_core_slots",
"MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.",
"MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
"MetricName": "tma_predecode",
"MetricThreshold": "tma_predecode > 0.05",
"MetricThreshold": "tma_predecode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
"MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / tma_info_core_slots",
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)",
"MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
"MetricName": "tma_register",
"MetricThreshold": "tma_register > 0.1",
"MetricThreshold": "tma_register > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
"MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / tma_info_core_slots",
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)",
"MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
"MetricName": "tma_reorder_buffer",
"MetricThreshold": "tma_reorder_buffer > 0.1",
"MetricThreshold": "tma_reorder_buffer > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls",
"MetricExpr": "tma_backend_bound",
"MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group",
"BriefDescription": "Counts the number of cycles the core is stalled due to a resource limitation",
"MetricExpr": "tma_backend_bound - tma_core_bound",
"MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_resource_bound",
"MetricThreshold": "tma_resource_bound > 0.2",
"MetricThreshold": "tma_resource_bound > 0.2 & tma_backend_bound > 0.1",
"MetricgroupNoGroup": "TopdownL2",
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count.",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that result in retirement slots.",
"BriefDescription": "Counts the number of issue slots that result in retirement slots",
"DefaultMetricgroupName": "TopdownL1",
"MetricExpr": "TOPDOWN_RETIRING.ALL / tma_info_core_slots",
"MetricExpr": "TOPDOWN_RETIRING.ALL / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "Default;TopdownL1;tma_L1_group",
"MetricName": "tma_retiring",
"MetricThreshold": "tma_retiring > 0.75",
@ -623,67 +591,11 @@
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to RSV full relative",
"MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.RSV / MEM_SCHEDULER_BLOCK.ALL",
"MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group",
"MetricName": "tma_rsv",
"MetricThreshold": "tma_rsv > 0.05",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
"MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / tma_info_core_slots",
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)",
"MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / (5 * CPU_CLK_UNHALTED.CORE)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
"MetricName": "tma_serialization",
"MetricThreshold": "tma_serialization > 0.1",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to SMC.",
"MetricExpr": "tma_nuke * (MACHINE_CLEARS.SMC / MACHINE_CLEARS.SLOW)",
"MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group",
"MetricName": "tma_smc",
"MetricThreshold": "tma_smc > 0.02",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to store buffer full",
"MetricExpr": "tma_store_bound",
"MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group",
"MetricName": "tma_st_buffer",
"MetricThreshold": "tma_st_buffer > 0.05",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a first level TLB miss.",
"MetricExpr": "LD_HEAD.DTLB_MISS_AT_RET / tma_info_core_clks",
"MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
"MetricName": "tma_stlb_hit",
"MetricThreshold": "tma_stlb_hit > 0.05",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a second level TLB miss requiring a page walk.",
"MetricExpr": "LD_HEAD.PGWALK_AT_RET / tma_info_core_clks",
"MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
"MetricName": "tma_stlb_miss",
"MetricThreshold": "tma_stlb_miss > 0.05",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.",
"MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)",
"MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group",
"MetricName": "tma_store_bound",
"MetricThreshold": "tma_store_bound > 0.1",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block.",
"MetricExpr": "LD_HEAD.ST_ADDR_AT_RET / tma_info_core_clks",
"MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
"MetricName": "tma_store_fwd_blk",
"MetricThreshold": "tma_store_fwd_blk > 0.05",
"MetricThreshold": "tma_serialization > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
"ScaleUnit": "100%"
}
]

50
tools/perf/pmu-events/arch/x86/alderlaken/cache.json
View File

@ -1,22 +1,25 @@
[
{
"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
{
"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x4f"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
@ -25,6 +28,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",
@ -33,6 +37,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
@ -41,6 +46,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
@ -49,6 +55,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD",
"SampleAfterValue": "200003",
@ -56,6 +63,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
"SampleAfterValue": "200003",
@ -63,6 +71,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
"SampleAfterValue": "200003",
@ -70,6 +79,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
"PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
@ -78,6 +88,7 @@
},
{
"BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
@ -87,6 +98,7 @@
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
@ -96,6 +108,7 @@
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
@ -105,6 +118,7 @@
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.ALL",
"SampleAfterValue": "20003",
@ -112,6 +126,7 @@
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",
"SampleAfterValue": "20003",
@ -119,6 +134,7 @@
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.RSV",
"SampleAfterValue": "20003",
@ -126,6 +142,7 @@
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",
"SampleAfterValue": "20003",
@ -133,6 +150,7 @@
},
{
"BriefDescription": "Counts the number of load uops retired.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
@ -143,6 +161,7 @@
},
{
"BriefDescription": "Counts the number of store uops retired.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
@ -153,6 +172,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
@ -165,6 +185,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
@ -177,6 +198,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
@ -189,6 +211,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
@ -201,6 +224,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
@ -213,6 +237,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
@ -225,6 +250,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
@ -237,6 +263,7 @@
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
@ -247,8 +274,19 @@
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
"BriefDescription": "Counts the number of load uops retired that performed one or more locks.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x21"
},
{
"BriefDescription": "Counts the number of retired split load uops.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
@ -258,6 +296,7 @@
},
{
"BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
@ -268,6 +307,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@ -277,6 +317,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@ -286,6 +327,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
@ -295,6 +337,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@ -304,6 +347,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
@ -313,6 +357,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@ -322,6 +367,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ICACHE",
"SampleAfterValue": "1000003",

2
tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
@ -9,6 +10,7 @@
},
{
"BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.FPDIV",
"PEBS": "1",

3
tools/perf/pmu-events/arch/x86/alderlaken/frontend.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
@ -9,6 +10,7 @@
},
{
"BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
@ -17,6 +19,7 @@
},
{
"BriefDescription": "Counts the number of instruction cache misses.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",

11
tools/perf/pmu-events/arch/x86/alderlaken/memory.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.ANY_AT_RET",
"SampleAfterValue": "1000003",
@ -8,6 +9,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.L1_BOUND_AT_RET",
"SampleAfterValue": "1000003",
@ -15,6 +17,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.L1_MISS_AT_RET",
"SampleAfterValue": "1000003",
@ -22,6 +25,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.OTHER_AT_RET",
"PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.",
@ -30,6 +34,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.PGWALK_AT_RET",
"SampleAfterValue": "1000003",
@ -37,6 +42,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.ST_ADDR_AT_RET",
"SampleAfterValue": "1000003",
@ -44,6 +50,7 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "20003",
@ -51,6 +58,7 @@
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@ -60,6 +68,7 @@
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
@ -69,6 +78,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@ -78,6 +88,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",

21
tools/perf/pmu-events/arch/x86/alderlaken/metricgroups.json
View File

@ -1,26 +1,23 @@
{
"Flops": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Ifetch": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Load_Store_Miss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Mem_Exec": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Power": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Summary": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"TopdownL1": "Metrics for top-down breakdown at level 1",
"TopdownL2": "Metrics for top-down breakdown at level 2",
"TopdownL3": "Metrics for top-down breakdown at level 3",
"TopdownL4": "Metrics for top-down breakdown at level 4",
"load_store_bound": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"tma_L1_group": "Metrics for top-down breakdown at level 1",
"tma_L2_group": "Metrics for top-down breakdown at level 2",
"tma_L3_group": "Metrics for top-down breakdown at level 3",
"tma_L4_group": "Metrics for top-down breakdown at level 4",
"tma_backend_bound_aux_group": "Metrics contributing to tma_backend_bound_aux category",
"tma_backend_bound_group": "Metrics contributing to tma_backend_bound category",
"tma_bad_speculation_group": "Metrics contributing to tma_bad_speculation category",
"tma_base_group": "Metrics contributing to tma_base category",
"tma_fetch_bandwidth_group": "Metrics contributing to tma_fetch_bandwidth category",
"tma_fetch_latency_group": "Metrics contributing to tma_fetch_latency category",
"tma_core_bound_group": "Metrics contributing to tma_core_bound category",
"tma_frontend_bound_group": "Metrics contributing to tma_frontend_bound category",
"tma_l1_bound_group": "Metrics contributing to tma_l1_bound category",
"tma_ifetch_bandwidth_group": "Metrics contributing to tma_ifetch_bandwidth category",
"tma_ifetch_latency_group": "Metrics contributing to tma_ifetch_latency category",
"tma_machine_clears_group": "Metrics contributing to tma_machine_clears category",
"tma_mem_scheduler_group": "Metrics contributing to tma_mem_scheduler category",
"tma_memory_bound_group": "Metrics contributing to tma_memory_bound category",
"tma_nuke_group": "Metrics contributing to tma_nuke category",
"tma_resource_bound_group": "Metrics contributing to tma_resource_bound category",
"tma_retiring_group": "Metrics contributing to tma_retiring category"
"tma_resource_bound_group": "Metrics contributing to tma_resource_bound category"
}

13
tools/perf/pmu-events/arch/x86/alderlaken/other.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0xe4",
"EventName": "LBR_INSERTS.ANY",
@ -10,6 +11,7 @@
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.COREWB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@ -19,6 +21,7 @@
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@ -28,6 +31,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@ -37,11 +41,20 @@
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state)",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x75",
"EventName": "SERIALIZATION.C01_MS_SCB",
"SampleAfterValue": "200003",
"UMask": "0x4"
}
]

80
tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@ -9,6 +10,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.CALL",
@ -18,6 +20,7 @@
},
{
"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND",
"PEBS": "1",
@ -26,6 +29,7 @@
},
{
"BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"PEBS": "1",
@ -34,6 +38,7 @@
},
{
"BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
@ -42,6 +47,7 @@
},
{
"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT",
"PEBS": "1",
@ -50,6 +56,7 @@
},
{
"BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT_CALL",
"PEBS": "1",
@ -58,6 +65,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.IND_CALL",
@ -67,6 +75,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.JCC",
@ -76,6 +85,7 @@
},
{
"BriefDescription": "Counts the number of near CALL branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@ -84,6 +94,7 @@
},
{
"BriefDescription": "Counts the number of near RET branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@ -92,6 +103,7 @@
},
{
"BriefDescription": "Counts the number of near taken branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@ -100,6 +112,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
@ -109,6 +122,7 @@
},
{
"BriefDescription": "Counts the number of near relative CALL branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.REL_CALL",
"PEBS": "1",
@ -117,6 +131,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURN",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.RETURN",
@ -126,6 +141,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKEN",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
@ -135,6 +151,7 @@
},
{
"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@ -143,6 +160,7 @@
},
{
"BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND",
"PEBS": "1",
@ -151,6 +169,7 @@
},
{
"BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_TAKEN",
"PEBS": "1",
@ -159,6 +178,7 @@
},
{
"BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT",
"PEBS": "1",
@ -167,6 +187,7 @@
},
{
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"PEBS": "1",
@ -175,6 +196,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.IND_CALL",
@ -184,6 +206,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.JCC",
@ -193,6 +216,7 @@
},
{
"BriefDescription": "Counts the number of mispredicted near taken branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@ -201,6 +225,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
@ -210,6 +235,7 @@
},
{
"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PEBS": "1",
@ -218,6 +244,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKEN",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
@ -227,6 +254,7 @@
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
"SampleAfterValue": "2000003",
@ -234,6 +262,7 @@
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
@ -241,6 +270,7 @@
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
"Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
"SampleAfterValue": "2000003",
@ -248,6 +278,7 @@
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
@ -256,6 +287,7 @@
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
"SampleAfterValue": "2000003",
@ -263,6 +295,7 @@
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
@ -270,6 +303,7 @@
},
{
"BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
"Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.",
@ -278,6 +312,7 @@
},
{
"BriefDescription": "Counts the total number of instructions retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
@ -286,6 +321,7 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS",
"Counter": "0,1,2,3,4,5",
"Deprecated": "1",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.4K_ALIAS",
@ -295,6 +331,7 @@
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ADDRESS_ALIAS",
"PEBS": "1",
@ -303,6 +340,7 @@
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"PEBS": "1",
@ -311,6 +349,7 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.DISAMBIGUATION",
"SampleAfterValue": "20003",
@ -318,6 +357,7 @@
},
{
"BriefDescription": "Counts the number of machines clears due to memory renaming.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MRN_NUKE",
"SampleAfterValue": "1000003",
@ -325,6 +365,7 @@
},
{
"BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.PAGE_FAULT",
"SampleAfterValue": "20003",
@ -332,6 +373,7 @@
},
{
"BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SLOW",
"SampleAfterValue": "20003",
@ -339,6 +381,7 @@
},
{
"BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "20003",
@ -346,6 +389,7 @@
},
{
"BriefDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to LBR_INSERTS.ANY]",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xe4",
"EventName": "MISC_RETIRED.LBR_INSERTS",
"PEBS": "1",
@ -355,6 +399,7 @@
},
{
"BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x75",
"EventName": "SERIALIZATION.NON_C01_MS_SCB",
"PublicDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE.",
@ -363,6 +408,7 @@
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.ALL",
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
@ -370,6 +416,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
"SampleAfterValue": "1000003",
@ -377,6 +424,7 @@
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
"SampleAfterValue": "1000003",
@ -384,6 +432,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
"SampleAfterValue": "1000003",
@ -391,6 +440,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.NUKE",
"SampleAfterValue": "1000003",
@ -398,12 +448,14 @@
},
{
"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.ALL",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
"SampleAfterValue": "1000003",
@ -411,6 +463,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
"SampleAfterValue": "1000003",
@ -418,6 +471,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
"SampleAfterValue": "1000003",
@ -425,6 +479,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.REGISTER",
"SampleAfterValue": "1000003",
@ -432,6 +487,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
"SampleAfterValue": "1000003",
@ -439,6 +495,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
"SampleAfterValue": "1000003",
@ -446,12 +503,14 @@
},
{
"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ALL",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
@ -460,6 +519,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
@ -468,6 +528,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.CISC",
"SampleAfterValue": "1000003",
@ -475,6 +536,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.DECODE",
"SampleAfterValue": "1000003",
@ -482,6 +544,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH",
"SampleAfterValue": "1000003",
@ -489,6 +552,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY",
"SampleAfterValue": "1000003",
@ -496,6 +560,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ITLB",
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
@ -504,6 +569,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.OTHER",
"SampleAfterValue": "1000003",
@ -511,6 +577,7 @@
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.PREDECODE",
"SampleAfterValue": "1000003",
@ -518,13 +585,23 @@
},
{
"BriefDescription": "Counts the total number of consumed retirement slots.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "TOPDOWN_RETIRING.ALL",
"PEBS": "1",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of uops issued by the front end every cycle.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the total number of uops retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
@ -532,6 +609,7 @@
},
{
"BriefDescription": "Counts the number of integer divide uops retired.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.IDIV",
"PEBS": "1",
@ -540,6 +618,7 @@
},
{
"BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MS",
"PEBS": "1",
@ -549,6 +628,7 @@
},
{
"BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.X87",
"PEBS": "1",

19
tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Number of requests allocated in Coherency Tracker.",
"Counter": "0,1",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
@ -9,56 +10,69 @@
},
{
"BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
"Counter": "0",
"EventCode": "0x85",
"EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
"Counter": "0",
"EventCode": "0x85",
"EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD",
"Counter": "0,1",
"Deprecated": "1",
"EventCode": "0x81",
"EventName": "UNC_ARB_DAT_REQUESTS.RD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
"Counter": "0",
"Deprecated": "1",
"EventCode": "0x85",
"EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]",
"Counter": "0",
"EventCode": "0x80",
"EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
"Counter": "0",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
@ -67,14 +81,17 @@
},
{
"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]",
"Counter": "0",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.RD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
@ -83,8 +100,10 @@
},
{
"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.RD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"

25
tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).",
"Counter": "0",
"EventCode": "0xff",
"EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
"PerPkg": "1",
@ -10,6 +11,7 @@
},
{
"BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
"Counter": "1",
"EventCode": "0xff",
"EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
"PerPkg": "1",
@ -18,6 +20,7 @@
},
{
"BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).",
"Counter": "3",
"EventCode": "0xff",
"EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
"PerPkg": "1",
@ -27,6 +30,7 @@
},
{
"BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
"Counter": "4",
"EventCode": "0xff",
"EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
"PerPkg": "1",
@ -35,6 +39,7 @@
},
{
"BriefDescription": "ACT command for a read request sent to DRAM",
"Counter": "0,1,2,3,4",
"EventCode": "0x24",
"EventName": "UNC_M_ACT_COUNT_RD",
"PerPkg": "1",
@ -42,6 +47,7 @@
},
{
"BriefDescription": "ACT command sent to DRAM",
"Counter": "0,1,2,3,4",
"EventCode": "0x26",
"EventName": "UNC_M_ACT_COUNT_TOTAL",
"PerPkg": "1",
@ -49,6 +55,7 @@
},
{
"BriefDescription": "ACT command for a write request sent to DRAM",
"Counter": "0,1,2,3,4",
"EventCode": "0x25",
"EventName": "UNC_M_ACT_COUNT_WR",
"PerPkg": "1",
@ -56,6 +63,7 @@
},
{
"BriefDescription": "Read CAS command sent to DRAM",
"Counter": "0,1,2,3,4",
"EventCode": "0x22",
"EventName": "UNC_M_CAS_COUNT_RD",
"PerPkg": "1",
@ -63,6 +71,7 @@
},
{
"BriefDescription": "Write CAS command sent to DRAM",
"Counter": "0,1,2,3,4",
"EventCode": "0x23",
"EventName": "UNC_M_CAS_COUNT_WR",
"PerPkg": "1",
@ -70,6 +79,7 @@
},
{
"BriefDescription": "Number of clocks",
"Counter": "0,1,2,3,4",
"EventCode": "0x01",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
@ -77,6 +87,7 @@
},
{
"BriefDescription": "incoming read request page status is Page Empty",
"Counter": "0,1,2,3,4",
"EventCode": "0x1D",
"EventName": "UNC_M_DRAM_PAGE_EMPTY_RD",
"PerPkg": "1",
@ -84,6 +95,7 @@
},
{
"BriefDescription": "incoming write request page status is Page Empty",
"Counter": "0,1,2,3,4",
"EventCode": "0x20",
"EventName": "UNC_M_DRAM_PAGE_EMPTY_WR",
"PerPkg": "1",
@ -91,6 +103,7 @@
},
{
"BriefDescription": "incoming read request page status is Page Hit",
"Counter": "0,1,2,3,4",
"EventCode": "0x1C",
"EventName": "UNC_M_DRAM_PAGE_HIT_RD",
"PerPkg": "1",
@ -98,6 +111,7 @@
},
{
"BriefDescription": "incoming write request page status is Page Hit",
"Counter": "0,1,2,3,4",
"EventCode": "0x1F",
"EventName": "UNC_M_DRAM_PAGE_HIT_WR",
"PerPkg": "1",
@ -105,6 +119,7 @@
},
{
"BriefDescription": "incoming read request page status is Page Miss",
"Counter": "0,1,2,3,4",
"EventCode": "0x1E",
"EventName": "UNC_M_DRAM_PAGE_MISS_RD",
"PerPkg": "1",
@ -112,6 +127,7 @@
},
{
"BriefDescription": "incoming write request page status is Page Miss",
"Counter": "0,1,2,3,4",
"EventCode": "0x21",
"EventName": "UNC_M_DRAM_PAGE_MISS_WR",
"PerPkg": "1",
@ -119,6 +135,7 @@
},
{
"BriefDescription": "Any Rank at Hot state",
"Counter": "0,1,2,3,4",
"EventCode": "0x19",
"EventName": "UNC_M_DRAM_THERMAL_HOT",
"PerPkg": "1",
@ -126,6 +143,7 @@
},
{
"BriefDescription": "Any Rank at Warm state",
"Counter": "0,1,2,3,4",
"EventCode": "0x1A",
"EventName": "UNC_M_DRAM_THERMAL_WARM",
"PerPkg": "1",
@ -133,6 +151,7 @@
},
{
"BriefDescription": "Incoming read prefetch request from IA.",
"Counter": "0,1,2,3,4",
"EventCode": "0x0A",
"EventName": "UNC_M_PREFETCH_RD",
"PerPkg": "1",
@ -140,6 +159,7 @@
},
{
"BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration",
"Counter": "0,1,2,3,4",
"EventCode": "0x28",
"EventName": "UNC_M_PRE_COUNT_IDLE",
"PerPkg": "1",
@ -147,6 +167,7 @@
},
{
"BriefDescription": "PRE command sent to DRAM for a read/write request",
"Counter": "0,1,2,3,4",
"EventCode": "0x27",
"EventName": "UNC_M_PRE_COUNT_PAGE_MISS",
"PerPkg": "1",
@ -154,6 +175,7 @@
},
{
"BriefDescription": "Incoming VC0 read request",
"Counter": "0,1,2,3,4",
"EventCode": "0x02",
"EventName": "UNC_M_VC0_REQUESTS_RD",
"PerPkg": "1",
@ -161,6 +183,7 @@
},
{
"BriefDescription": "Incoming VC0 write request",
"Counter": "0,1,2,3,4",
"EventCode": "0x03",
"EventName": "UNC_M_VC0_REQUESTS_WR",
"PerPkg": "1",
@ -168,6 +191,7 @@
},
{
"BriefDescription": "Incoming VC1 read request",
"Counter": "0,1,2,3,4",
"EventCode": "0x04",
"EventName": "UNC_M_VC1_REQUESTS_RD",
"PerPkg": "1",
@ -175,6 +199,7 @@
},
{
"BriefDescription": "Incoming VC1 write request",
"Counter": "0,1,2,3,4",
"EventCode": "0x05",
"EventName": "UNC_M_VC1_REQUESTS_WR",
"PerPkg": "1",

1
tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Counter": "FIXED",
"EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1",

6
tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
@ -9,6 +10,7 @@
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
@ -17,6 +19,7 @@
},
{
"BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSED_WALK",
"SampleAfterValue": "1000003",
@ -24,6 +27,7 @@
},
{
"BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.PDE_CACHE_MISS",
"SampleAfterValue": "2000003",
@ -31,6 +35,7 @@
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
@ -39,6 +44,7 @@
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.DTLB_MISS_AT_RET",
"SampleAfterValue": "1000003",

93
tools/perf/pmu-events/arch/x86/bonnell/cache.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "L1 Data Cacheable reads and writes",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.ALL_CACHE_REF",
"SampleAfterValue": "2000000",
@ -8,6 +9,7 @@
},
{
"BriefDescription": "L1 Data reads and writes",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.ALL_REF",
"SampleAfterValue": "2000000",
@ -15,6 +17,7 @@
},
{
"BriefDescription": "Modified cache lines evicted from the L1 data cache",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.EVICT",
"SampleAfterValue": "200000",
@ -22,6 +25,7 @@
},
{
"BriefDescription": "L1 Cacheable Data Reads",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.LD",
"SampleAfterValue": "2000000",
@ -29,6 +33,7 @@
},
{
"BriefDescription": "L1 Data line replacements",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.REPL",
"SampleAfterValue": "200000",
@ -36,6 +41,7 @@
},
{
"BriefDescription": "Modified cache lines allocated in the L1 data cache",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.REPLM",
"SampleAfterValue": "200000",
@ -43,6 +49,7 @@
},
{
"BriefDescription": "L1 Cacheable Data Writes",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.ST",
"SampleAfterValue": "2000000",
@ -50,6 +57,7 @@
},
{
"BriefDescription": "Cycles L2 address bus is in use.",
"Counter": "0,1",
"EventCode": "0x21",
"EventName": "L2_ADS.SELF",
"SampleAfterValue": "200000",
@ -57,6 +65,7 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.E_STATE",
"SampleAfterValue": "200000",
@ -64,6 +73,7 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.I_STATE",
"SampleAfterValue": "200000",
@ -71,6 +81,7 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.MESI",
"SampleAfterValue": "200000",
@ -78,6 +89,7 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.M_STATE",
"SampleAfterValue": "200000",
@ -85,6 +97,7 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.S_STATE",
"SampleAfterValue": "200000",
@ -92,6 +105,7 @@
},
{
"BriefDescription": "Cycles the L2 cache data bus is busy.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "L2_DBUS_BUSY.SELF",
"SampleAfterValue": "200000",
@ -99,6 +113,7 @@
},
{
"BriefDescription": "Cycles the L2 transfers data to the core.",
"Counter": "0,1",
"EventCode": "0x23",
"EventName": "L2_DBUS_BUSY_RD.SELF",
"SampleAfterValue": "200000",
@ -106,6 +121,7 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.E_STATE",
"SampleAfterValue": "200000",
@ -113,6 +129,7 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.I_STATE",
"SampleAfterValue": "200000",
@ -120,6 +137,7 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.MESI",
"SampleAfterValue": "200000",
@ -127,6 +145,7 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.M_STATE",
"SampleAfterValue": "200000",
@ -134,6 +153,7 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.S_STATE",
"SampleAfterValue": "200000",
@ -141,6 +161,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
@ -148,6 +169,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
@ -155,6 +177,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.MESI",
"SampleAfterValue": "200000",
@ -162,6 +185,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
@ -169,6 +193,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
@ -176,6 +201,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@ -183,6 +209,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@ -190,6 +217,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
@ -197,6 +225,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@ -204,6 +233,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@ -211,6 +241,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@ -218,6 +249,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@ -225,6 +257,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
@ -232,6 +265,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@ -239,6 +273,7 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@ -246,6 +281,7 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.E_STATE",
"SampleAfterValue": "200000",
@ -253,6 +289,7 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.I_STATE",
"SampleAfterValue": "200000",
@ -260,6 +297,7 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.MESI",
"SampleAfterValue": "200000",
@ -267,6 +305,7 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.M_STATE",
"SampleAfterValue": "200000",
@ -274,6 +313,7 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.S_STATE",
"SampleAfterValue": "200000",
@ -281,6 +321,7 @@
},
{
"BriefDescription": "L2 cache misses.",
"Counter": "0,1",
"EventCode": "0x24",
"EventName": "L2_LINES_IN.SELF.ANY",
"SampleAfterValue": "200000",
@ -288,6 +329,7 @@
},
{
"BriefDescription": "L2 cache misses.",
"Counter": "0,1",
"EventCode": "0x24",
"EventName": "L2_LINES_IN.SELF.DEMAND",
"SampleAfterValue": "200000",
@ -295,6 +337,7 @@
},
{
"BriefDescription": "L2 cache misses.",
"Counter": "0,1",
"EventCode": "0x24",
"EventName": "L2_LINES_IN.SELF.PREFETCH",
"SampleAfterValue": "200000",
@ -302,6 +345,7 @@
},
{
"BriefDescription": "L2 cache lines evicted.",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.SELF.ANY",
"SampleAfterValue": "200000",
@ -309,6 +353,7 @@
},
{
"BriefDescription": "L2 cache lines evicted.",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.SELF.DEMAND",
"SampleAfterValue": "200000",
@ -316,6 +361,7 @@
},
{
"BriefDescription": "L2 cache lines evicted.",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.SELF.PREFETCH",
"SampleAfterValue": "200000",
@ -323,6 +369,7 @@
},
{
"BriefDescription": "L2 locked accesses",
"Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.E_STATE",
"SampleAfterValue": "200000",
@ -330,6 +377,7 @@
},
{
"BriefDescription": "L2 locked accesses",
"Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.I_STATE",
"SampleAfterValue": "200000",
@ -337,6 +385,7 @@
},
{
"BriefDescription": "L2 locked accesses",
"Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.MESI",
"SampleAfterValue": "200000",
@ -344,6 +393,7 @@
},
{
"BriefDescription": "L2 locked accesses",
"Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.M_STATE",
"SampleAfterValue": "200000",
@ -351,6 +401,7 @@
},
{
"BriefDescription": "L2 locked accesses",
"Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.S_STATE",
"SampleAfterValue": "200000",
@ -358,6 +409,7 @@
},
{
"BriefDescription": "L2 cache line modifications.",
"Counter": "0,1",
"EventCode": "0x25",
"EventName": "L2_M_LINES_IN.SELF",
"SampleAfterValue": "200000",
@ -365,6 +417,7 @@
},
{
"BriefDescription": "Modified lines evicted from the L2 cache",
"Counter": "0,1",
"EventCode": "0x27",
"EventName": "L2_M_LINES_OUT.SELF.ANY",
"SampleAfterValue": "200000",
@ -372,6 +425,7 @@
},
{
"BriefDescription": "Modified lines evicted from the L2 cache",
"Counter": "0,1",
"EventCode": "0x27",
"EventName": "L2_M_LINES_OUT.SELF.DEMAND",
"SampleAfterValue": "200000",
@ -379,6 +433,7 @@
},
{
"BriefDescription": "Modified lines evicted from the L2 cache",
"Counter": "0,1",
"EventCode": "0x27",
"EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
"SampleAfterValue": "200000",
@ -386,6 +441,7 @@
},
{
"BriefDescription": "Cycles no L2 cache requests are pending",
"Counter": "0,1",
"EventCode": "0x32",
"EventName": "L2_NO_REQ.SELF",
"SampleAfterValue": "200000",
@ -393,6 +449,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
@ -400,6 +457,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
@ -407,6 +465,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
"SampleAfterValue": "200000",
@ -414,6 +473,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
@ -421,6 +481,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
@ -428,6 +489,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@ -435,6 +497,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@ -442,6 +505,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
@ -449,6 +513,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@ -456,6 +521,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@ -463,6 +529,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@ -470,6 +537,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@ -477,6 +545,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
@ -484,6 +553,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@ -491,6 +561,7 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@ -498,6 +569,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
@ -505,6 +577,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
@ -512,6 +585,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.MESI",
"SampleAfterValue": "200000",
@ -519,6 +593,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
@ -526,6 +601,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
@ -533,6 +609,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@ -540,6 +617,7 @@
},
{
"BriefDescription": "L2 cache demand requests from this core that missed the L2",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@ -547,6 +625,7 @@
},
{
"BriefDescription": "L2 cache demand requests from this core",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
@ -554,6 +633,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@ -561,6 +641,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@ -568,6 +649,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@ -575,6 +657,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@ -582,6 +665,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
@ -589,6 +673,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@ -596,6 +681,7 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@ -603,6 +689,7 @@
},
{
"BriefDescription": "L2 store requests",
"Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.E_STATE",
"SampleAfterValue": "200000",
@ -610,6 +697,7 @@
},
{
"BriefDescription": "L2 store requests",
"Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.I_STATE",
"SampleAfterValue": "200000",
@ -617,6 +705,7 @@
},
{
"BriefDescription": "L2 store requests",
"Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.MESI",
"SampleAfterValue": "200000",
@ -624,6 +713,7 @@
},
{
"BriefDescription": "L2 store requests",
"Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.M_STATE",
"SampleAfterValue": "200000",
@ -631,6 +721,7 @@
},
{
"BriefDescription": "L2 store requests",
"Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.S_STATE",
"SampleAfterValue": "200000",
@ -638,6 +729,7 @@
},
{
"BriefDescription": "Retired loads that hit the L2 cache (precise event).",
"Counter": "0,1",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"SampleAfterValue": "200000",
@ -645,6 +737,7 @@
},
{
"BriefDescription": "Retired loads that miss the L2 cache",
"Counter": "0,1",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"SampleAfterValue": "10000",

7
tools/perf/pmu-events/arch/x86/bonnell/counter.json Normal file
View File

@ -0,0 +1,7 @@
[
{
"Unit": "core",
"CountersNumFixed": "4",
"CountersNumGeneric": "2"
}
]

32
tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Floating point assists for retired operations.",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "FP_ASSIST.AR",
"SampleAfterValue": "10000",
@ -8,6 +9,7 @@
},
{
"BriefDescription": "Floating point assists.",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "FP_ASSIST.S",
"SampleAfterValue": "10000",
@ -15,12 +17,14 @@
},
{
"BriefDescription": "SIMD assists invoked.",
"Counter": "0,1",
"EventCode": "0xCD",
"EventName": "SIMD_ASSIST",
"SampleAfterValue": "100000"
},
{
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
"Counter": "0,1",
"EventCode": "0xCA",
"EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000",
@ -28,6 +32,7 @@
},
{
"BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
"Counter": "0,1",
"EventCode": "0xCA",
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000",
@ -35,6 +40,7 @@
},
{
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
"Counter": "0,1",
"EventCode": "0xCA",
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000",
@ -42,12 +48,14 @@
},
{
"BriefDescription": "SIMD Instructions retired.",
"Counter": "0,1",
"EventCode": "0xCE",
"EventName": "SIMD_INSTR_RETIRED",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
"Counter": "0,1",
"EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000",
@ -55,6 +63,7 @@
},
{
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
"Counter": "0,1",
"EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000",
@ -62,6 +71,7 @@
},
{
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
"Counter": "0,1",
"EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000",
@ -69,6 +79,7 @@
},
{
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
"Counter": "0,1",
"EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.VECTOR",
"SampleAfterValue": "2000000",
@ -76,12 +87,14 @@
},
{
"BriefDescription": "Saturated arithmetic instructions retired.",
"Counter": "0,1",
"EventCode": "0xCF",
"EventName": "SIMD_SAT_INSTR_RETIRED",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "SIMD saturated arithmetic micro-ops retired.",
"Counter": "0,1",
"EventCode": "0xB1",
"EventName": "SIMD_SAT_UOP_EXEC.AR",
"SampleAfterValue": "2000000",
@ -89,12 +102,14 @@
},
{
"BriefDescription": "SIMD saturated arithmetic micro-ops executed.",
"Counter": "0,1",
"EventCode": "0xB1",
"EventName": "SIMD_SAT_UOP_EXEC.S",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "SIMD micro-ops retired (excluding stores).",
"Counter": "0,1",
"EventCode": "0xB0",
"EventName": "SIMD_UOPS_EXEC.AR",
"PEBS": "2",
@ -103,12 +118,14 @@
},
{
"BriefDescription": "SIMD micro-ops executed (excluding stores).",
"Counter": "0,1",
"EventCode": "0xB0",
"EventName": "SIMD_UOPS_EXEC.S",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "SIMD packed arithmetic micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
"SampleAfterValue": "2000000",
@ -116,6 +133,7 @@
},
{
"BriefDescription": "SIMD packed arithmetic micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
"SampleAfterValue": "2000000",
@ -123,6 +141,7 @@
},
{
"BriefDescription": "SIMD packed logical micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
"SampleAfterValue": "2000000",
@ -130,6 +149,7 @@
},
{
"BriefDescription": "SIMD packed logical micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
"SampleAfterValue": "2000000",
@ -137,6 +157,7 @@
},
{
"BriefDescription": "SIMD packed multiply micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
"SampleAfterValue": "2000000",
@ -144,6 +165,7 @@
},
{
"BriefDescription": "SIMD packed multiply micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
"SampleAfterValue": "2000000",
@ -151,6 +173,7 @@
},
{
"BriefDescription": "SIMD packed micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
"SampleAfterValue": "2000000",
@ -158,6 +181,7 @@
},
{
"BriefDescription": "SIMD packed micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
"SampleAfterValue": "2000000",
@ -165,6 +189,7 @@
},
{
"BriefDescription": "SIMD packed shift micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
"SampleAfterValue": "2000000",
@ -172,6 +197,7 @@
},
{
"BriefDescription": "SIMD packed shift micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
"SampleAfterValue": "2000000",
@ -179,6 +205,7 @@
},
{
"BriefDescription": "SIMD unpacked micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
"SampleAfterValue": "2000000",
@ -186,6 +213,7 @@
},
{
"BriefDescription": "SIMD unpacked micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
"SampleAfterValue": "2000000",
@ -193,6 +221,7 @@
},
{
"BriefDescription": "Floating point computational micro-ops retired.",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.ANY.AR",
"PEBS": "2",
@ -201,6 +230,7 @@
},
{
"BriefDescription": "Floating point computational micro-ops executed.",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.ANY.S",
"SampleAfterValue": "2000000",
@ -208,6 +238,7 @@
},
{
"BriefDescription": "FXCH uops retired.",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.FXCH.AR",
"PEBS": "2",
@ -216,6 +247,7 @@
},
{
"BriefDescription": "FXCH uops executed.",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.FXCH.S",
"SampleAfterValue": "2000000",

11
tools/perf/pmu-events/arch/x86/bonnell/frontend.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "BACLEARS asserted.",
"Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "2000000",
@ -8,6 +9,7 @@
},
{
"BriefDescription": "Cycles during which instruction fetches are stalled.",
"Counter": "0,1",
"EventCode": "0x86",
"EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
"SampleAfterValue": "2000000",
@ -15,6 +17,7 @@
},
{
"BriefDescription": "Decode stall due to IQ full",
"Counter": "0,1",
"EventCode": "0x87",
"EventName": "DECODE_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
@ -22,6 +25,7 @@
},
{
"BriefDescription": "Decode stall due to PFB empty",
"Counter": "0,1",
"EventCode": "0x87",
"EventName": "DECODE_STALL.PFB_EMPTY",
"SampleAfterValue": "2000000",
@ -29,6 +33,7 @@
},
{
"BriefDescription": "Instruction fetches.",
"Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "200000",
@ -36,6 +41,7 @@
},
{
"BriefDescription": "Icache hit",
"Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "200000",
@ -43,6 +49,7 @@
},
{
"BriefDescription": "Icache miss",
"Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200000",
@ -50,6 +57,7 @@
},
{
"BriefDescription": "All Instructions decoded",
"Counter": "0,1",
"EventCode": "0xAA",
"EventName": "MACRO_INSTS.ALL_DECODED",
"SampleAfterValue": "2000000",
@ -57,6 +65,7 @@
},
{
"BriefDescription": "CISC macro instructions decoded",
"Counter": "0,1",
"EventCode": "0xAA",
"EventName": "MACRO_INSTS.CISC_DECODED",
"SampleAfterValue": "2000000",
@ -64,6 +73,7 @@
},
{
"BriefDescription": "Non-CISC macro instructions decoded",
"Counter": "0,1",
"EventCode": "0xAA",
"EventName": "MACRO_INSTS.NON_CISC_DECODED",
"SampleAfterValue": "2000000",
@ -71,6 +81,7 @@
},
{
"BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
"Counter": "0,1",
"CounterMask": "1",
"EventCode": "0xA9",
"EventName": "UOPS.MS_CYCLES",

19
tools/perf/pmu-events/arch/x86/bonnell/memory.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Nonzero segbase 1 bubble",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.BUBBLE",
"SampleAfterValue": "200000",
@ -8,6 +9,7 @@
},
{
"BriefDescription": "Nonzero segbase load 1 bubble",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
"SampleAfterValue": "200000",
@ -15,6 +17,7 @@
},
{
"BriefDescription": "Load splits",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT",
"SampleAfterValue": "200000",
@ -22,6 +25,7 @@
},
{
"BriefDescription": "Load splits (At Retirement)",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
"SampleAfterValue": "200000",
@ -29,6 +33,7 @@
},
{
"BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
"SampleAfterValue": "200000",
@ -36,6 +41,7 @@
},
{
"BriefDescription": "ld-op-st splits",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
"SampleAfterValue": "200000",
@ -43,6 +49,7 @@
},
{
"BriefDescription": "Memory references that cross an 8-byte boundary.",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.SPLIT",
"SampleAfterValue": "200000",
@ -50,6 +57,7 @@
},
{
"BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.SPLIT.AR",
"SampleAfterValue": "200000",
@ -57,6 +65,7 @@
},
{
"BriefDescription": "Nonzero segbase store 1 bubble",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
"SampleAfterValue": "200000",
@ -64,6 +73,7 @@
},
{
"BriefDescription": "Store splits",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT",
"SampleAfterValue": "200000",
@ -71,6 +81,7 @@
},
{
"BriefDescription": "Store splits (Ar Retirement)",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
"SampleAfterValue": "200000",
@ -78,6 +89,7 @@
},
{
"BriefDescription": "L1 hardware prefetch request",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.HW_PREFETCH",
"SampleAfterValue": "2000000",
@ -85,6 +97,7 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHNTA",
"SampleAfterValue": "200000",
@ -92,6 +105,7 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT0",
"SampleAfterValue": "200000",
@ -99,6 +113,7 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT1",
"SampleAfterValue": "200000",
@ -106,6 +121,7 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT2",
"SampleAfterValue": "200000",
@ -113,6 +129,7 @@
},
{
"BriefDescription": "Any Software prefetch",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH",
"SampleAfterValue": "200000",
@ -120,6 +137,7 @@
},
{
"BriefDescription": "Any Software prefetch",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
"SampleAfterValue": "200000",
@ -127,6 +145,7 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.SW_L2",
"SampleAfterValue": "200000",

56
tools/perf/pmu-events/arch/x86/bonnell/other.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Bus queue is empty.",
"Counter": "0,1",
"EventCode": "0x7D",
"EventName": "BUSQ_EMPTY.SELF",
"SampleAfterValue": "200000",
@ -8,6 +9,7 @@
},
{
"BriefDescription": "Number of Bus Not Ready signals asserted.",
"Counter": "0,1",
"EventCode": "0x61",
"EventName": "BUS_BNR_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -15,12 +17,14 @@
},
{
"BriefDescription": "Number of Bus Not Ready signals asserted.",
"Counter": "0,1",
"EventCode": "0x61",
"EventName": "BUS_BNR_DRV.THIS_AGENT",
"SampleAfterValue": "200000"
},
{
"BriefDescription": "Bus cycles while processor receives data.",
"Counter": "0,1",
"EventCode": "0x64",
"EventName": "BUS_DATA_RCV.SELF",
"SampleAfterValue": "200000",
@ -28,6 +32,7 @@
},
{
"BriefDescription": "Bus cycles when data is sent on the bus.",
"Counter": "0,1",
"EventCode": "0x62",
"EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -35,12 +40,14 @@
},
{
"BriefDescription": "Bus cycles when data is sent on the bus.",
"Counter": "0,1",
"EventCode": "0x62",
"EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
"SampleAfterValue": "200000"
},
{
"BriefDescription": "HITM signal asserted.",
"Counter": "0,1",
"EventCode": "0x7B",
"EventName": "BUS_HITM_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -48,12 +55,14 @@
},
{
"BriefDescription": "HITM signal asserted.",
"Counter": "0,1",
"EventCode": "0x7B",
"EventName": "BUS_HITM_DRV.THIS_AGENT",
"SampleAfterValue": "200000"
},
{
"BriefDescription": "HIT signal asserted.",
"Counter": "0,1",
"EventCode": "0x7A",
"EventName": "BUS_HIT_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -61,12 +70,14 @@
},
{
"BriefDescription": "HIT signal asserted.",
"Counter": "0,1",
"EventCode": "0x7A",
"EventName": "BUS_HIT_DRV.THIS_AGENT",
"SampleAfterValue": "200000"
},
{
"BriefDescription": "IO requests waiting in the bus queue.",
"Counter": "0,1",
"EventCode": "0x7F",
"EventName": "BUS_IO_WAIT.SELF",
"SampleAfterValue": "200000",
@ -74,6 +85,7 @@
},
{
"BriefDescription": "Bus cycles when a LOCK signal is asserted.",
"Counter": "0,1",
"EventCode": "0x63",
"EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -81,6 +93,7 @@
},
{
"BriefDescription": "Bus cycles when a LOCK signal is asserted.",
"Counter": "0,1",
"EventCode": "0x63",
"EventName": "BUS_LOCK_CLOCKS.SELF",
"SampleAfterValue": "200000",
@ -88,6 +101,7 @@
},
{
"BriefDescription": "Outstanding cacheable data read bus requests duration.",
"Counter": "0,1",
"EventCode": "0x60",
"EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -95,6 +109,7 @@
},
{
"BriefDescription": "Outstanding cacheable data read bus requests duration.",
"Counter": "0,1",
"EventCode": "0x60",
"EventName": "BUS_REQUEST_OUTSTANDING.SELF",
"SampleAfterValue": "200000",
@ -102,6 +117,7 @@
},
{
"BriefDescription": "All bus transactions.",
"Counter": "0,1",
"EventCode": "0x70",
"EventName": "BUS_TRANS_ANY.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -109,6 +125,7 @@
},
{
"BriefDescription": "All bus transactions.",
"Counter": "0,1",
"EventCode": "0x70",
"EventName": "BUS_TRANS_ANY.SELF",
"SampleAfterValue": "200000",
@ -116,6 +133,7 @@
},
{
"BriefDescription": "Burst read bus transactions.",
"Counter": "0,1",
"EventCode": "0x65",
"EventName": "BUS_TRANS_BRD.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -123,6 +141,7 @@
},
{
"BriefDescription": "Burst read bus transactions.",
"Counter": "0,1",
"EventCode": "0x65",
"EventName": "BUS_TRANS_BRD.SELF",
"SampleAfterValue": "200000",
@ -130,6 +149,7 @@
},
{
"BriefDescription": "Burst (full cache-line) bus transactions.",
"Counter": "0,1",
"EventCode": "0x6E",
"EventName": "BUS_TRANS_BURST.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -137,6 +157,7 @@
},
{
"BriefDescription": "Burst (full cache-line) bus transactions.",
"Counter": "0,1",
"EventCode": "0x6E",
"EventName": "BUS_TRANS_BURST.SELF",
"SampleAfterValue": "200000",
@ -144,6 +165,7 @@
},
{
"BriefDescription": "Deferred bus transactions.",
"Counter": "0,1",
"EventCode": "0x6D",
"EventName": "BUS_TRANS_DEF.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -151,6 +173,7 @@
},
{
"BriefDescription": "Deferred bus transactions.",
"Counter": "0,1",
"EventCode": "0x6D",
"EventName": "BUS_TRANS_DEF.SELF",
"SampleAfterValue": "200000",
@ -158,6 +181,7 @@
},
{
"BriefDescription": "Instruction-fetch bus transactions.",
"Counter": "0,1",
"EventCode": "0x68",
"EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -165,6 +189,7 @@
},
{
"BriefDescription": "Instruction-fetch bus transactions.",
"Counter": "0,1",
"EventCode": "0x68",
"EventName": "BUS_TRANS_IFETCH.SELF",
"SampleAfterValue": "200000",
@ -172,6 +197,7 @@
},
{
"BriefDescription": "Invalidate bus transactions.",
"Counter": "0,1",
"EventCode": "0x69",
"EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -179,6 +205,7 @@
},
{
"BriefDescription": "Invalidate bus transactions.",
"Counter": "0,1",
"EventCode": "0x69",
"EventName": "BUS_TRANS_INVAL.SELF",
"SampleAfterValue": "200000",
@ -186,6 +213,7 @@
},
{
"BriefDescription": "IO bus transactions.",
"Counter": "0,1",
"EventCode": "0x6C",
"EventName": "BUS_TRANS_IO.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -193,6 +221,7 @@
},
{
"BriefDescription": "IO bus transactions.",
"Counter": "0,1",
"EventCode": "0x6C",
"EventName": "BUS_TRANS_IO.SELF",
"SampleAfterValue": "200000",
@ -200,6 +229,7 @@
},
{
"BriefDescription": "Memory bus transactions.",
"Counter": "0,1",
"EventCode": "0x6F",
"EventName": "BUS_TRANS_MEM.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -207,6 +237,7 @@
},
{
"BriefDescription": "Memory bus transactions.",
"Counter": "0,1",
"EventCode": "0x6F",
"EventName": "BUS_TRANS_MEM.SELF",
"SampleAfterValue": "200000",
@ -214,6 +245,7 @@
},
{
"BriefDescription": "Partial bus transactions.",
"Counter": "0,1",
"EventCode": "0x6B",
"EventName": "BUS_TRANS_P.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -221,6 +253,7 @@
},
{
"BriefDescription": "Partial bus transactions.",
"Counter": "0,1",
"EventCode": "0x6B",
"EventName": "BUS_TRANS_P.SELF",
"SampleAfterValue": "200000",
@ -228,6 +261,7 @@
},
{
"BriefDescription": "Partial write bus transaction.",
"Counter": "0,1",
"EventCode": "0x6A",
"EventName": "BUS_TRANS_PWR.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -235,6 +269,7 @@
},
{
"BriefDescription": "Partial write bus transaction.",
"Counter": "0,1",
"EventCode": "0x6A",
"EventName": "BUS_TRANS_PWR.SELF",
"SampleAfterValue": "200000",
@ -242,6 +277,7 @@
},
{
"BriefDescription": "RFO bus transactions.",
"Counter": "0,1",
"EventCode": "0x66",
"EventName": "BUS_TRANS_RFO.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -249,6 +285,7 @@
},
{
"BriefDescription": "RFO bus transactions.",
"Counter": "0,1",
"EventCode": "0x66",
"EventName": "BUS_TRANS_RFO.SELF",
"SampleAfterValue": "200000",
@ -256,6 +293,7 @@
},
{
"BriefDescription": "Explicit writeback bus transactions.",
"Counter": "0,1",
"EventCode": "0x67",
"EventName": "BUS_TRANS_WB.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -263,6 +301,7 @@
},
{
"BriefDescription": "Explicit writeback bus transactions.",
"Counter": "0,1",
"EventCode": "0x67",
"EventName": "BUS_TRANS_WB.SELF",
"SampleAfterValue": "200000",
@ -270,6 +309,7 @@
},
{
"BriefDescription": "Cycles during which interrupts are disabled.",
"Counter": "0,1",
"EventCode": "0xC6",
"EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED",
"SampleAfterValue": "2000000",
@ -277,6 +317,7 @@
},
{
"BriefDescription": "Cycles during which interrupts are pending and disabled.",
"Counter": "0,1",
"EventCode": "0xC6",
"EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",
"SampleAfterValue": "2000000",
@ -284,6 +325,7 @@
},
{
"BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
"Counter": "0,1",
"EventCode": "0x9",
"EventName": "DISPATCH_BLOCKED.ANY",
"SampleAfterValue": "200000",
@ -291,12 +333,14 @@
},
{
"BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
"Counter": "0,1",
"EventCode": "0x3A",
"EventName": "EIST_TRANS",
"SampleAfterValue": "200000"
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
"SampleAfterValue": "200000",
@ -304,6 +348,7 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
"SampleAfterValue": "200000",
@ -311,6 +356,7 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
"SampleAfterValue": "200000",
@ -318,6 +364,7 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
"SampleAfterValue": "200000",
@ -325,6 +372,7 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.THIS_AGENT.ANY",
"SampleAfterValue": "200000",
@ -332,6 +380,7 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
"SampleAfterValue": "200000",
@ -339,6 +388,7 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.THIS_AGENT.HIT",
"SampleAfterValue": "200000",
@ -346,6 +396,7 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.THIS_AGENT.HITM",
"SampleAfterValue": "200000",
@ -353,12 +404,14 @@
},
{
"BriefDescription": "Hardware interrupts received.",
"Counter": "0,1",
"EventCode": "0xC8",
"EventName": "HW_INT_RCV",
"SampleAfterValue": "200000"
},
{
"BriefDescription": "Number of segment register loads.",
"Counter": "0,1",
"EventCode": "0x6",
"EventName": "SEGMENT_REG_LOADS.ANY",
"SampleAfterValue": "200000",
@ -366,6 +419,7 @@
},
{
"BriefDescription": "Bus stalled for snoops.",
"Counter": "0,1",
"EventCode": "0x7E",
"EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -373,6 +427,7 @@
},
{
"BriefDescription": "Bus stalled for snoops.",
"Counter": "0,1",
"EventCode": "0x7E",
"EventName": "SNOOP_STALL_DRV.SELF",
"SampleAfterValue": "200000",
@ -380,6 +435,7 @@
},
{
"BriefDescription": "Number of thermal trips",
"Counter": "0,1",
"EventCode": "0x3B",
"EventName": "THERMAL_TRIP",
"SampleAfterValue": "200000",

44
tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Bogus branches",
"Counter": "0,1",
"EventCode": "0xE4",
"EventName": "BOGUS_BR",
"SampleAfterValue": "2000000",
@ -8,6 +9,7 @@
},
{
"BriefDescription": "Branch instructions decoded",
"Counter": "0,1",
"EventCode": "0xE0",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
@ -15,12 +17,14 @@
},
{
"BriefDescription": "Retired branch instructions.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ANY",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Retired branch instructions.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ANY1",
"SampleAfterValue": "2000000",
@ -28,6 +32,7 @@
},
{
"BriefDescription": "Retired mispredicted branch instructions (precise event).",
"Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_INST_RETIRED.MISPRED",
"PEBS": "1",
@ -35,6 +40,7 @@
},
{
"BriefDescription": "Retired branch instructions that were mispredicted not-taken.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
"SampleAfterValue": "200000",
@ -42,6 +48,7 @@
},
{
"BriefDescription": "Retired branch instructions that were mispredicted taken.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
"SampleAfterValue": "200000",
@ -49,6 +56,7 @@
},
{
"BriefDescription": "Retired branch instructions that were predicted not-taken.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
"SampleAfterValue": "2000000",
@ -56,6 +64,7 @@
},
{
"BriefDescription": "Retired branch instructions that were predicted taken.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.PRED_TAKEN",
"SampleAfterValue": "2000000",
@ -63,6 +72,7 @@
},
{
"BriefDescription": "Retired taken branch instructions.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.TAKEN",
"SampleAfterValue": "2000000",
@ -70,6 +80,7 @@
},
{
"BriefDescription": "All macro conditional branch instructions.",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.COND",
"SampleAfterValue": "2000000",
@ -77,6 +88,7 @@
},
{
"BriefDescription": "Only taken macro conditional branch instructions",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
"SampleAfterValue": "2000000",
@ -84,6 +96,7 @@
},
{
"BriefDescription": "All non-indirect calls",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
"SampleAfterValue": "2000000",
@ -91,6 +104,7 @@
},
{
"BriefDescription": "All indirect branches that are not calls.",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.IND",
"SampleAfterValue": "2000000",
@ -98,6 +112,7 @@
},
{
"BriefDescription": "All indirect calls, including both register and memory indirect.",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
"SampleAfterValue": "2000000",
@ -105,6 +120,7 @@
},
{
"BriefDescription": "All indirect branches that have a return mnemonic",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.RET",
"SampleAfterValue": "2000000",
@ -112,6 +128,7 @@
},
{
"BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.UNCOND",
"SampleAfterValue": "2000000",
@ -119,6 +136,7 @@
},
{
"BriefDescription": "Mispredicted cond branch instructions retired",
"Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.COND",
"SampleAfterValue": "200000",
@ -126,6 +144,7 @@
},
{
"BriefDescription": "Mispredicted and taken cond branch instructions retired",
"Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
"SampleAfterValue": "200000",
@ -133,6 +152,7 @@
},
{
"BriefDescription": "Mispredicted ind branches that are not calls",
"Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.IND",
"SampleAfterValue": "200000",
@ -140,6 +160,7 @@
},
{
"BriefDescription": "Mispredicted indirect calls, including both register and memory indirect.",
"Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
"SampleAfterValue": "200000",
@ -147,6 +168,7 @@
},
{
"BriefDescription": "Mispredicted return branches",
"Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
"SampleAfterValue": "200000",
@ -154,6 +176,7 @@
},
{
"BriefDescription": "Bus cycles when core is not halted",
"Counter": "0,1",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.BUS",
"SampleAfterValue": "200000",
@ -161,24 +184,28 @@
},
{
"BriefDescription": "Core cycles when core is not halted",
"Counter": "Fixed counter 2",
"EventCode": "0xA",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Core cycles when core is not halted",
"Counter": "0,1",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Reference cycles when core is not halted.",
"Counter": "Fixed counter 3",
"EventCode": "0xA",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Cycles the divider is busy.",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
@ -186,6 +213,7 @@
},
{
"BriefDescription": "Divide operations retired",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "DIV.AR",
"SampleAfterValue": "2000000",
@ -193,6 +221,7 @@
},
{
"BriefDescription": "Divide operations executed.",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "DIV.S",
"SampleAfterValue": "2000000",
@ -200,12 +229,14 @@
},
{
"BriefDescription": "Instructions retired.",
"Counter": "Fixed counter 1",
"EventCode": "0xA",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Instructions retired (precise event).",
"Counter": "0,1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "2",
@ -213,6 +244,7 @@
},
{
"BriefDescription": "Self-Modifying Code detected.",
"Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "200000",
@ -220,6 +252,7 @@
},
{
"BriefDescription": "Multiply operations retired",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "MUL.AR",
"SampleAfterValue": "2000000",
@ -227,6 +260,7 @@
},
{
"BriefDescription": "Multiply operations executed.",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "MUL.S",
"SampleAfterValue": "2000000",
@ -234,6 +268,7 @@
},
{
"BriefDescription": "Micro-op reissues for any cause",
"Counter": "0,1",
"EventCode": "0x3",
"EventName": "REISSUE.ANY",
"SampleAfterValue": "200000",
@ -241,6 +276,7 @@
},
{
"BriefDescription": "Micro-op reissues for any cause (At Retirement)",
"Counter": "0,1",
"EventCode": "0x3",
"EventName": "REISSUE.ANY.AR",
"SampleAfterValue": "200000",
@ -248,6 +284,7 @@
},
{
"BriefDescription": "Micro-op reissues on a store-load collision",
"Counter": "0,1",
"EventCode": "0x3",
"EventName": "REISSUE.OVERLAP_STORE",
"SampleAfterValue": "200000",
@ -255,6 +292,7 @@
},
{
"BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)",
"Counter": "0,1",
"EventCode": "0x3",
"EventName": "REISSUE.OVERLAP_STORE.AR",
"SampleAfterValue": "200000",
@ -262,6 +300,7 @@
},
{
"BriefDescription": "Cycles issue is stalled due to div busy.",
"Counter": "0,1",
"EventCode": "0xDC",
"EventName": "RESOURCE_STALLS.DIV_BUSY",
"SampleAfterValue": "2000000",
@ -269,6 +308,7 @@
},
{
"BriefDescription": "All store forwards",
"Counter": "0,1",
"EventCode": "0x2",
"EventName": "STORE_FORWARDS.ANY",
"SampleAfterValue": "200000",
@ -276,6 +316,7 @@
},
{
"BriefDescription": "Good store forwards",
"Counter": "0,1",
"EventCode": "0x2",
"EventName": "STORE_FORWARDS.GOOD",
"SampleAfterValue": "200000",
@ -283,6 +324,7 @@
},
{
"BriefDescription": "Micro-ops retired.",
"Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"SampleAfterValue": "2000000",
@ -290,6 +332,7 @@
},
{
"BriefDescription": "Cycles no micro-ops retired.",
"Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALLED_CYCLES",
"SampleAfterValue": "2000000",
@ -297,6 +340,7 @@
},
{
"BriefDescription": "Periods no micro-ops retired.",
"Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALLS",
"SampleAfterValue": "2000000",

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