RDMA/hns: Clean the hardware related code for HEM
Move the HIP06 related code to the hw v1 source file for HEM. Link: https://lore.kernel.org/r/1621589395-2435-6-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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@ -47,8 +47,6 @@
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#define HNS_ROCE_IB_MIN_SQ_STRIDE 6
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#define HNS_ROCE_BA_SIZE (32 * 4096)
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#define BA_BYTE_LEN 8
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/* Hardware specification only for v1 engine */
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@ -36,9 +36,6 @@
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#include "hns_roce_hem.h"
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#include "hns_roce_common.h"
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#define DMA_ADDR_T_SHIFT 12
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#define BT_BA_SHIFT 32
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#define HEM_INDEX_BUF BIT(0)
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#define HEM_INDEX_L0 BIT(1)
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#define HEM_INDEX_L1 BIT(2)
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@ -337,81 +334,6 @@ void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem)
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kfree(hem);
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}
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static int hns_roce_set_hem(struct hns_roce_dev *hr_dev,
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struct hns_roce_hem_table *table, unsigned long obj)
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{
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spinlock_t *lock = &hr_dev->bt_cmd_lock;
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struct device *dev = hr_dev->dev;
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struct hns_roce_hem_iter iter;
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void __iomem *bt_cmd;
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__le32 bt_cmd_val[2];
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__le32 bt_cmd_h = 0;
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unsigned long flags;
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__le32 bt_cmd_l;
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int ret = 0;
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u64 bt_ba;
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long end;
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/* Find the HEM(Hardware Entry Memory) entry */
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unsigned long i = (obj & (table->num_obj - 1)) /
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(table->table_chunk_size / table->obj_size);
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switch (table->type) {
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case HEM_TYPE_QPC:
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case HEM_TYPE_MTPT:
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case HEM_TYPE_CQC:
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case HEM_TYPE_SRQC:
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roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
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ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
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break;
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default:
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return ret;
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}
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roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
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ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
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roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
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roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
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/* Currently iter only a chunk */
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for (hns_roce_hem_first(table->hem[i], &iter);
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!hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
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bt_ba = hns_roce_hem_addr(&iter) >> DMA_ADDR_T_SHIFT;
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spin_lock_irqsave(lock, flags);
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bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
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end = HW_SYNC_TIMEOUT_MSECS;
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while (end > 0) {
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if (!(readl(bt_cmd) >> BT_CMD_SYNC_SHIFT))
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break;
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mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
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end -= HW_SYNC_SLEEP_TIME_INTERVAL;
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}
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if (end <= 0) {
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dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
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spin_unlock_irqrestore(lock, flags);
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return -EBUSY;
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}
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bt_cmd_l = cpu_to_le32(bt_ba);
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roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
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ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S,
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bt_ba >> BT_BA_SHIFT);
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bt_cmd_val[0] = bt_cmd_l;
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bt_cmd_val[1] = bt_cmd_h;
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hns_roce_write64_k(bt_cmd_val,
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hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
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spin_unlock_irqrestore(lock, flags);
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}
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return ret;
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}
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static int calc_hem_config(struct hns_roce_dev *hr_dev,
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struct hns_roce_hem_table *table, unsigned long obj,
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struct hns_roce_hem_mhop *mhop,
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@ -677,7 +599,7 @@ int hns_roce_table_get(struct hns_roce_dev *hr_dev,
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}
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/* Set HEM base address(128K/page, pa) to Hardware */
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if (hns_roce_set_hem(hr_dev, table, obj)) {
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if (hr_dev->hw->set_hem(hr_dev, table, obj, HEM_HOP_STEP_DIRECT)) {
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hns_roce_free_hem(hr_dev, table->hem[i]);
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table->hem[i] = NULL;
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ret = -ENODEV;
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@ -782,7 +704,7 @@ void hns_roce_table_put(struct hns_roce_dev *hr_dev,
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&table->mutex))
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return;
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if (hr_dev->hw->clear_hem(hr_dev, table, obj, 0))
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if (hr_dev->hw->clear_hem(hr_dev, table, obj, HEM_HOP_STEP_DIRECT))
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dev_warn(dev, "failed to clear HEM base address.\n");
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hns_roce_free_hem(hr_dev, table->hem[i]);
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@ -34,9 +34,7 @@
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#ifndef _HNS_ROCE_HEM_H
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#define _HNS_ROCE_HEM_H
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#define HW_SYNC_SLEEP_TIME_INTERVAL 20
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#define HW_SYNC_TIMEOUT_MSECS (25 * HW_SYNC_SLEEP_TIME_INTERVAL)
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#define BT_CMD_SYNC_SHIFT 31
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#define HEM_HOP_STEP_DIRECT 0xff
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enum {
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/* MAP HEM(Hardware Entry Memory) */
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@ -74,11 +72,6 @@ enum {
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(type >= HEM_TYPE_MTT && hop_num == 1) || \
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(type >= HEM_TYPE_MTT && hop_num == HNS_ROCE_HOP_NUM_0))
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enum {
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HNS_ROCE_HEM_PAGE_SHIFT = 12,
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HNS_ROCE_HEM_PAGE_SIZE = 1 << HNS_ROCE_HEM_PAGE_SHIFT,
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};
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struct hns_roce_hem_chunk {
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struct list_head list;
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int npages;
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@ -462,6 +462,82 @@ static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
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roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
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}
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static int hns_roce_v1_set_hem(struct hns_roce_dev *hr_dev,
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struct hns_roce_hem_table *table, int obj,
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int step_idx)
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{
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spinlock_t *lock = &hr_dev->bt_cmd_lock;
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struct device *dev = hr_dev->dev;
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struct hns_roce_hem_iter iter;
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void __iomem *bt_cmd;
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__le32 bt_cmd_val[2];
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__le32 bt_cmd_h = 0;
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unsigned long flags;
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__le32 bt_cmd_l;
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int ret = 0;
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u64 bt_ba;
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long end;
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/* Find the HEM(Hardware Entry Memory) entry */
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unsigned long i = (obj & (table->num_obj - 1)) /
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(table->table_chunk_size / table->obj_size);
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switch (table->type) {
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case HEM_TYPE_QPC:
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case HEM_TYPE_MTPT:
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case HEM_TYPE_CQC:
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case HEM_TYPE_SRQC:
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roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
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ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
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break;
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default:
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return ret;
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}
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roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
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ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
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roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
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roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
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/* Currently iter only a chunk */
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for (hns_roce_hem_first(table->hem[i], &iter);
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!hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
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bt_ba = hns_roce_hem_addr(&iter) >> HNS_HW_PAGE_SHIFT;
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spin_lock_irqsave(lock, flags);
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bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
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end = HW_SYNC_TIMEOUT_MSECS;
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while (end > 0) {
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if (!(readl(bt_cmd) >> BT_CMD_SYNC_SHIFT))
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break;
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mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
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end -= HW_SYNC_SLEEP_TIME_INTERVAL;
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}
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if (end <= 0) {
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dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
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spin_unlock_irqrestore(lock, flags);
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return -EBUSY;
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}
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bt_cmd_l = cpu_to_le32(bt_ba);
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roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
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ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S,
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upper_32_bits(bt_ba));
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bt_cmd_val[0] = bt_cmd_l;
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bt_cmd_val[1] = bt_cmd_h;
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hns_roce_write64_k(bt_cmd_val,
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hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
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spin_unlock_irqrestore(lock, flags);
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}
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return ret;
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}
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static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
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u32 odb_mode)
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{
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@ -4352,6 +4428,7 @@ static const struct hns_roce_hw hns_roce_hw_v1 = {
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.set_mtu = hns_roce_v1_set_mtu,
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.write_mtpt = hns_roce_v1_write_mtpt,
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.write_cqc = hns_roce_v1_write_cqc,
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.set_hem = hns_roce_v1_set_hem,
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.clear_hem = hns_roce_v1_clear_hem,
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.modify_qp = hns_roce_v1_modify_qp,
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.dereg_mr = hns_roce_v1_dereg_mr,
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@ -1085,6 +1085,11 @@ struct hns_roce_db_table {
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struct hns_roce_ext_db *ext_db;
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};
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#define HW_SYNC_SLEEP_TIME_INTERVAL 20
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#define HW_SYNC_TIMEOUT_MSECS (25 * HW_SYNC_SLEEP_TIME_INTERVAL)
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#define BT_CMD_SYNC_SHIFT 31
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#define HNS_ROCE_BA_SIZE (32 * 4096)
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struct hns_roce_bt_table {
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struct hns_roce_buf_list qpc_buf;
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struct hns_roce_buf_list mtpt_buf;
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