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iio: imu: adis: ensure proper DMA alignment

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commit 8e98b87f515d8c4bae521048a037b2cc431c3fd5 upstream.

Aligning the buffer to the L1 cache is not sufficient in some platforms
as they might have larger cacheline sizes for caches after L1 and thus,
we can't guarantee DMA safety.

That was the whole reason to introduce IIO_DMA_MINALIGN in [1]. Do the same
for the sigma_delta ADCs.

[1]: https://lore.kernel.org/linux-iio/20220508175712.647246-2-jic23@kernel.org/

Fixes: ccd2b52f4ac6 ("staging:iio: Add common ADIS library")
Signed-off-by: Nuno Sa <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20240117-adis-improv-v1-1-7f90e9fad200@analog.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Nuno Sa 2024-01-17 14:10:49 +01:00 committed by Greg Kroah-Hartman
parent c0f2ab954b
commit 68f2bdcbd7
1 changed files with 2 additions and 1 deletions
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3
include/linux/iio/imu/adis.h
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@ -11,6 +11,7 @@
#include <linux/spi/spi.h>
#include <linux/interrupt.h>
#include <linux/iio/iio.h>
#include <linux/iio/types.h>
#define ADIS_WRITE_REG(reg) ((0x80 | (reg)))
@ -131,7 +132,7 @@ struct adis {
unsigned long irq_flag;
void *buffer;
u8 tx[10] ____cacheline_aligned;
u8 tx[10] __aligned(IIO_DMA_MINALIGN);
u8 rx[4];
};