PCI: microchip: Move PLDA IP register macros to pcie-plda.h
Move PLDA PCIe host controller IP registers macros to pcie-plda.h, including bridge registers and PLDA IRQ event number. Link: https://lore.kernel.org/linux-pci/20240328091835.14797-4-minda.chen@starfivetech.com Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Minda Chen
Bjorn Helgaas
parent
24934ee897
commit
692c9b0a64
@ -17224,6 +17224,7 @@ M: Daire McNamara <daire.mcnamara@microchip.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml
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F: drivers/pci/controller/plda/pcie-plda.h
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PCI DRIVER FOR RENESAS R-CAR
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M: Marek Vasut <marek.vasut+renesas@gmail.com>
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@ -19,6 +19,7 @@
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#include <linux/platform_device.h>
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#include "../../pci.h"
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#include "pcie-plda.h"
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/* Number of MSI IRQs */
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#define MC_MAX_NUM_MSI_IRQS 32
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@ -30,84 +31,6 @@
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#define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR)
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#define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR)
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/* PCIe Bridge Phy Regs */
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#define PCIE_PCI_IRQ_DW0 0xa8
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#define MSIX_CAP_MASK BIT(31)
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#define NUM_MSI_MSGS_MASK GENMASK(6, 4)
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#define NUM_MSI_MSGS_SHIFT 4
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#define IMASK_LOCAL 0x180
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#define DMA_END_ENGINE_0_MASK 0x00000000u
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#define DMA_END_ENGINE_0_SHIFT 0
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#define DMA_END_ENGINE_1_MASK 0x00000000u
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#define DMA_END_ENGINE_1_SHIFT 1
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#define DMA_ERROR_ENGINE_0_MASK 0x00000100u
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#define DMA_ERROR_ENGINE_0_SHIFT 8
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#define DMA_ERROR_ENGINE_1_MASK 0x00000200u
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#define DMA_ERROR_ENGINE_1_SHIFT 9
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#define A_ATR_EVT_POST_ERR_MASK 0x00010000u
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#define A_ATR_EVT_POST_ERR_SHIFT 16
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#define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u
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#define A_ATR_EVT_FETCH_ERR_SHIFT 17
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#define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u
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#define A_ATR_EVT_DISCARD_ERR_SHIFT 18
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#define A_ATR_EVT_DOORBELL_MASK 0x00000000u
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#define A_ATR_EVT_DOORBELL_SHIFT 19
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#define P_ATR_EVT_POST_ERR_MASK 0x00100000u
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#define P_ATR_EVT_POST_ERR_SHIFT 20
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#define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u
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#define P_ATR_EVT_FETCH_ERR_SHIFT 21
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#define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u
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#define P_ATR_EVT_DISCARD_ERR_SHIFT 22
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#define P_ATR_EVT_DOORBELL_MASK 0x00000000u
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#define P_ATR_EVT_DOORBELL_SHIFT 23
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#define PM_MSI_INT_INTA_MASK 0x01000000u
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#define PM_MSI_INT_INTA_SHIFT 24
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#define PM_MSI_INT_INTB_MASK 0x02000000u
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#define PM_MSI_INT_INTB_SHIFT 25
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#define PM_MSI_INT_INTC_MASK 0x04000000u
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#define PM_MSI_INT_INTC_SHIFT 26
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#define PM_MSI_INT_INTD_MASK 0x08000000u
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#define PM_MSI_INT_INTD_SHIFT 27
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#define PM_MSI_INT_INTX_MASK 0x0f000000u
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#define PM_MSI_INT_INTX_SHIFT 24
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#define PM_MSI_INT_MSI_MASK 0x10000000u
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#define PM_MSI_INT_MSI_SHIFT 28
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#define PM_MSI_INT_AER_EVT_MASK 0x20000000u
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#define PM_MSI_INT_AER_EVT_SHIFT 29
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#define PM_MSI_INT_EVENTS_MASK 0x40000000u
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#define PM_MSI_INT_EVENTS_SHIFT 30
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#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u
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#define PM_MSI_INT_SYS_ERR_SHIFT 31
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#define NUM_LOCAL_EVENTS 15
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#define ISTATUS_LOCAL 0x184
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#define IMASK_HOST 0x188
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#define ISTATUS_HOST 0x18c
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#define IMSI_ADDR 0x190
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#define ISTATUS_MSI 0x194
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/* PCIe Master table init defines */
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#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u
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#define ATR0_PCIE_ATR_SIZE 0x25
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#define ATR0_PCIE_ATR_SIZE_SHIFT 1
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#define ATR0_PCIE_WIN0_SRC_ADDR 0x604u
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#define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u
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#define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu
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#define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u
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/* PCIe AXI slave table init defines */
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#define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u
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#define ATR_SIZE_SHIFT 1
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#define ATR_IMPL_ENABLE 1
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#define ATR0_AXI4_SLV0_SRC_ADDR 0x804u
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#define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u
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#define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu
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#define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u
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#define PCIE_TX_RX_INTERFACE 0x00000000u
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#define PCIE_CONFIG_INTERFACE 0x00000001u
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#define ATR_ENTRY_SIZE 32
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/* PCIe Controller Phy Regs */
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#define SEC_ERROR_EVENT_CNT 0x20
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#define DED_ERROR_EVENT_CNT 0x24
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@ -179,20 +102,21 @@
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#define EVENT_LOCAL_DMA_END_ENGINE_1 12
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#define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13
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#define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14
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#define EVENT_LOCAL_A_ATR_EVT_POST_ERR 15
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#define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR 16
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#define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR 17
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#define EVENT_LOCAL_A_ATR_EVT_DOORBELL 18
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#define EVENT_LOCAL_P_ATR_EVT_POST_ERR 19
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#define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR 20
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#define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR 21
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#define EVENT_LOCAL_P_ATR_EVT_DOORBELL 22
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#define EVENT_LOCAL_PM_MSI_INT_INTX 23
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#define EVENT_LOCAL_PM_MSI_INT_MSI 24
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#define EVENT_LOCAL_PM_MSI_INT_AER_EVT 25
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#define EVENT_LOCAL_PM_MSI_INT_EVENTS 26
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#define EVENT_LOCAL_PM_MSI_INT_SYS_ERR 27
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#define NUM_EVENTS 28
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#define NUM_MC_EVENTS 15
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#define EVENT_LOCAL_A_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_AXI_POST_ERR)
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#define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_AXI_FETCH_ERR)
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#define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_AXI_DISCARD_ERR)
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#define EVENT_LOCAL_A_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_AXI_DOORBELL)
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#define EVENT_LOCAL_P_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_PCIE_POST_ERR)
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#define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_PCIE_FETCH_ERR)
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#define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_PCIE_DISCARD_ERR)
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#define EVENT_LOCAL_P_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_PCIE_DOORBELL)
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#define EVENT_LOCAL_PM_MSI_INT_INTX (NUM_MC_EVENTS + PLDA_INTX)
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#define EVENT_LOCAL_PM_MSI_INT_MSI (NUM_MC_EVENTS + PLDA_MSI)
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#define EVENT_LOCAL_PM_MSI_INT_AER_EVT (NUM_MC_EVENTS + PLDA_AER_EVENT)
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#define EVENT_LOCAL_PM_MSI_INT_EVENTS (NUM_MC_EVENTS + PLDA_MISC_EVENTS)
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#define EVENT_LOCAL_PM_MSI_INT_SYS_ERR (NUM_MC_EVENTS + PLDA_SYS_ERR)
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#define NUM_EVENTS (NUM_MC_EVENTS + PLDA_INT_EVENT_NUM)
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#define PCIE_EVENT_CAUSE(x, s) \
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[EVENT_PCIE_ ## x] = { __stringify(x), s }
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108
drivers/pci/controller/plda/pcie-plda.h
Normal file
108
drivers/pci/controller/plda/pcie-plda.h
Normal file
@ -0,0 +1,108 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PLDA PCIe host controller driver
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*/
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#ifndef _PCIE_PLDA_H
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#define _PCIE_PLDA_H
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/* PCIe Bridge Phy Regs */
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#define PCIE_PCI_IRQ_DW0 0xa8
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#define MSIX_CAP_MASK BIT(31)
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#define NUM_MSI_MSGS_MASK GENMASK(6, 4)
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#define NUM_MSI_MSGS_SHIFT 4
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#define IMASK_LOCAL 0x180
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#define DMA_END_ENGINE_0_MASK 0x00000000u
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#define DMA_END_ENGINE_0_SHIFT 0
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#define DMA_END_ENGINE_1_MASK 0x00000000u
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#define DMA_END_ENGINE_1_SHIFT 1
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#define DMA_ERROR_ENGINE_0_MASK 0x00000100u
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#define DMA_ERROR_ENGINE_0_SHIFT 8
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#define DMA_ERROR_ENGINE_1_MASK 0x00000200u
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#define DMA_ERROR_ENGINE_1_SHIFT 9
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#define A_ATR_EVT_POST_ERR_MASK 0x00010000u
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#define A_ATR_EVT_POST_ERR_SHIFT 16
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#define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u
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#define A_ATR_EVT_FETCH_ERR_SHIFT 17
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#define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u
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#define A_ATR_EVT_DISCARD_ERR_SHIFT 18
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#define A_ATR_EVT_DOORBELL_MASK 0x00000000u
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#define A_ATR_EVT_DOORBELL_SHIFT 19
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#define P_ATR_EVT_POST_ERR_MASK 0x00100000u
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#define P_ATR_EVT_POST_ERR_SHIFT 20
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#define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u
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#define P_ATR_EVT_FETCH_ERR_SHIFT 21
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#define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u
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#define P_ATR_EVT_DISCARD_ERR_SHIFT 22
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#define P_ATR_EVT_DOORBELL_MASK 0x00000000u
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#define P_ATR_EVT_DOORBELL_SHIFT 23
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#define PM_MSI_INT_INTA_MASK 0x01000000u
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#define PM_MSI_INT_INTA_SHIFT 24
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#define PM_MSI_INT_INTB_MASK 0x02000000u
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#define PM_MSI_INT_INTB_SHIFT 25
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#define PM_MSI_INT_INTC_MASK 0x04000000u
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#define PM_MSI_INT_INTC_SHIFT 26
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#define PM_MSI_INT_INTD_MASK 0x08000000u
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#define PM_MSI_INT_INTD_SHIFT 27
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#define PM_MSI_INT_INTX_MASK 0x0f000000u
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#define PM_MSI_INT_INTX_SHIFT 24
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#define PM_MSI_INT_MSI_MASK 0x10000000u
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#define PM_MSI_INT_MSI_SHIFT 28
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#define PM_MSI_INT_AER_EVT_MASK 0x20000000u
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#define PM_MSI_INT_AER_EVT_SHIFT 29
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#define PM_MSI_INT_EVENTS_MASK 0x40000000u
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#define PM_MSI_INT_EVENTS_SHIFT 30
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#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u
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#define PM_MSI_INT_SYS_ERR_SHIFT 31
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#define NUM_LOCAL_EVENTS 15
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#define ISTATUS_LOCAL 0x184
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#define IMASK_HOST 0x188
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#define ISTATUS_HOST 0x18c
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#define IMSI_ADDR 0x190
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#define ISTATUS_MSI 0x194
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/* PCIe Master table init defines */
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#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u
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#define ATR0_PCIE_ATR_SIZE 0x25
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#define ATR0_PCIE_ATR_SIZE_SHIFT 1
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#define ATR0_PCIE_WIN0_SRC_ADDR 0x604u
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#define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u
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#define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu
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#define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u
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/* PCIe AXI slave table init defines */
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#define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u
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#define ATR_SIZE_SHIFT 1
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#define ATR_IMPL_ENABLE 1
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#define ATR0_AXI4_SLV0_SRC_ADDR 0x804u
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#define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u
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#define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu
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#define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u
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#define PCIE_TX_RX_INTERFACE 0x00000000u
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#define PCIE_CONFIG_INTERFACE 0x00000001u
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#define ATR_ENTRY_SIZE 32
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enum plda_int_event {
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PLDA_AXI_POST_ERR,
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PLDA_AXI_FETCH_ERR,
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PLDA_AXI_DISCARD_ERR,
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PLDA_AXI_DOORBELL,
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PLDA_PCIE_POST_ERR,
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PLDA_PCIE_FETCH_ERR,
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PLDA_PCIE_DISCARD_ERR,
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PLDA_PCIE_DOORBELL,
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PLDA_INTX,
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PLDA_MSI,
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PLDA_AER_EVENT,
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PLDA_MISC_EVENTS,
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PLDA_SYS_ERR,
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PLDA_INT_EVENT_NUM
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};
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#define PLDA_NUM_DMA_EVENTS 16
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#define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM)
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#endif
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