dt-bindings: phy: tegra20-usb-phy: Convert to schema
Convert NVIDIA Tegra20 USB PHY binding to schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210912181718.1328-2-digetx@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Dmitry Osipenko
Greg Kroah-Hartman
parent
202698580e
commit
6941d194fa
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Tegra SOC USB PHY
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The device node for Tegra SOC USB PHY:
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Required properties :
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- compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
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For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
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"nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
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tegra114, tegra124, tegra132, or tegra210.
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- reg : Defines the following set of registers, in the order listed:
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- The PHY's own register set.
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Always present.
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- The register set of the PHY containing the UTMI pad control registers.
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Present if-and-only-if phy_type == utmi.
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- phy_type : Should be one of "utmi", "ulpi" or "hsic".
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- clocks : Defines the clocks listed in the clock-names property.
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- clock-names : The following clock names must be present:
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- reg: The clock needed to access the PHY's own registers. This is the
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associated EHCI controller's clock. Always present.
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- pll_u: PLL_U. Always present.
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- timer: The timeout clock (clk_m). Present if phy_type == utmi.
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- utmi-pads: The clock needed to access the UTMI pad control registers.
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Present if phy_type == utmi.
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- ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2
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with pad group aka "nvidia,pins" cdev2 and pin mux option config aka
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"nvidia,function" pllp_out4).
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Present if phy_type == ulpi, and ULPI link mode is in use.
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Must include the following entries:
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- usb: The PHY's own reset signal.
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- utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control
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registers. Required even if phy_type == ulpi.
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Required properties for phy_type == ulpi:
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- nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
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Required PHY timing params for utmi phy, for all chips:
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- nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
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start of sync launches RxActive
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- nvidia,elastic-limit : Variable FIFO Depth of elastic input store
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- nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
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before declare IDLE.
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- nvidia,term-range-adj : Range adjusment on terminations
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- Either one of the following for HS driver output control:
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- nvidia,xcvr-setup : integer, uses the provided value.
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- nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read
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from the on-chip fuses
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If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.
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- nvidia,xcvr-lsfslew : LS falling slew rate control.
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- nvidia,xcvr-lsrslew : LS rising slew rate control.
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Required PHY timing params for utmi phy, only on Tegra30 and above:
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- nvidia,xcvr-hsslew : HS slew rate control.
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- nvidia,hssquelch-level : HS squelch detector level.
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- nvidia,hsdiscon-level : HS disconnect detector level.
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Optional properties:
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- nvidia,has-legacy-mode : boolean indicates whether this controller can
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operate in legacy mode (as APX 2500 / 2600). In legacy mode some
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registers are accessed through the APB_MISC base address instead of
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the USB controller.
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- nvidia,is-wired : boolean. Indicates whether we can do certain kind of power
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optimizations for the devices that are always connected. e.g. modem.
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- dr_mode : dual role mode. Indicates the working mode for the PHY. Can be
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"host", "peripheral", or "otg". Defaults to "host" if not defined.
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host means this is a host controller
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peripheral means it is device controller
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otg means it can operate as either ("on the go")
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- nvidia,has-utmi-pad-registers : boolean indicates whether this controller
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contains the UTMI pad control registers common to all USB controllers.
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VBUS control (required for dr_mode == otg, optional for dr_mode == host):
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- vbus-supply: regulator for VBUS
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@ -0,0 +1,357 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra USB PHY
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maintainers:
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- Dmitry Osipenko <digetx@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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- Thierry Reding <thierry.reding@gmail.com>
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- nvidia,tegra124-usb-phy
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- nvidia,tegra114-usb-phy
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- enum:
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- nvidia,tegra30-usb-phy
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- items:
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- enum:
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- nvidia,tegra30-usb-phy
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- nvidia,tegra20-usb-phy
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reg:
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minItems: 1
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maxItems: 2
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description: |
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PHY0 and PHY2 share power and ground, PHY0 contains shared registers.
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PHY0 and PHY2 must specify two register sets, where the first set is
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PHY own registers and the second set is the PHY0 registers.
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clocks:
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anyOf:
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- items:
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- description: Registers clock
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- description: Main PHY clock
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- items:
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- description: Registers clock
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- description: Main PHY clock
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- description: ULPI PHY clock
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- items:
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- description: Registers clock
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- description: Main PHY clock
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- description: UTMI pads control registers clock
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- items:
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- description: Registers clock
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- description: Main PHY clock
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- description: UTMI timeout clock
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- description: UTMI pads control registers clock
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clock-names:
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oneOf:
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- items:
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- const: reg
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- const: pll_u
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- items:
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- const: reg
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- const: pll_u
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- const: ulpi-link
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- items:
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- const: reg
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- const: pll_u
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- const: utmi-pads
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- items:
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- const: reg
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- const: pll_u
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- const: timer
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- const: utmi-pads
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resets:
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oneOf:
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- maxItems: 1
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description: PHY reset
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- items:
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- description: PHY reset
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- description: UTMI pads reset
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reset-names:
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oneOf:
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- const: usb
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- items:
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- const: usb
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- const: utmi-pads
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"#phy-cells":
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const: 0
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phy_type:
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$ref: /schemas/types.yaml#/definitions/string
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enum: [utmi, ulpi, hsic]
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dr_mode:
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$ref: /schemas/types.yaml#/definitions/string
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enum: [host, peripheral, otg]
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default: host
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vbus-supply:
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description: Regulator controlling USB VBUS.
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nvidia,has-legacy-mode:
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description: |
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Indicates whether this controller can operate in legacy mode
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(as APX 2500 / 2600). In legacy mode some registers are accessed
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through the APB_MISC base address instead of the USB controller.
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type: boolean
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nvidia,is-wired:
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description: |
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Indicates whether we can do certain kind of power optimizations for
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the devices that are always connected. e.g. modem.
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type: boolean
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nvidia,has-utmi-pad-registers:
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description: |
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Indicates whether this controller contains the UTMI pad control
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registers common to all USB controllers.
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type: boolean
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nvidia,hssync-start-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 31
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description: |
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Number of 480 MHz clock cycles to wait before start of sync launches
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RxActive.
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nvidia,elastic-limit:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 31
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description: Variable FIFO Depth of elastic input store.
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nvidia,idle-wait-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 31
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description: |
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Number of 480 MHz clock cycles of idle to wait before declare IDLE.
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nvidia,term-range-adj:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 15
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description: Range adjustment on terminations.
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nvidia,xcvr-setup:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 127
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description: Input of XCVR cell, HS driver output control.
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nvidia,xcvr-setup-use-fuses:
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description: Indicates that the value is read from the on-chip fuses.
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type: boolean
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nvidia,xcvr-lsfslew:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 3
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description: LS falling slew rate control.
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nvidia,xcvr-lsrslew:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 3
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description: LS rising slew rate control.
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nvidia,xcvr-hsslew:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 511
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description: HS slew rate control.
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nvidia,hssquelch-level:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 3
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description: HS squelch detector level.
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nvidia,hsdiscon-level:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 7
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description: HS disconnect detector level.
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nvidia,phy-reset-gpio:
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maxItems: 1
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description: GPIO used to reset the PHY.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- "#phy-cells"
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- phy_type
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additionalProperties: false
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allOf:
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- if:
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properties:
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phy_type:
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const: utmi
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then:
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properties:
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reg:
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minItems: 2
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maxItems: 2
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resets:
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maxItems: 2
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reset-names:
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maxItems: 2
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required:
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- nvidia,hssync-start-delay
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- nvidia,elastic-limit
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- nvidia,idle-wait-delay
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- nvidia,term-range-adj
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- nvidia,xcvr-lsfslew
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- nvidia,xcvr-lsrslew
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anyOf:
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- required: ["nvidia,xcvr-setup"]
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- required: ["nvidia,xcvr-setup-use-fuses"]
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if:
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properties:
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compatible:
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contains:
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const: nvidia,tegra30-usb-phy
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then:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: reg
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- const: pll_u
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- const: utmi-pads
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required:
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- nvidia,xcvr-hsslew
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- nvidia,hssquelch-level
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- nvidia,hsdiscon-level
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else:
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properties:
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: reg
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- const: pll_u
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- const: timer
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- const: utmi-pads
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- if:
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properties:
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phy_type:
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const: ulpi
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then:
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properties:
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reg:
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minItems: 1
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maxItems: 1
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clocks:
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minItems: 2
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maxItems: 3
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clock-names:
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minItems: 2
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maxItems: 3
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oneOf:
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- items:
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- const: reg
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- const: pll_u
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- items:
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- const: reg
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- const: pll_u
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- const: ulpi-link
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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minItems: 1
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maxItems: 2
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examples:
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- |
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#include <dt-bindings/clock/tegra124-car.h>
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usb-phy@7d008000 {
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compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
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reg = <0x7d008000 0x4000>,
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<0x7d000000 0x4000>;
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phy_type = "utmi";
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clocks = <&tegra_car TEGRA124_CLK_USB3>,
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<&tegra_car TEGRA124_CLK_PLL_U>,
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<&tegra_car TEGRA124_CLK_USBD>;
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clock-names = "reg", "pll_u", "utmi-pads";
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resets = <&tegra_car 59>, <&tegra_car 22>;
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reset-names = "usb", "utmi-pads";
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#phy-cells = <0>;
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nvidia,hssync-start-delay = <0>;
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nvidia,idle-wait-delay = <17>;
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nvidia,elastic-limit = <16>;
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nvidia,term-range-adj = <6>;
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nvidia,xcvr-setup = <9>;
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nvidia,xcvr-lsfslew = <0>;
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nvidia,xcvr-lsrslew = <3>;
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nvidia,hssquelch-level = <2>;
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nvidia,hsdiscon-level = <5>;
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nvidia,xcvr-hsslew = <12>;
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};
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- |
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#include <dt-bindings/clock/tegra20-car.h>
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usb-phy@c5004000 {
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compatible = "nvidia,tegra20-usb-phy";
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reg = <0xc5004000 0x4000>;
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phy_type = "ulpi";
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clocks = <&tegra_car TEGRA20_CLK_USB2>,
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<&tegra_car TEGRA20_CLK_PLL_U>,
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<&tegra_car TEGRA20_CLK_CDEV2>;
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clock-names = "reg", "pll_u", "ulpi-link";
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resets = <&tegra_car 58>, <&tegra_car 22>;
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reset-names = "usb", "utmi-pads";
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#phy-cells = <0>;
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};
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