staging: rtl8192e: Delete dead code
Signed-off-by: Mike McCormack <mikem@ring3k.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mike McCormack
Greg Kroah-Hartman
parent
db38680061
commit
699d015702
@ -21,7 +21,6 @@
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#define R8180_HW
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typedef enum _VERSION_8190{
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// RTL8190
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VERSION_8190_BD=0x3,
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VERSION_8190_BE
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}VERSION_8190,*PVERSION_8190;
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@ -38,15 +37,7 @@ typedef enum _BaseBand_Config_Type{
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BaseBand_Config_PHY_REG = 0, //Radio Path A
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BaseBand_Config_AGC_TAB = 1, //Radio Path B
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}BaseBand_Config_Type, *PBaseBand_Config_Type;
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#if 0
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typedef enum _RT_RF_TYPE_819xU{
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RF_TYPE_MIN = 0,
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RF_8225,
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RF_8256,
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RF_8258,
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RF_PSEUDO_11N = 4,
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}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
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#endif
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#define RTL8187_REQT_READ 0xc0
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#define RTL8187_REQT_WRITE 0x40
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#define RTL8187_REQ_GET_REGS 0x05
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@ -55,8 +46,6 @@ typedef enum _RT_RF_TYPE_819xU{
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#define R8180_MAX_RETRY 255
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#define MAX_TX_URB 5
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#define MAX_RX_URB 16
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//#define MAX_RX_NORMAL_URB 3
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//#define MAX_RX_COMMAND_URB 2
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#define RX_URB_SIZE 9100
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#define BB_ANTATTEN_CHAN14 0x0c
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@ -68,7 +57,6 @@ typedef enum _RT_RF_TYPE_819xU{
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#define BB_HOST_BANG_RW (1<<3)
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#define BB_HOST_BANG_DATA 1
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//#if (RTL819X_FPGA_VER & RTL819X_FPGA_VIVI_070920)
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#define RTL8190_EEPROM_ID 0x8129
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#define EEPROM_VID 0x02
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#define EEPROM_DID 0x04
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@ -103,7 +91,7 @@ typedef enum _RT_RF_TYPE_819xU{
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#define EEPROM_TxPwIndex_OFDM_24G 0x3A //0x24~0x26
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#define EEPROM_Default_TxPowerLevel 0x10
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//#define EEPROM_ChannelPlan 0x7c //0x7C
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#define EEPROM_IC_VER 0x7d //0x7D
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#define EEPROM_CRC 0x7e //0x7E~0x7F
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@ -117,7 +105,7 @@ typedef enum _RT_RF_TYPE_819xU{
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#define EEPROM_CID_Pronet 0x7
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#define EEPROM_CID_DLINK 0x8
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#define EEPROM_CID_WHQL 0xFE //added by sherry for dtm, 20080728
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//#endif
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enum _RTL8192Pci_HW {
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MAC0 = 0x000,
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MAC1 = 0x001,
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@ -485,311 +473,9 @@ enum _RTL8192Pci_HW {
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DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI
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MCS_TXAGC = 0x340, // MCS AGC
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CCK_TXAGC = 0x348, // CCK AGC
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// IMR = 0x354, // Interrupt Mask Register
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// IMR_POLL = 0x360,
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MacBlkCtrl = 0x403, // Mac block on/off control register
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//Cmd9346CR = 0x00e,
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//#define Cmd9346CR_9356SEL (1<<4)
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#if 0
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/* 0x0006 - 0x0007 - reserved */
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RXFIFOCOUNT = 0x010,
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TXFIFOCOUNT = 0x012,
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BQREQ = 0x013,
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/* 0x0010 - 0x0017 - reserved */
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TSFTR = 0x018,
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TLPDA = 0x020,
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TNPDA = 0x024,
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THPDA = 0x028,
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BSSID = 0x02E,
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RESP_RATE = 0x034,
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CMD = 0x037,
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#define CMD_RST_SHIFT 4
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#define CMD_RESERVED_MASK ((1<<1) | (1<<5) | (1<<6) | (1<<7))
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#define CMD_RX_ENABLE_SHIFT 3
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#define CMD_TX_ENABLE_SHIFT 2
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#define CR_RST ((1<< 4))
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#define CR_RE ((1<< 3))
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#define CR_TE ((1<< 2))
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#define CR_MulRW ((1<< 0))
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INTA = 0x03e,
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#endif
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///////////////////
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//////////////////
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#if 0
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TX_CONF = 0x040,
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#define TX_CONF_HEADER_AUTOICREMENT_SHIFT 30
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#define TX_LOOPBACK_SHIFT 17
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#define TX_LOOPBACK_MAC 1
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#define TX_LOOPBACK_BASEBAND 2
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#define TX_LOOPBACK_NONE 0
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#define TX_LOOPBACK_CONTINUE 3
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#define TX_LOOPBACK_MASK ((1<<17)|(1<<18))
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#define TX_LRLRETRY_SHIFT 0
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#define TX_SRLRETRY_SHIFT 8
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#define TX_NOICV_SHIFT 19
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#define TX_NOCRC_SHIFT 16
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#define TCR_DurProcMode ((1<<30))
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#define TCR_DISReqQsize ((1<<28))
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#define TCR_HWVERID_MASK ((1<<27)|(1<<26)|(1<<25))
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#define TCR_HWVERID_SHIFT 25
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#define TCR_SWPLCPLEN ((1<<24))
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#define TCR_PLCP_LEN TCR_SAT // rtl8180
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#define TCR_MXDMA_MASK ((1<<23)|(1<<22)|(1<<21))
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#define TCR_MXDMA_1024 6
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#define TCR_MXDMA_2048 7
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#define TCR_MXDMA_SHIFT 21
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#define TCR_DISCW ((1<<20))
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#define TCR_ICV ((1<<19))
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#define TCR_LBK ((1<<18)|(1<<17))
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#define TCR_LBK1 ((1<<18))
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#define TCR_LBK0 ((1<<17))
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#define TCR_CRC ((1<<16))
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#define TCR_SRL_MASK ((1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8))
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#define TCR_LRL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7))
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#define TCR_PROBE_NOTIMESTAMP_SHIFT 29 //rtl8185
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RX_CONF = 0x044,
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#define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \
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(1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23))
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#define RX_CHECK_BSSID_SHIFT 23
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#define ACCEPT_PWR_FRAME_SHIFT 22
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#define ACCEPT_MNG_FRAME_SHIFT 20
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#define ACCEPT_CTL_FRAME_SHIFT 19
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#define ACCEPT_DATA_FRAME_SHIFT 18
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#define ACCEPT_ICVERR_FRAME_SHIFT 12
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#define ACCEPT_CRCERR_FRAME_SHIFT 5
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#define ACCEPT_BCAST_FRAME_SHIFT 3
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#define ACCEPT_MCAST_FRAME_SHIFT 2
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#define ACCEPT_ALLMAC_FRAME_SHIFT 0
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#define ACCEPT_NICMAC_FRAME_SHIFT 1
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#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15))
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#define RX_FIFO_THRESHOLD_SHIFT 13
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#define RX_FIFO_THRESHOLD_128 3
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#define RX_FIFO_THRESHOLD_256 4
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#define RX_FIFO_THRESHOLD_512 5
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#define RX_FIFO_THRESHOLD_1024 6
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#define RX_FIFO_THRESHOLD_NONE 7
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#define RX_AUTORESETPHY_SHIFT 28
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#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10))
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#define MAX_RX_DMA_2048 7
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#define MAX_RX_DMA_1024 6
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#define MAX_RX_DMA_SHIFT 10
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#define RCR_ONLYERLPKT ((1<<31))
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#define RCR_CS_SHIFT 29
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#define RCR_CS_MASK ((1<<30) | (1<<29))
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#define RCR_ENMARP ((1<<28))
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#define RCR_CBSSID ((1<<23))
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#define RCR_APWRMGT ((1<<22))
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#define RCR_ADD3 ((1<<21))
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#define RCR_AMF ((1<<20))
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#define RCR_ACF ((1<<19))
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#define RCR_ADF ((1<<18))
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#define RCR_RXFTH ((1<<15)|(1<<14)|(1<<13))
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#define RCR_RXFTH2 ((1<<15))
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#define RCR_RXFTH1 ((1<<14))
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#define RCR_RXFTH0 ((1<<13))
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#define RCR_AICV ((1<<12))
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#define RCR_MXDMA ((1<<10)|(1<< 9)|(1<< 8))
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#define RCR_MXDMA2 ((1<<10))
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#define RCR_MXDMA1 ((1<< 9))
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#define RCR_MXDMA0 ((1<< 8))
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#define RCR_9356SEL ((1<< 6))
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#define RCR_ACRC32 ((1<< 5))
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#define RCR_AB ((1<< 3))
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#define RCR_AM ((1<< 2))
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#define RCR_APM ((1<< 1))
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#define RCR_AAP ((1<< 0))
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INT_TIMEOUT = 0x048,
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TX_BEACON_RING_ADDR = 0x04c,
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#endif
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#if 0
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CONFIG0 = 0x051,
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#define CONFIG0_WEP104 ((1<<6))
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#define CONFIG0_LEDGPO_En ((1<<4))
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#define CONFIG0_Aux_Status ((1<<3))
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#define CONFIG0_GL ((1<<1)|(1<<0))
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#define CONFIG0_GL1 ((1<<1))
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#define CONFIG0_GL0 ((1<<0))
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CONFIG1 = 0x052,
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#define CONFIG1_LEDS ((1<<7)|(1<<6))
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#define CONFIG1_LEDS1 ((1<<7))
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#define CONFIG1_LEDS0 ((1<<6))
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#define CONFIG1_LWACT ((1<<4))
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#define CONFIG1_MEMMAP ((1<<3))
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#define CONFIG1_IOMAP ((1<<2))
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#define CONFIG1_VPD ((1<<1))
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#define CONFIG1_PMEn ((1<<0))
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CONFIG2 = 0x053,
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#define CONFIG2_LCK ((1<<7))
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#define CONFIG2_ANT ((1<<6))
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#define CONFIG2_DPS ((1<<3))
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#define CONFIG2_PAPE_sign ((1<<2))
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#define CONFIG2_PAPE_time ((1<<1)|(1<<0))
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#define CONFIG2_PAPE_time1 ((1<<1))
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#define CONFIG2_PAPE_time0 ((1<<0))
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ANA_PARAM = 0x054,
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CONFIG3 = 0x059,
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#define CONFIG3_GNTSel ((1<<7))
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#define CONFIG3_PARM_En ((1<<6))
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#define CONFIG3_Magic ((1<<5))
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#define CONFIG3_CardB_En ((1<<3))
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#define CONFIG3_CLKRUN_En ((1<<2))
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#define CONFIG3_FuncRegEn ((1<<1))
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#define CONFIG3_FBtbEn ((1<<0))
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#define CONFIG3_CLKRUN_SHIFT 2
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#define CONFIG3_ANAPARAM_W_SHIFT 6
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CONFIG4 = 0x05a,
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#define CONFIG4_VCOPDN ((1<<7))
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#define CONFIG4_PWROFF ((1<<6))
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#define CONFIG4_PWRMGT ((1<<5))
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#define CONFIG4_LWPME ((1<<4))
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#define CONFIG4_LWPTN ((1<<2))
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#define CONFIG4_RFTYPE ((1<<1)|(1<<0))
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#define CONFIG4_RFTYPE1 ((1<<1))
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#define CONFIG4_RFTYPE0 ((1<<0))
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TESTR = 0x05b,
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#define TFPC_AC 0x05C
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#define SCR 0x05F
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PGSELECT = 0x05e,
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#define PGSELECT_PG_SHIFT 0
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SECURITY = 0x05f,
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#define SECURITY_WEP_TX_ENABLE_SHIFT 1
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#define SECURITY_WEP_RX_ENABLE_SHIFT 0
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#define SECURITY_ENCRYP_104 1
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#define SECURITY_ENCRYP_SHIFT 4
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#define SECURITY_ENCRYP_MASK ((1<<4)|(1<<5))
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ANA_PARAM2 = 0x060,
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BEACON_INTERVAL = 0x070,
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#define BEACON_INTERVAL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)| \
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(1<<6)|(1<<7)|(1<<8)|(1<<9))
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ATIM_WND = 0x072,
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#define ATIM_WND_MASK (0x01FF)
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BCN_INTR_ITV = 0x074,
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#define BCN_INTR_ITV_MASK (0x01FF)
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ATIM_INTR_ITV = 0x076,
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#define ATIM_INTR_ITV_MASK (0x01FF)
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AckTimeOutReg = 0x079, //ACK timeout register, in unit of 4 us.
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PHY_ADR = 0x07c,
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PHY_READ = 0x07e,
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RFPinsOutput = 0x080,
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RFPinsEnable = 0x082,
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//Page 0
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RFPinsSelect = 0x084,
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#define SW_CONTROL_GPIO 0x400
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RFPinsInput = 0x086,
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RF_PARA = 0x088,
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RF_TIMING = 0x08c,
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GP_ENABLE = 0x090,
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GPIO = 0x091,
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TX_AGC_CTL = 0x09c,
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#define TX_AGC_CTL_PER_PACKET_TXAGC 0x01
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#define TX_AGC_CTL_PERPACKET_GAIN_SHIFT 0
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#define TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT 1
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#define TX_AGC_CTL_FEEDBACK_ANT 2
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#define TXAGC_CTL_PER_PACKET_ANT_SEL 0x02
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OFDM_TXAGC = 0x09e,
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ANTSEL = 0x09f,
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SIFS = 0x0b4,
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DIFS = 0x0b5,
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SLOT = 0x0b6,
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CW_CONF = 0x0bc,
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#define CW_CONF_PERPACKET_RETRY_LIMIT 0x02
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#define CW_CONF_PERPACKET_CW 0x01
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#define CW_CONF_PERPACKET_RETRY_SHIFT 1
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#define CW_CONF_PERPACKET_CW_SHIFT 0
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CW_VAL = 0x0bd,
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RATE_FALLBACK = 0x0be,
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#define MAX_RESP_RATE_SHIFT 4
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#define MIN_RESP_RATE_SHIFT 0
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#define RATE_FALLBACK_CTL_ENABLE 0x80
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#define RATE_FALLBACK_CTL_AUTO_STEP0 0x00
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ACM_CONTROL = 0x0BF, // ACM Control Registe
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//----------------------------------------------------------------------------
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// 8187B ACM_CONTROL bits (Offset 0xBF, 1 Byte)
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//----------------------------------------------------------------------------
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#define VOQ_ACM_EN (0x01 << 7) //BIT7
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#define VIQ_ACM_EN (0x01 << 6) //BIT6
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#define BEQ_ACM_EN (0x01 << 5) //BIT5
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#define ACM_HW_EN (0x01 << 4) //BIT4
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#define TXOPSEL (0x01 << 3) //BIT3
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#define VOQ_ACM_CTL (0x01 << 2) //BIT2 // Set to 1 when AC_VO used time reaches or exceeds the admitted time
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#define VIQ_ACM_CTL (0x01 << 1) //BIT1 // Set to 1 when AC_VI used time reaches or exceeds the admitted time
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#define BEQ_ACM_CTL (0x01 << 0) //BIT0 // Set to 1 when AC_BE used time reaches or exceeds the admitted time
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CONFIG5 = 0x0D8,
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#define CONFIG5_TX_FIFO_OK ((1<<7))
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#define CONFIG5_RX_FIFO_OK ((1<<6))
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#define CONFIG5_CALON ((1<<5))
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#define CONFIG5_EACPI ((1<<2))
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#define CONFIG5_LANWake ((1<<1))
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#define CONFIG5_PME_STS ((1<<0))
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TX_DMA_POLLING = 0x0fd,
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#define TX_DMA_POLLING_BEACON_SHIFT 7
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#define TX_DMA_POLLING_HIPRIORITY_SHIFT 6
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#define TX_DMA_POLLING_NORMPRIORITY_SHIFT 5
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#define TX_DMA_POLLING_LOWPRIORITY_SHIFT 4
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#define TX_DMA_STOP_BEACON_SHIFT 3
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#define TX_DMA_STOP_HIPRIORITY_SHIFT 2
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#define TX_DMA_STOP_NORMPRIORITY_SHIFT 1
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#define TX_DMA_STOP_LOWPRIORITY_SHIFT 0
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CWR = 0x0DC,
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RetryCTR = 0x0DE,
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INT_MIG = 0x0E2, // Interrupt Migration (0xE2 ~ 0xE3)
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TID_AC_MAP = 0x0E8, // TID to AC Mapping Register
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ANA_PARAM3 = 0x0EE,
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//page 1
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Wakeup0 = 0x084,
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Wakeup1 = 0x08C,
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Wakeup2LD = 0x094,
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Wakeup2HD = 0x09C,
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Wakeup3LD = 0x0A4,
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Wakeup3HD = 0x0AC,
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Wakeup4LD = 0x0B4,
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Wakeup4HD = 0x0BC,
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CRC0 = 0x0C4,
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CRC1 = 0x0C6,
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CRC2 = 0x0C8,
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CRC3 = 0x0CA,
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CRC4 = 0x0CC,
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/* 0x00CE - 0x00D3 - reserved */
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RFSW_CTRL = 0x272, // 0x272-0x273.
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/**************************************************************************/
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FER = 0x0F0,
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FEMR = 0x0F4,
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FPSR = 0x0F8,
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FFER = 0x0FC,
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AC_VO_PARAM = 0x0F0, // AC_VO Parameters Record
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AC_VI_PARAM = 0x0F4, // AC_VI Parameters Record
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AC_BE_PARAM = 0x0F8, // AC_BE Parameters Record
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AC_BK_PARAM = 0x0FC, // AC_BK Parameters Record
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TALLY_SEL = 0x0fc,
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#endif
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}
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;
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//----------------------------------------------------------------------------
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// 818xB AnaParm & AnaParm2 Register
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//----------------------------------------------------------------------------
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//#define ANAPARM_ASIC_ON 0x45090658
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//#define ANAPARM2_ASIC_ON 0x727f3f52
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};
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#define GPI 0x108
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#define GPO 0x109
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