misc: Convert cs5535-mfgpt from pci device to platform device
The cs5535-mfd driver now takes care of the PCI BAR handling; this simplifies the mfgpt driver a bunch. Signed-off-by: Andres Salomon <dilinger@queued.net> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
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df96669401
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69bc6def39
@ -16,12 +16,11 @@
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/cs5535.h>
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#include <linux/slab.h>
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#define DRV_NAME "cs5535-mfgpt"
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#define MFGPT_BAR 2
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static int mfgpt_reset_timers;
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module_param_named(mfgptfix, mfgpt_reset_timers, int, 0644);
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@ -37,7 +36,7 @@ static struct cs5535_mfgpt_chip {
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DECLARE_BITMAP(avail, MFGPT_MAX_TIMERS);
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resource_size_t base;
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struct pci_dev *pdev;
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struct platform_device *pdev;
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spinlock_t lock;
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int initialized;
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} cs5535_mfgpt_chip;
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@ -290,10 +289,10 @@ static int __init scan_timers(struct cs5535_mfgpt_chip *mfgpt)
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return timers;
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}
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static int __init cs5535_mfgpt_probe(struct pci_dev *pdev,
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const struct pci_device_id *pci_id)
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static int __devinit cs5535_mfgpt_probe(struct platform_device *pdev)
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{
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int err, t;
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struct resource *res;
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int err = -EIO, t;
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/* There are two ways to get the MFGPT base address; one is by
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* fetching it from MSR_LBAR_MFGPT, the other is by reading the
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@ -302,29 +301,28 @@ static int __init cs5535_mfgpt_probe(struct pci_dev *pdev,
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* it turns out to be unreliable in the face of crappy BIOSes, we
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* can always go back to using MSRs.. */
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err = pci_enable_device_io(pdev);
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if (err) {
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dev_err(&pdev->dev, "can't enable device IO\n");
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res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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if (!res) {
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dev_err(&pdev->dev, "can't fetch device resource info\n");
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goto done;
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}
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err = pci_request_region(pdev, MFGPT_BAR, DRV_NAME);
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if (err) {
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dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", MFGPT_BAR);
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if (!request_region(res->start, resource_size(res), pdev->name)) {
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dev_err(&pdev->dev, "can't request region\n");
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goto done;
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}
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/* set up the driver-specific struct */
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cs5535_mfgpt_chip.base = pci_resource_start(pdev, MFGPT_BAR);
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cs5535_mfgpt_chip.base = res->start;
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cs5535_mfgpt_chip.pdev = pdev;
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spin_lock_init(&cs5535_mfgpt_chip.lock);
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dev_info(&pdev->dev, "allocated PCI BAR #%d: base 0x%llx\n", MFGPT_BAR,
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(unsigned long long) cs5535_mfgpt_chip.base);
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dev_info(&pdev->dev, "region 0x%x - 0x%x reserved\n", res->start,
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res->end);
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/* detect the available timers */
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t = scan_timers(&cs5535_mfgpt_chip);
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dev_info(&pdev->dev, DRV_NAME ": %d MFGPT timers available\n", t);
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dev_info(&pdev->dev, "%d MFGPT timers available\n", t);
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cs5535_mfgpt_chip.initialized = 1;
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return 0;
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@ -332,47 +330,18 @@ done:
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return err;
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}
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static struct pci_device_id cs5535_mfgpt_pci_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) },
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{ 0, },
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static struct platform_driver cs5535_mfgpt_drv = {
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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.probe = cs5535_mfgpt_probe,
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};
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MODULE_DEVICE_TABLE(pci, cs5535_mfgpt_pci_tbl);
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/*
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* Just like with the cs5535-gpio driver, we can't use the standard PCI driver
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* registration stuff. It only allows only one driver to bind to each PCI
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* device, and we want the GPIO and MFGPT drivers to be able to share a PCI
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* device. Instead, we manually scan for the PCI device, request a single
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* region, and keep track of the devices that we're using.
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*/
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static int __init cs5535_mfgpt_scan_pci(void)
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{
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struct pci_dev *pdev;
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int err = -ENODEV;
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int i;
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for (i = 0; i < ARRAY_SIZE(cs5535_mfgpt_pci_tbl); i++) {
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pdev = pci_get_device(cs5535_mfgpt_pci_tbl[i].vendor,
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cs5535_mfgpt_pci_tbl[i].device, NULL);
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if (pdev) {
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err = cs5535_mfgpt_probe(pdev,
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&cs5535_mfgpt_pci_tbl[i]);
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if (err)
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pci_dev_put(pdev);
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/* we only support a single CS5535/6 southbridge */
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break;
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}
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}
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return err;
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}
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static int __init cs5535_mfgpt_init(void)
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{
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return cs5535_mfgpt_scan_pci();
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return platform_driver_register(&cs5535_mfgpt_drv);
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}
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module_init(cs5535_mfgpt_init);
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