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clk: qcom: gcc-msm8916: move GPLL definitions up

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Move GPLL definitions up, before the clock parent tables, so that we can
use gpll hw clock fields in the parent_data/parent_hws tables.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220704172453.838303-5-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov 2022-07-04 20:24:50 +03:00 committed by Bjorn Andersson
parent 5a6d30675d
commit 69da4290a9
1 changed files with 108 additions and 108 deletions
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216
drivers/clk/qcom/gcc-msm8916.c
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@ -42,6 +42,114 @@ enum {
P_EXT_MCLK,
};
static struct clk_pll gpll0 = {
.l_reg = 0x21004,
.m_reg = 0x21008,
.n_reg = 0x2100c,
.config_reg = 0x21010,
.mode_reg = 0x21000,
.status_reg = 0x2101c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll0_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_vote",
.parent_names = (const char *[]){ "gpll0" },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll1 = {
.l_reg = 0x20004,
.m_reg = 0x20008,
.n_reg = 0x2000c,
.config_reg = 0x20010,
.mode_reg = 0x20000,
.status_reg = 0x2001c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll1_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_vote",
.parent_names = (const char *[]){ "gpll1" },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll2 = {
.l_reg = 0x4a004,
.m_reg = 0x4a008,
.n_reg = 0x4a00c,
.config_reg = 0x4a010,
.mode_reg = 0x4a000,
.status_reg = 0x4a01c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll2_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2_vote",
.parent_names = (const char *[]){ "gpll2" },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll bimc_pll = {
.l_reg = 0x23004,
.m_reg = 0x23008,
.n_reg = 0x2300c,
.config_reg = 0x23010,
.mode_reg = 0x23000,
.status_reg = 0x2301c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_pll",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap bimc_pll_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "bimc_pll_vote",
.parent_names = (const char *[]){ "bimc_pll" },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
@ -256,114 +364,6 @@ static const char * const gcc_xo_gpll1_emclk_sleep[] = {
"sleep_clk",
};
static struct clk_pll gpll0 = {
.l_reg = 0x21004,
.m_reg = 0x21008,
.n_reg = 0x2100c,
.config_reg = 0x21010,
.mode_reg = 0x21000,
.status_reg = 0x2101c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll0_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_vote",
.parent_names = (const char *[]){ "gpll0" },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll1 = {
.l_reg = 0x20004,
.m_reg = 0x20008,
.n_reg = 0x2000c,
.config_reg = 0x20010,
.mode_reg = 0x20000,
.status_reg = 0x2001c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll1_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_vote",
.parent_names = (const char *[]){ "gpll1" },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll2 = {
.l_reg = 0x4a004,
.m_reg = 0x4a008,
.n_reg = 0x4a00c,
.config_reg = 0x4a010,
.mode_reg = 0x4a000,
.status_reg = 0x4a01c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll2_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2_vote",
.parent_names = (const char *[]){ "gpll2" },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll bimc_pll = {
.l_reg = 0x23004,
.m_reg = 0x23008,
.n_reg = 0x2300c,
.config_reg = 0x23010,
.mode_reg = 0x23000,
.status_reg = 0x2301c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_pll",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap bimc_pll_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "bimc_pll_vote",
.parent_names = (const char *[]){ "bimc_pll" },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x27000,
.hid_width = 5,