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drm/amdgpu: loose check for umc poison mode

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No need to check poison setting for each channel, check for umc0
channel0 is enough.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tao Zhou 2022-02-10 15:46:12 +08:00 committed by Alex Deucher
parent f9ed188d5a
commit 69f915cc97
1 changed files with 5 additions and 13 deletions
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18
drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
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@ -451,21 +451,13 @@ static uint32_t umc_v6_7_query_ras_poison_mode_per_channel(
static bool umc_v6_7_query_ras_poison_mode(struct amdgpu_device *adev)
{
uint32_t umc_inst = 0;
uint32_t ch_inst = 0;
uint32_t umc_reg_offset = 0;
LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
umc_reg_offset = get_umc_v6_7_reg_offset(adev,
umc_inst,
ch_inst);
/* Enabling fatal error in one channel will be considered
as fatal error mode */
if (umc_v6_7_query_ras_poison_mode_per_channel(adev, umc_reg_offset))
return false;
}
return true;
/* Enabling fatal error in umc instance0 channel0 will be
* considered as fatal error mode
*/
umc_reg_offset = get_umc_v6_7_reg_offset(adev, 0, 0);
return !umc_v6_7_query_ras_poison_mode_per_channel(adev, umc_reg_offset);
}
const struct amdgpu_ras_block_hw_ops umc_v6_7_ras_hw_ops = {