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usb: dwc2: add defines to support s3c-hsotg driver

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In preparation of combining the dwc2/s3c-hsotg driver in a single
DRD driver, the defines in dwc2/hw.h needs to get updated so that
the s3c-hsotg driver can use them.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
[ jh,rb - For gadget part only: ]
Tested-by: Jingoo Han <jg1.han@samsung.com>
Tested-by: Robert Baldyga <r.baldyga@samsung.com>
[ pz - Tested host part only. ]
Signed-off-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Dinh Nguyen 2014-04-14 14:13:33 -07:00 committed by Greg Kroah-Hartman
parent 543cab6402
commit 6ab5332449
1 changed files with 7 additions and 5 deletions
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12
drivers/usb/dwc2/hw.h
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@ -109,6 +109,7 @@
#define GUSBCFG_FSINTF (1 << 5) #define GUSBCFG_FSINTF (1 << 5)
#define GUSBCFG_ULPI_UTMI_SEL (1 << 4) #define GUSBCFG_ULPI_UTMI_SEL (1 << 4)
#define GUSBCFG_PHYIF16 (1 << 3) #define GUSBCFG_PHYIF16 (1 << 3)
#define GUSBCFG_PHYIF8 (0 << 3)
#define GUSBCFG_TOUTCAL_MASK (0x7 << 0) #define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
#define GUSBCFG_TOUTCAL_SHIFT 0 #define GUSBCFG_TOUTCAL_SHIFT 0
#define GUSBCFG_TOUTCAL_LIMIT 0x7 #define GUSBCFG_TOUTCAL_LIMIT 0x7
@ -403,6 +404,7 @@
#define FIFOSIZE_DEPTH_SHIFT 16 #define FIFOSIZE_DEPTH_SHIFT 16
#define FIFOSIZE_STARTADDR_MASK (0xffff << 0) #define FIFOSIZE_STARTADDR_MASK (0xffff << 0)
#define FIFOSIZE_STARTADDR_SHIFT 0 #define FIFOSIZE_STARTADDR_SHIFT 0
#define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff)
/* Device mode registers */ /* Device mode registers */
@ -519,11 +521,11 @@
#define DXEPCTL_STALL (1 << 21) #define DXEPCTL_STALL (1 << 21)
#define DXEPCTL_SNP (1 << 20) #define DXEPCTL_SNP (1 << 20)
#define DXEPCTL_EPTYPE_MASK (0x3 << 18) #define DXEPCTL_EPTYPE_MASK (0x3 << 18)
#define DXEPCTL_EPTYPE_SHIFT 18 #define DXEPCTL_EPTYPE_CONTROL (0x0 << 18)
#define DXEPCTL_EPTYPE_CONTROL 0 #define DXEPCTL_EPTYPE_ISO (0x1 << 18)
#define DXEPCTL_EPTYPE_ISO 1 #define DXEPCTL_EPTYPE_BULK (0x2 << 18)
#define DXEPCTL_EPTYPE_BULK 2 #define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
#define DXEPCTL_EPTYPE_INTTERUPT 3
#define DXEPCTL_NAKSTS (1 << 17) #define DXEPCTL_NAKSTS (1 << 17)
#define DXEPCTL_DPID (1 << 16) #define DXEPCTL_DPID (1 << 16)
#define DXEPCTL_EOFRNUM (1 << 16) #define DXEPCTL_EOFRNUM (1 << 16)