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ASoC: SOF: Intel: remove circular dependency for

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Merge series from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:

The SoundWire BPT support will rely on the HDaudio DMA. This exposes a
circular dependency module dependency which has to be resolved by
splitting common parts used by HDaudio and SoundWire parts, and
'generic' parts used by HDaudio only.

This patchset does not change any functionality, it just moves code
around, exposes symbols that are used in the new module. The code has
been in use for more than one kernel cycle already so it really
shouldn't break any existing platforms.

The main issue with such code moves is that it makes backports or
fixes more complicated. That's the main reason why we held back these
patches until we were reasonably confident on the maturity of MTL and
LNL drivers.
This commit is contained in:
Mark Brown 2024-05-07 00:31:25 +09:00
commit 6b045e2e21
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
31 changed files with 811 additions and 637 deletions
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25
sound/soc/sof/intel/Kconfig
View File

@ -97,7 +97,7 @@ config SND_SOC_SOF_MERRIFIELD
config SND_SOC_SOF_INTEL_SKL
tristate
select SND_SOC_SOF_HDA_COMMON
select SND_SOC_SOF_HDA_GENERIC
select SND_SOC_SOF_IPC4
config SND_SOC_SOF_SKYLAKE
@ -122,7 +122,7 @@ config SND_SOC_SOF_KABYLAKE
config SND_SOC_SOF_INTEL_APL
tristate
select SND_SOC_SOF_HDA_COMMON
select SND_SOC_SOF_HDA_GENERIC
select SND_SOC_SOF_IPC3
select SND_SOC_SOF_IPC4
@ -148,7 +148,7 @@ config SND_SOC_SOF_GEMINILAKE
config SND_SOC_SOF_INTEL_CNL
tristate
select SND_SOC_SOF_HDA_COMMON
select SND_SOC_SOF_HDA_GENERIC
select SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE
select SND_SOC_SOF_IPC3
select SND_SOC_SOF_IPC4
@ -184,10 +184,11 @@ config SND_SOC_SOF_COMETLAKE
config SND_SOC_SOF_INTEL_ICL
tristate
select SND_SOC_SOF_HDA_COMMON
select SND_SOC_SOF_HDA_GENERIC
select SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE
select SND_SOC_SOF_IPC3
select SND_SOC_SOF_IPC4
select SND_SOC_SOF_INTEL_CNL
config SND_SOC_SOF_ICELAKE
tristate "SOF support for Icelake"
@ -211,10 +212,11 @@ config SND_SOC_SOF_JASPERLAKE
config SND_SOC_SOF_INTEL_TGL
tristate
select SND_SOC_SOF_HDA_COMMON
select SND_SOC_SOF_HDA_GENERIC
select SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE
select SND_SOC_SOF_IPC3
select SND_SOC_SOF_IPC4
select SND_SOC_SOF_INTEL_CNL
config SND_SOC_SOF_TIGERLAKE
tristate "SOF support for Tigerlake"
@ -248,7 +250,7 @@ config SND_SOC_SOF_ALDERLAKE
config SND_SOC_SOF_INTEL_MTL
tristate
select SND_SOC_SOF_HDA_COMMON
select SND_SOC_SOF_HDA_GENERIC
select SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE
select SND_SOC_SOF_IPC4
@ -264,9 +266,10 @@ config SND_SOC_SOF_METEORLAKE
config SND_SOC_SOF_INTEL_LNL
tristate
select SND_SOC_SOF_HDA_COMMON
select SND_SOC_SOF_HDA_GENERIC
select SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE
select SND_SOC_SOF_IPC4
select SND_SOC_SOF_INTEL_MTL
config SND_SOC_SOF_LUNARLAKE
tristate "SOF support for Lunarlake"
@ -280,6 +283,10 @@ config SND_SOC_SOF_LUNARLAKE
config SND_SOC_SOF_HDA_COMMON
tristate
config SND_SOC_SOF_HDA_GENERIC
tristate
select SND_SOC_SOF_HDA_COMMON
select SND_SOC_SOF_INTEL_COMMON
select SND_SOC_SOF_PCI_DEV
select SND_INTEL_DSP_CONFIG
@ -296,7 +303,7 @@ config SND_SOC_SOF_HDA_MLINK
This option is not user-selectable but automagically handled by
'select' statements at a higher level.
if SND_SOC_SOF_HDA_COMMON
if SND_SOC_SOF_HDA_GENERIC
config SND_SOC_SOF_HDA_LINK
bool "SOF support for HDA Links(HDA/HDMI)"
@ -316,7 +323,7 @@ config SND_SOC_SOF_HDA_AUDIO_CODEC
Say Y if you want to enable HDAudio codecs with SOF.
If unsure select "N".
endif ## SND_SOC_SOF_HDA_COMMON
endif ## SND_SOC_SOF_HDA_GENERIC
config SND_SOC_SOF_HDA_LINK_BASELINE
tristate

23
sound/soc/sof/intel/Makefile
View File

@ -3,12 +3,12 @@
snd-sof-acpi-intel-byt-objs := byt.o
snd-sof-acpi-intel-bdw-objs := bdw.o
snd-sof-intel-hda-common-objs := hda.o hda-loader.o hda-stream.o hda-trace.o \
snd-sof-intel-hda-common-objs := hda-loader.o hda-stream.o hda-trace.o \
hda-dsp.o hda-ipc.o hda-ctrl.o hda-pcm.o \
hda-dai.o hda-dai-ops.o hda-bus.o \
skl.o hda-loader-skl.o \
apl.o cnl.o tgl.o icl.o mtl.o lnl.o hda-common-ops.o \
telemetry.o
telemetry.o tracepoints.o
snd-sof-intel-hda-generic-objs := hda.o hda-common-ops.o
snd-sof-intel-hda-mlink-objs := hda-mlink.o
@ -22,17 +22,18 @@ obj-$(CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP) += snd-sof-intel-atom.o
obj-$(CONFIG_SND_SOC_SOF_BAYTRAIL) += snd-sof-acpi-intel-byt.o
obj-$(CONFIG_SND_SOC_SOF_BROADWELL) += snd-sof-acpi-intel-bdw.o
obj-$(CONFIG_SND_SOC_SOF_HDA_COMMON) += snd-sof-intel-hda-common.o
obj-$(CONFIG_SND_SOC_SOF_HDA_GENERIC) += snd-sof-intel-hda-generic.o
obj-$(CONFIG_SND_SOC_SOF_HDA_MLINK) += snd-sof-intel-hda-mlink.o
obj-$(CONFIG_SND_SOC_SOF_HDA) += snd-sof-intel-hda.o
snd-sof-pci-intel-tng-objs := pci-tng.o
snd-sof-pci-intel-skl-objs := pci-skl.o
snd-sof-pci-intel-apl-objs := pci-apl.o
snd-sof-pci-intel-cnl-objs := pci-cnl.o
snd-sof-pci-intel-icl-objs := pci-icl.o
snd-sof-pci-intel-tgl-objs := pci-tgl.o
snd-sof-pci-intel-mtl-objs := pci-mtl.o
snd-sof-pci-intel-lnl-objs := pci-lnl.o
snd-sof-pci-intel-skl-objs := pci-skl.o skl.o hda-loader-skl.o
snd-sof-pci-intel-apl-objs := pci-apl.o apl.o
snd-sof-pci-intel-cnl-objs := pci-cnl.o cnl.o
snd-sof-pci-intel-icl-objs := pci-icl.o icl.o
snd-sof-pci-intel-tgl-objs := pci-tgl.o tgl.o
snd-sof-pci-intel-mtl-objs := pci-mtl.o mtl.o
snd-sof-pci-intel-lnl-objs := pci-lnl.o lnl.o
obj-$(CONFIG_SND_SOC_SOF_MERRIFIELD) += snd-sof-pci-intel-tng.o
obj-$(CONFIG_SND_SOC_SOF_INTEL_SKL) += snd-sof-pci-intel-skl.o

3
sound/soc/sof/intel/apl.c
View File

@ -29,7 +29,6 @@ static const struct snd_sof_debugfs_map apl_dsp_debugfs[] = {
/* apollolake ops */
struct snd_sof_dsp_ops sof_apl_ops;
EXPORT_SYMBOL_NS(sof_apl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
int sof_apl_ops_init(struct snd_sof_dev *sdev)
{
@ -97,7 +96,6 @@ int sof_apl_ops_init(struct snd_sof_dev *sdev)
return 0;
};
EXPORT_SYMBOL_NS(sof_apl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc apl_chip_info = {
/* Apollolake */
@ -121,4 +119,3 @@ const struct sof_intel_dsp_desc apl_chip_info = {
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_1_5_PLUS,
};
EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

15
sound/soc/sof/intel/cnl.c
View File

@ -110,6 +110,7 @@ irqreturn_t cnl_ipc4_irq_thread(int irq, void *context)
return IRQ_HANDLED;
}
EXPORT_SYMBOL_NS(cnl_ipc4_irq_thread, SND_SOC_SOF_INTEL_CNL);
irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
{
@ -202,6 +203,7 @@ irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
return IRQ_HANDLED;
}
EXPORT_SYMBOL_NS(cnl_ipc_irq_thread, SND_SOC_SOF_INTEL_CNL);
static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
{
@ -284,6 +286,7 @@ int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
return 0;
}
EXPORT_SYMBOL_NS(cnl_ipc4_send_msg, SND_SOC_SOF_INTEL_CNL);
int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
{
@ -331,6 +334,7 @@ int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
return 0;
}
EXPORT_SYMBOL_NS(cnl_ipc_send_msg, SND_SOC_SOF_INTEL_CNL);
void cnl_ipc_dump(struct snd_sof_dev *sdev)
{
@ -351,6 +355,7 @@ void cnl_ipc_dump(struct snd_sof_dev *sdev)
"error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
hipcida, hipctdr, hipcctl);
}
EXPORT_SYMBOL_NS(cnl_ipc_dump, SND_SOC_SOF_INTEL_CNL);
void cnl_ipc4_dump(struct snd_sof_dev *sdev)
{
@ -372,10 +377,11 @@ void cnl_ipc4_dump(struct snd_sof_dev *sdev)
"Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n",
hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl);
}
EXPORT_SYMBOL_NS(cnl_ipc4_dump, SND_SOC_SOF_INTEL_CNL);
/* cannonlake ops */
struct snd_sof_dsp_ops sof_cnl_ops;
EXPORT_SYMBOL_NS(sof_cnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
EXPORT_SYMBOL_NS(sof_cnl_ops, SND_SOC_SOF_INTEL_CNL);
int sof_cnl_ops_init(struct snd_sof_dev *sdev)
{
@ -444,7 +450,7 @@ int sof_cnl_ops_init(struct snd_sof_dev *sdev)
return 0;
};
EXPORT_SYMBOL_NS(sof_cnl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
EXPORT_SYMBOL_NS(sof_cnl_ops_init, SND_SOC_SOF_INTEL_CNL);
const struct sof_intel_dsp_desc cnl_chip_info = {
/* Cannonlake */
@ -467,13 +473,13 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
.enable_sdw_irq = hda_common_enable_sdw_irq,
.check_sdw_irq = hda_common_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.sdw_process_wakeen = hda_sdw_process_wakeen_common,
.check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_1_8,
};
EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
/*
* JasperLake is technically derived from IceLake, and should be in
@ -503,10 +509,11 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
.enable_sdw_irq = hda_common_enable_sdw_irq,
.check_sdw_irq = hda_common_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.sdw_process_wakeen = hda_sdw_process_wakeen_common,
.check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_0,
};
EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_CNL);

2
sound/soc/sof/intel/hda-bus.c
View File

@ -94,6 +94,7 @@ void sof_hda_bus_init(struct snd_sof_dev *sdev, struct device *dev)
spin_lock_init(&bus->reg_lock);
#endif /* CONFIG_SND_SOC_SOF_HDA_LINK */
}
EXPORT_SYMBOL_NS(sof_hda_bus_init, SND_SOC_SOF_INTEL_HDA_COMMON);
void sof_hda_bus_exit(struct snd_sof_dev *sdev)
{
@ -103,3 +104,4 @@ void sof_hda_bus_exit(struct snd_sof_dev *sdev)
snd_hdac_ext_bus_exit(bus);
#endif
}
EXPORT_SYMBOL_NS(sof_hda_bus_exit, SND_SOC_SOF_INTEL_HDA_COMMON);

1
sound/soc/sof/intel/hda-common-ops.c
View File

@ -105,3 +105,4 @@ const struct snd_sof_dsp_ops sof_hda_common_ops = {
.dsp_arch_ops = &sof_xtensa_arch_ops,
};
EXPORT_SYMBOL_NS(sof_hda_common_ops, SND_SOC_SOF_INTEL_HDA_GENERIC);

10
sound/soc/sof/intel/hda-ctrl.c
View File

@ -128,6 +128,7 @@ int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev)
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_ctrl_get_caps, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable)
{
@ -136,6 +137,7 @@ void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable)
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
SOF_HDA_PPCTL_GPROCEN, val);
}
EXPORT_SYMBOL_NS(hda_dsp_ctrl_ppcap_enable, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable)
{
@ -144,6 +146,7 @@ void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable)
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
SOF_HDA_PPCTL_PIE, val);
}
EXPORT_SYMBOL_NS(hda_dsp_ctrl_ppcap_int_enable, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)
{
@ -178,6 +181,7 @@ int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_ctrl_clock_power_gating, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev)
{
@ -262,6 +266,7 @@ err:
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_ctrl_init_chip, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
{
@ -321,3 +326,8 @@ void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
bus->chip_init = false;
}
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK);
MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC);
MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915);

6
sound/soc/sof/intel/hda-dai.c
View File

@ -54,6 +54,7 @@ int hda_dai_config(struct snd_soc_dapm_widget *w, unsigned int flags,
return 0;
}
EXPORT_SYMBOL_NS(hda_dai_config, SND_SOC_SOF_INTEL_HDA_COMMON);
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_LINK)
@ -542,6 +543,7 @@ int sdw_hda_dai_hw_params(struct snd_pcm_substream *substream,
}
return 0;
}
EXPORT_SYMBOL_NS(sdw_hda_dai_hw_params, SND_SOC_SOF_INTEL_HDA_COMMON);
int sdw_hda_dai_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai,
@ -570,12 +572,14 @@ int sdw_hda_dai_hw_free(struct snd_pcm_substream *substream,
return 0;
}
EXPORT_SYMBOL_NS(sdw_hda_dai_hw_free, SND_SOC_SOF_INTEL_HDA_COMMON);
int sdw_hda_dai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *cpu_dai)
{
return hda_dai_trigger(substream, cmd, cpu_dai);
}
EXPORT_SYMBOL_NS(sdw_hda_dai_trigger, SND_SOC_SOF_INTEL_HDA_COMMON);
static int hda_dai_suspend(struct hdac_bus *bus)
{
@ -690,6 +694,7 @@ void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops)
ipc4_data->nhlt = intel_nhlt_init(sdev->dev);
}
}
EXPORT_SYMBOL_NS(hda_set_dai_drv_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_ops_free(struct snd_sof_dev *sdev)
{
@ -855,6 +860,7 @@ struct snd_soc_dai_driver skl_dai[] = {
},
#endif
};
EXPORT_SYMBOL_NS(skl_dai, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_dais_suspend(struct snd_sof_dev *sdev)
{

502
sound/soc/sof/intel/hda-dsp.c
View File

@ -20,11 +20,21 @@
#include <sound/hda_register.h>
#include <sound/hda-mlink.h>
#include <trace/events/sof_intel.h>
#include <sound/sof/xtensa.h>
#include "../sof-audio.h"
#include "../ops.h"
#include "hda.h"
#include "mtl.h"
#include "hda-ipc.h"
#define EXCEPT_MAX_HDR_SIZE 0x400
#define HDA_EXT_ROM_STATUS_SIZE 8
struct hda_dsp_msg_code {
u32 code;
const char *text;
};
static bool hda_enable_trace_D0I3_S0;
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444);
@ -32,6 +42,85 @@ MODULE_PARM_DESC(enable_trace_D0I3_S0,
"SOF HDA enable trace when the DSP is in D0I3 in S0");
#endif
static void hda_get_interfaces(struct snd_sof_dev *sdev, u32 *interface_mask)
{
const struct sof_intel_dsp_desc *chip;
chip = get_chip_info(sdev->pdata);
switch (chip->hw_ip_version) {
case SOF_INTEL_TANGIER:
case SOF_INTEL_BAYTRAIL:
case SOF_INTEL_BROADWELL:
interface_mask[SOF_DAI_DSP_ACCESS] = BIT(SOF_DAI_INTEL_SSP);
break;
case SOF_INTEL_CAVS_1_5:
case SOF_INTEL_CAVS_1_5_PLUS:
interface_mask[SOF_DAI_DSP_ACCESS] =
BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | BIT(SOF_DAI_INTEL_HDA);
interface_mask[SOF_DAI_HOST_ACCESS] = BIT(SOF_DAI_INTEL_HDA);
break;
case SOF_INTEL_CAVS_1_8:
case SOF_INTEL_CAVS_2_0:
case SOF_INTEL_CAVS_2_5:
case SOF_INTEL_ACE_1_0:
interface_mask[SOF_DAI_DSP_ACCESS] =
BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) |
BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH);
interface_mask[SOF_DAI_HOST_ACCESS] = BIT(SOF_DAI_INTEL_HDA);
break;
case SOF_INTEL_ACE_2_0:
interface_mask[SOF_DAI_DSP_ACCESS] =
BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) |
BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH);
/* all interfaces accessible without DSP */
interface_mask[SOF_DAI_HOST_ACCESS] =
interface_mask[SOF_DAI_DSP_ACCESS];
break;
default:
break;
}
}
u32 hda_get_interface_mask(struct snd_sof_dev *sdev)
{
u32 interface_mask[SOF_DAI_ACCESS_NUM] = { 0 };
hda_get_interfaces(sdev, interface_mask);
return interface_mask[sdev->dspless_mode_selected];
}
EXPORT_SYMBOL_NS(hda_get_interface_mask, SND_SOC_SOF_INTEL_HDA_COMMON);
bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type)
{
u32 interface_mask[SOF_DAI_ACCESS_NUM] = { 0 };
const struct sof_intel_dsp_desc *chip;
if (sdev->dspless_mode_selected)
return false;
hda_get_interfaces(sdev, interface_mask);
if (!(interface_mask[SOF_DAI_DSP_ACCESS] & BIT(dai_type)))
return false;
if (dai_type == SOF_DAI_INTEL_HDA)
return true;
switch (dai_type) {
case SOF_DAI_INTEL_SSP:
case SOF_DAI_INTEL_DMIC:
case SOF_DAI_INTEL_ALH:
chip = get_chip_info(sdev->pdata);
if (chip->hw_ip_version < SOF_INTEL_ACE_2_0)
return false;
return true;
default:
return false;
}
}
EXPORT_SYMBOL_NS(hda_is_chain_dma_supported, SND_SOC_SOF_INTEL_HDA_COMMON);
/*
* DSP Core control.
*/
@ -126,6 +215,7 @@ int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
/* set reset state */
return hda_dsp_core_reset_enter(sdev, core_mask);
}
EXPORT_SYMBOL_NS(hda_dsp_core_stall_reset, SND_SOC_SOF_INTEL_HDA_COMMON);
bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask)
{
@ -151,6 +241,7 @@ bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask)
return is_enable;
}
EXPORT_SYMBOL_NS(hda_dsp_core_is_enabled, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
{
@ -178,6 +269,7 @@ int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_core_run, SND_SOC_SOF_INTEL_HDA_COMMON);
/*
* Power Management.
@ -229,6 +321,7 @@ int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_core_power_up, SND_SOC_SOF_INTEL_HDA_COMMON);
static int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
{
@ -276,6 +369,7 @@ int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
return hda_dsp_core_run(sdev, core_mask);
}
EXPORT_SYMBOL_NS(hda_dsp_enable_core, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
unsigned int core_mask)
@ -316,6 +410,7 @@ int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_core_reset_power_down, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
{
@ -334,6 +429,7 @@ void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
}
EXPORT_SYMBOL_NS(hda_dsp_ipc_int_enable, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
{
@ -351,6 +447,7 @@ void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
}
EXPORT_SYMBOL_NS(hda_dsp_ipc_int_disable, SND_SOC_SOF_INTEL_HDA_COMMON);
static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
{
@ -634,6 +731,7 @@ int hda_dsp_set_power_state_ipc3(struct snd_sof_dev *sdev,
return hda_dsp_set_power_state(sdev, target_state);
}
EXPORT_SYMBOL_NS(hda_dsp_set_power_state_ipc3, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_set_power_state_ipc4(struct snd_sof_dev *sdev,
const struct sof_dsp_power_state *target_state)
@ -645,6 +743,7 @@ int hda_dsp_set_power_state_ipc4(struct snd_sof_dev *sdev,
return hda_dsp_set_power_state(sdev, target_state);
}
EXPORT_SYMBOL_NS(hda_dsp_set_power_state_ipc4, SND_SOC_SOF_INTEL_HDA_COMMON);
/*
* Audio DSP states may transform as below:-
@ -853,6 +952,7 @@ int hda_dsp_resume(struct snd_sof_dev *sdev)
return snd_sof_dsp_set_power_state(sdev, &target_state);
}
EXPORT_SYMBOL_NS(hda_dsp_resume, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
{
@ -868,6 +968,7 @@ int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
return snd_sof_dsp_set_power_state(sdev, &target_state);
}
EXPORT_SYMBOL_NS(hda_dsp_runtime_resume, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
{
@ -881,6 +982,7 @@ int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_runtime_idle, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
{
@ -902,6 +1004,7 @@ int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
return snd_sof_dsp_set_power_state(sdev, &target_state);
}
EXPORT_SYMBOL_NS(hda_dsp_runtime_suspend, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
{
@ -962,6 +1065,7 @@ int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
EXPORT_SYMBOL_NS(hda_dsp_suspend, SND_SOC_SOF_INTEL_HDA_COMMON);
static unsigned int hda_dsp_check_for_dma_streams(struct snd_sof_dev *sdev)
{
@ -1034,12 +1138,14 @@ int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev)
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_shutdown_dma_flush, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_shutdown(struct snd_sof_dev *sdev)
{
sdev->system_suspend_target = SOF_SUSPEND_S3;
return snd_sof_suspend(sdev->dev);
}
EXPORT_SYMBOL_NS(hda_dsp_shutdown, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
{
@ -1052,6 +1158,7 @@ int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_set_hw_params_upon_resume, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_dsp_d0i3_work(struct work_struct *work)
{
@ -1078,6 +1185,7 @@ void hda_dsp_d0i3_work(struct work_struct *work)
"error: failed to set DSP state %d substate %d\n",
target_state.state, target_state.substate);
}
EXPORT_SYMBOL_NS(hda_dsp_d0i3_work, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_core_get(struct snd_sof_dev *sdev, int core)
{
@ -1118,6 +1226,115 @@ power_down:
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_core_get, SND_SOC_SOF_INTEL_HDA_COMMON);
#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
{
struct sof_intel_hda_dev *hdev;
hdev = sdev->pdata->hw_pdata;
if (!hdev->sdw)
return;
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2,
HDA_DSP_REG_ADSPIC2_SNDW,
enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0);
}
EXPORT_SYMBOL_NS(hda_common_enable_sdw_irq, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
{
u32 interface_mask = hda_get_interface_mask(sdev);
const struct sof_intel_dsp_desc *chip;
if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
return;
chip = get_chip_info(sdev->pdata);
if (chip && chip->enable_sdw_irq)
chip->enable_sdw_irq(sdev, enable);
}
EXPORT_SYMBOL_NS(hda_sdw_int_enable, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev;
struct sdw_intel_ctx *ctx;
u32 caps;
hdev = sdev->pdata->hw_pdata;
ctx = hdev->sdw;
caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP);
caps &= SDW_SHIM_LCAP_LCOUNT_MASK;
/* Check HW supported vs property value */
if (caps < ctx->count) {
dev_err(sdev->dev,
"%s: BIOS master count %d is larger than hardware capabilities %d\n",
__func__, ctx->count, caps);
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL_NS(hda_sdw_check_lcount_common, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev;
struct sdw_intel_ctx *ctx;
struct hdac_bus *bus;
u32 slcount;
bus = sof_to_bus(sdev);
hdev = sdev->pdata->hw_pdata;
ctx = hdev->sdw;
slcount = hdac_bus_eml_get_count(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
/* Check HW supported vs property value */
if (slcount < ctx->count) {
dev_err(sdev->dev,
"%s: BIOS master count %d is larger than hardware capabilities %d\n",
__func__, ctx->count, slcount);
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL_NS(hda_sdw_check_lcount_ext, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_sdw_check_lcount(struct snd_sof_dev *sdev)
{
const struct sof_intel_dsp_desc *chip;
chip = get_chip_info(sdev->pdata);
if (chip && chip->read_sdw_lcount)
return chip->read_sdw_lcount(sdev);
return 0;
}
EXPORT_SYMBOL_NS(hda_sdw_check_lcount, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
{
u32 interface_mask = hda_get_interface_mask(sdev);
const struct sof_intel_dsp_desc *chip;
if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
return;
chip = get_chip_info(sdev->pdata);
if (chip && chip->sdw_process_wakeen)
chip->sdw_process_wakeen(sdev);
}
EXPORT_SYMBOL_NS(hda_sdw_process_wakeen, SND_SOC_SOF_INTEL_HDA_COMMON);
#endif
int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev)
{
@ -1126,3 +1343,288 @@ int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev)
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_disable_interrupts, SND_SOC_SOF_INTEL_HDA_COMMON);
static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = {
{HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
{HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
{HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
{HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
{HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
{HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
{HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
{HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
{HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
{HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"},
{HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
{HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
{HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
{HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
{HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
{HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"},
};
#define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state}
static const struct hda_dsp_msg_code cavs_fsr_rom_state_names[] = {
FSR_ROM_STATE_ENTRY(INIT),
FSR_ROM_STATE_ENTRY(INIT_DONE),
FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED),
FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED),
FSR_ROM_STATE_ENTRY(FW_FW_LOADED),
FSR_ROM_STATE_ENTRY(FW_ENTERED),
FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK),
FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET),
FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT),
FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE),
/* CSE states */
FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST),
FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED),
FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST),
FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED),
FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT),
FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1),
FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY),
FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL),
FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN),
};
static const struct hda_dsp_msg_code ace_fsr_rom_state_names[] = {
FSR_ROM_STATE_ENTRY(INIT),
FSR_ROM_STATE_ENTRY(INIT_DONE),
FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED),
FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED),
FSR_ROM_STATE_ENTRY(FW_FW_LOADED),
FSR_ROM_STATE_ENTRY(FW_ENTERED),
FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK),
FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET),
FSR_ROM_STATE_ENTRY(RESET_VECTOR_DONE),
FSR_ROM_STATE_ENTRY(PURGE_BOOT),
FSR_ROM_STATE_ENTRY(RESTORE_BOOT),
FSR_ROM_STATE_ENTRY(FW_ENTRY_POINT),
FSR_ROM_STATE_ENTRY(VALIDATE_PUB_KEY),
FSR_ROM_STATE_ENTRY(POWER_DOWN_HPSRAM),
FSR_ROM_STATE_ENTRY(POWER_DOWN_ULPSRAM),
FSR_ROM_STATE_ENTRY(POWER_UP_ULPSRAM_STACK),
FSR_ROM_STATE_ENTRY(POWER_UP_HPSRAM_DMA),
FSR_ROM_STATE_ENTRY(BEFORE_EP_POINTER_READ),
FSR_ROM_STATE_ENTRY(VALIDATE_MANIFEST),
FSR_ROM_STATE_ENTRY(VALIDATE_FW_MODULE),
FSR_ROM_STATE_ENTRY(PROTECT_IMR_REGION),
FSR_ROM_STATE_ENTRY(PUSH_MODEL_ROUTINE),
FSR_ROM_STATE_ENTRY(PULL_MODEL_ROUTINE),
FSR_ROM_STATE_ENTRY(VALIDATE_PKG_DIR),
FSR_ROM_STATE_ENTRY(VALIDATE_CPD),
FSR_ROM_STATE_ENTRY(VALIDATE_CSS_MAN_HEADER),
FSR_ROM_STATE_ENTRY(VALIDATE_BLOB_SVN),
FSR_ROM_STATE_ENTRY(VERIFY_IFWI_PARTITION),
FSR_ROM_STATE_ENTRY(REMOVE_ACCESS_CONTROL),
FSR_ROM_STATE_ENTRY(AUTH_BYPASS),
FSR_ROM_STATE_ENTRY(AUTH_ENABLED),
FSR_ROM_STATE_ENTRY(INIT_DMA),
FSR_ROM_STATE_ENTRY(PURGE_FW_ENTRY),
FSR_ROM_STATE_ENTRY(PURGE_FW_END),
FSR_ROM_STATE_ENTRY(CLEAN_UP_BSS_DONE),
FSR_ROM_STATE_ENTRY(IMR_RESTORE_ENTRY),
FSR_ROM_STATE_ENTRY(IMR_RESTORE_END),
FSR_ROM_STATE_ENTRY(FW_MANIFEST_IN_DMA_BUFF),
FSR_ROM_STATE_ENTRY(LOAD_CSE_MAN_TO_IMR),
FSR_ROM_STATE_ENTRY(LOAD_FW_MAN_TO_IMR),
FSR_ROM_STATE_ENTRY(LOAD_FW_CODE_TO_IMR),
FSR_ROM_STATE_ENTRY(FW_LOADING_DONE),
FSR_ROM_STATE_ENTRY(FW_CODE_LOADED),
FSR_ROM_STATE_ENTRY(VERIFY_IMAGE_TYPE),
FSR_ROM_STATE_ENTRY(AUTH_API_INIT),
FSR_ROM_STATE_ENTRY(AUTH_API_PROC),
FSR_ROM_STATE_ENTRY(AUTH_API_FIRST_BUSY),
FSR_ROM_STATE_ENTRY(AUTH_API_FIRST_RESULT),
FSR_ROM_STATE_ENTRY(AUTH_API_CLEANUP),
};
#define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state}
static const struct hda_dsp_msg_code fsr_bringup_state_names[] = {
FSR_BRINGUP_STATE_ENTRY(INIT),
FSR_BRINGUP_STATE_ENTRY(INIT_DONE),
FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD),
FSR_BRINGUP_STATE_ENTRY(UNPACK_START),
FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE),
FSR_BRINGUP_STATE_ENTRY(FW_ENTERED),
};
#define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state}
static const struct hda_dsp_msg_code fsr_wait_state_names[] = {
FSR_WAIT_STATE_ENTRY(IPC_BUSY),
FSR_WAIT_STATE_ENTRY(IPC_DONE),
FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION),
FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF),
FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL),
FSR_WAIT_STATE_ENTRY(CSE_CSR),
};
#define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod
static const char * const fsr_module_names[] = {
FSR_MODULE_NAME_ENTRY(ROM),
FSR_MODULE_NAME_ENTRY(ROM_BYP),
FSR_MODULE_NAME_ENTRY(BASE_FW),
FSR_MODULE_NAME_ENTRY(LP_BOOT),
FSR_MODULE_NAME_ENTRY(BRNGUP),
FSR_MODULE_NAME_ENTRY(ROM_EXT),
};
static const char *
hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code,
size_t array_size)
{
int i;
for (i = 0; i < array_size; i++) {
if (code == msg_code[i].code)
return msg_code[i].text;
}
return NULL;
}
void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level)
{
const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata);
const char *state_text, *error_text, *module_text;
u32 fsr, state, wait_state, module, error_code;
fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg);
state = FSR_TO_STATE_CODE(fsr);
wait_state = FSR_TO_WAIT_STATE_CODE(fsr);
module = FSR_TO_MODULE_CODE(fsr);
if (module > FSR_MOD_ROM_EXT)
module_text = "unknown";
else
module_text = fsr_module_names[module];
if (module == FSR_MOD_BRNGUP) {
state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names,
ARRAY_SIZE(fsr_bringup_state_names));
} else {
if (chip->hw_ip_version < SOF_INTEL_ACE_1_0)
state_text = hda_dsp_get_state_text(state,
cavs_fsr_rom_state_names,
ARRAY_SIZE(cavs_fsr_rom_state_names));
else
state_text = hda_dsp_get_state_text(state,
ace_fsr_rom_state_names,
ARRAY_SIZE(ace_fsr_rom_state_names));
}
/* not for us, must be generic sof message */
if (!state_text) {
dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr);
return;
}
if (wait_state) {
const char *wait_state_text;
wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names,
ARRAY_SIZE(fsr_wait_state_names));
if (!wait_state_text)
wait_state_text = "unknown";
dev_printk(level, sdev->dev,
"%#010x: module: %s, state: %s, waiting for: %s, %s\n",
fsr, module_text, state_text, wait_state_text,
fsr & FSR_HALTED ? "not running" : "running");
} else {
dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n",
fsr, module_text, state_text,
fsr & FSR_HALTED ? "not running" : "running");
}
error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4);
if (!error_code)
return;
error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts,
ARRAY_SIZE(hda_dsp_rom_fw_error_texts));
if (!error_text)
error_text = "unknown";
if (state == FSR_STATE_FW_ENTERED)
dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code,
error_text);
else
dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code,
error_text);
}
EXPORT_SYMBOL_NS(hda_dsp_get_state, SND_SOC_SOF_INTEL_HDA_COMMON);
static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
struct sof_ipc_dsp_oops_xtensa *xoops,
struct sof_ipc_panic_info *panic_info,
u32 *stack, size_t stack_words)
{
u32 offset = sdev->dsp_oops_offset;
/* first read registers */
sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
/* note: variable AR register array is not read */
/* then get panic info */
if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
xoops->arch_hdr.totalsize);
return;
}
offset += xoops->arch_hdr.totalsize;
sof_block_read(sdev, sdev->mmio_bar, offset,
panic_info, sizeof(*panic_info));
/* then get the stack */
offset += sizeof(*panic_info);
sof_block_read(sdev, sdev->mmio_bar, offset, stack,
stack_words * sizeof(u32));
}
/* dump the first 8 dwords representing the extended ROM status */
void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level,
u32 flags)
{
const struct sof_intel_dsp_desc *chip;
char msg[128];
int len = 0;
u32 value;
int i;
chip = get_chip_info(sdev->pdata);
for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) {
value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4);
len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value);
}
dev_printk(level, sdev->dev, "extended rom status: %s", msg);
}
void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
{
char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
struct sof_ipc_dsp_oops_xtensa xoops;
struct sof_ipc_panic_info panic_info;
u32 stack[HDA_DSP_STACK_DUMP_SIZE];
/* print ROM/FW status */
hda_dsp_get_state(sdev, level);
/* The firmware register dump only available with IPC3 */
if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC_TYPE_3) {
u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS);
u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);
hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
HDA_DSP_STACK_DUMP_SIZE);
sof_print_oops_and_stack(sdev, level, status, panic, &xoops,
&panic_info, stack, HDA_DSP_STACK_DUMP_SIZE);
} else {
hda_dsp_dump_ext_rom_status(sdev, level, flags);
}
}
EXPORT_SYMBOL_NS(hda_dsp_dump, SND_SOC_SOF_INTEL_HDA_COMMON);

115
sound/soc/sof/intel/hda-ipc.c
View File

@ -15,10 +15,16 @@
* Hardware interface for generic Intel audio DSP HDA IP
*/
#include <sound/hda_register.h>
#include <sound/sof/ipc4/header.h>
#include <trace/events/sof_intel.h>
#include "../ops.h"
#include "hda.h"
#include "telemetry.h"
EXPORT_TRACEPOINT_SYMBOL(sof_intel_ipc_firmware_initiated);
EXPORT_TRACEPOINT_SYMBOL(sof_intel_ipc_firmware_response);
EXPORT_TRACEPOINT_SYMBOL(sof_intel_hda_irq_ipc_check);
static void hda_dsp_ipc_host_done(struct snd_sof_dev *sdev)
{
@ -66,6 +72,7 @@ int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_ipc_send_msg, SND_SOC_SOF_INTEL_HDA_COMMON);
static inline bool hda_dsp_ipc4_pm_msg(u32 primary)
{
@ -92,6 +99,7 @@ void hda_dsp_ipc4_schedule_d0i3_work(struct sof_intel_hda_dev *hdev,
mod_delayed_work(system_wq, &hdev->d0i3_work,
msecs_to_jiffies(SOF_HDA_D0I3_WORK_DELAY_MS));
}
EXPORT_SYMBOL_NS(hda_dsp_ipc4_schedule_d0i3_work, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
{
@ -118,6 +126,7 @@ int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_ipc4_send_msg, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
{
@ -153,6 +162,7 @@ void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
snd_sof_ipc_get_reply(sdev);
}
}
EXPORT_SYMBOL_NS(hda_dsp_ipc_get_reply, SND_SOC_SOF_INTEL_HDA_COMMON);
irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context)
{
@ -235,6 +245,7 @@ irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context)
return IRQ_HANDLED;
}
EXPORT_SYMBOL_NS(hda_dsp_ipc4_irq_thread, SND_SOC_SOF_INTEL_HDA_COMMON);
/* IPC handler thread */
irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context)
@ -347,6 +358,7 @@ irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context)
return IRQ_HANDLED;
}
EXPORT_SYMBOL_NS(hda_dsp_ipc_irq_thread, SND_SOC_SOF_INTEL_HDA_COMMON);
/* Check if an IPC IRQ occurred */
bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
@ -380,16 +392,19 @@ bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
out:
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_check_ipc_irq, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
{
return HDA_DSP_MBOX_UPLINK_OFFSET;
}
EXPORT_SYMBOL_NS(hda_dsp_ipc_get_mailbox_offset, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
{
return SRAM_WINDOW_OFFSET(id);
}
EXPORT_SYMBOL_NS(hda_dsp_ipc_get_window_offset, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_ipc_msg_data(struct snd_sof_dev *sdev,
struct snd_sof_pcm_stream *sps,
@ -415,6 +430,7 @@ int hda_ipc_msg_data(struct snd_sof_dev *sdev,
return 0;
}
EXPORT_SYMBOL_NS(hda_ipc_msg_data, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_set_stream_data_offset(struct snd_sof_dev *sdev,
struct snd_sof_pcm_stream *sps,
@ -439,3 +455,102 @@ int hda_set_stream_data_offset(struct snd_sof_dev *sdev,
return 0;
}
EXPORT_SYMBOL_NS(hda_set_stream_data_offset, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
{
char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
/* print ROM/FW status */
hda_dsp_get_state(sdev, level);
if (flags & SOF_DBG_DUMP_REGS)
sof_ipc4_intel_dump_telemetry_state(sdev, flags);
else
hda_dsp_dump_ext_rom_status(sdev, level, flags);
}
EXPORT_SYMBOL_NS(hda_ipc4_dsp_dump, SND_SOC_SOF_INTEL_HDA_COMMON);
bool hda_check_ipc_irq(struct snd_sof_dev *sdev)
{
const struct sof_intel_dsp_desc *chip;
chip = get_chip_info(sdev->pdata);
if (chip && chip->check_ipc_irq)
return chip->check_ipc_irq(sdev);
return false;
}
EXPORT_SYMBOL_NS(hda_check_ipc_irq, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
{
u32 adspis;
u32 intsts;
u32 intctl;
u32 ppsts;
u8 rirbsts;
/* read key IRQ stats and config registers */
adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS);
dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
intsts, intctl, rirbsts);
dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis);
}
EXPORT_SYMBOL_NS(hda_ipc_irq_dump, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_ipc_dump(struct snd_sof_dev *sdev)
{
u32 hipcie;
u32 hipct;
u32 hipcctl;
hda_ipc_irq_dump(sdev);
/* read IPC status */
hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
/* dump the IPC regs */
/* TODO: parse the raw msg */
dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
hipcie, hipct, hipcctl);
}
EXPORT_SYMBOL_NS(hda_ipc_dump, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_ipc4_dump(struct snd_sof_dev *sdev)
{
u32 hipci, hipcie, hipct, hipcte, hipcctl;
hda_ipc_irq_dump(sdev);
hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI);
hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE);
hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
/* dump the IPC regs */
/* TODO: parse the raw msg */
dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n",
hipci, hipcie, hipct, hipcte, hipcctl);
}
EXPORT_SYMBOL_NS(hda_ipc4_dump, SND_SOC_SOF_INTEL_HDA_COMMON);
bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
u32 val;
val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req);
return !!(val & chip->ipc_req_mask);
}
EXPORT_SYMBOL_NS(hda_ipc4_tx_is_busy, SND_SOC_SOF_INTEL_HDA_COMMON);

45
sound/soc/sof/intel/hda-loader.c
View File

@ -15,7 +15,6 @@
* Hardware interface for HDA DSP code loader
*/
#include <linux/debugfs.h>
#include <linux/firmware.h>
#include <sound/hdaudio_ext.h>
#include <sound/hda_register.h>
@ -220,6 +219,7 @@ err:
kfree(dump_msg);
return ret;
}
EXPORT_SYMBOL_NS(cl_dsp_init, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_cl_trigger(struct device *dev, struct hdac_ext_stream *hext_stream, int cmd)
{
@ -394,6 +394,7 @@ int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev)
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_cl_boot_firmware_iccmax, SND_SOC_SOF_INTEL_CNL);
static int hda_dsp_boot_imr(struct snd_sof_dev *sdev)
{
@ -547,6 +548,7 @@ cleanup:
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_cl_boot_firmware, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev,
struct sof_ipc4_fw_library *fw_lib, bool reload)
@ -650,45 +652,7 @@ cleanup:
return ret;
}
/* pre fw run operations */
int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
{
/* disable clock gating and power gating */
return hda_dsp_ctrl_clock_power_gating(sdev, false);
}
/* post fw run operations */
int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
{
int ret;
if (sdev->first_boot) {
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
ret = hda_sdw_startup(sdev);
if (ret < 0) {
dev_err(sdev->dev,
"error: could not startup SoundWire links\n");
return ret;
}
/* Check if IMR boot is usable */
if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) &&
(sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT ||
sdev->pdata->ipc_type == SOF_IPC_TYPE_4)) {
hdev->imrboot_supported = true;
debugfs_create_bool("skip_imr_boot",
0644, sdev->debugfs_root,
&hdev->skip_imr_boot);
}
}
hda_sdw_int_enable(sdev, true);
/* re-enable clock gating and power gating */
return hda_dsp_ctrl_clock_power_gating(sdev, true);
}
EXPORT_SYMBOL_NS(hda_dsp_ipc4_load_library, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
const struct sof_ext_man_elem_header *hdr)
@ -727,3 +691,4 @@ int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_ext_man_get_cavs_config_data, SND_SOC_SOF_INTEL_HDA_COMMON);

6
sound/soc/sof/intel/hda-pcm.c
View File

@ -142,6 +142,7 @@ int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_pcm_hw_params, SND_SOC_SOF_INTEL_HDA_COMMON);
/* update SPIB register with appl position */
int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream)
@ -164,6 +165,7 @@ int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substrea
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_pcm_ack, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream, int cmd)
@ -173,6 +175,7 @@ int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
return hda_dsp_stream_trigger(sdev, hext_stream, cmd);
}
EXPORT_SYMBOL_NS(hda_dsp_pcm_trigger, SND_SOC_SOF_INTEL_HDA_COMMON);
snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream)
@ -204,6 +207,7 @@ found:
trace_sof_intel_hda_dsp_pcm(sdev, hstream, substream, pos);
return pos;
}
EXPORT_SYMBOL_NS(hda_dsp_pcm_pointer, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream)
@ -292,6 +296,7 @@ int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_pcm_open, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream)
@ -311,3 +316,4 @@ int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
substream->runtime->private_data = NULL;
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_pcm_close, SND_SOC_SOF_INTEL_HDA_COMMON);

2
sound/soc/sof/intel/hda-probes.c
View File

@ -139,10 +139,12 @@ int hda_probes_register(struct snd_sof_dev *sdev)
return sof_client_dev_register(sdev, "hda-probes", 0, &hda_probes_ops,
sizeof(hda_probes_ops));
}
EXPORT_SYMBOL_NS(hda_probes_register, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_probes_unregister(struct snd_sof_dev *sdev)
{
sof_client_dev_unregister(sdev, "hda-probes", 0);
}
EXPORT_SYMBOL_NS(hda_probes_unregister, SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_SOF_CLIENT);

13
sound/soc/sof/intel/hda-stream.c
View File

@ -24,6 +24,11 @@
#include "../ipc4-priv.h"
#include "hda.h"
int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS;
module_param_named(position_quirk, sof_hda_position_quirk, int, 0444);
MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk");
EXPORT_SYMBOL_NS(sof_hda_position_quirk, SND_SOC_SOF_INTEL_HDA_COMMON);
#define HDA_LTRP_GB_VALUE_US 95
static inline const char *hda_hstream_direction_str(struct hdac_stream *hstream)
@ -709,6 +714,7 @@ int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_stream_hw_free, SND_SOC_SOF_INTEL_HDA_COMMON);
bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev)
{
@ -731,6 +737,7 @@ bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev)
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_check_stream_irq, SND_SOC_SOF_INTEL_HDA_COMMON);
static void
hda_dsp_compr_bytes_transferred(struct hdac_stream *hstream, int direction)
@ -827,6 +834,7 @@ irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context)
return IRQ_HANDLED;
}
EXPORT_SYMBOL_NS(hda_dsp_stream_threaded_handler, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_stream_init(struct snd_sof_dev *sdev)
{
@ -964,6 +972,7 @@ int hda_dsp_stream_init(struct snd_sof_dev *sdev)
return 0;
}
EXPORT_SYMBOL_NS(hda_dsp_stream_init, SND_SOC_SOF_INTEL_HDA_COMMON);
void hda_dsp_stream_free(struct snd_sof_dev *sdev)
{
@ -993,6 +1002,7 @@ void hda_dsp_stream_free(struct snd_sof_dev *sdev)
devm_kfree(sdev->dev, hda_stream);
}
}
EXPORT_SYMBOL_NS(hda_dsp_stream_free, SND_SOC_SOF_INTEL_HDA_COMMON);
snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
int direction, bool can_sleep)
@ -1079,6 +1089,7 @@ snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
return pos;
}
EXPORT_SYMBOL_NS(hda_dsp_stream_get_position, SND_SOC_SOF_INTEL_HDA_COMMON);
#define merge_u64(u32_u, u32_l) (((u64)(u32_u) << 32) | (u32_l))
@ -1118,6 +1129,7 @@ u64 hda_dsp_get_stream_llp(struct snd_sof_dev *sdev,
return merge_u64(llp_u, llp_l);
}
EXPORT_SYMBOL_NS(hda_dsp_get_stream_llp, SND_SOC_SOF_INTEL_HDA_COMMON);
/**
* hda_dsp_get_stream_ldp - Retrieve the LDP (Linear DMA Position) of the stream
@ -1149,3 +1161,4 @@ u64 hda_dsp_get_stream_ldp(struct snd_sof_dev *sdev,
return ((u64)ldp_u << 32) | ldp_l;
}
EXPORT_SYMBOL_NS(hda_dsp_get_stream_ldp, SND_SOC_SOF_INTEL_HDA_COMMON);

3
sound/soc/sof/intel/hda-trace.c
View File

@ -68,6 +68,7 @@ int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_trace_init, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_trace_release(struct snd_sof_dev *sdev)
{
@ -86,6 +87,7 @@ int hda_dsp_trace_release(struct snd_sof_dev *sdev)
dev_dbg(sdev->dev, "DMA trace stream is not opened!\n");
return -ENODEV;
}
EXPORT_SYMBOL_NS(hda_dsp_trace_release, SND_SOC_SOF_INTEL_HDA_COMMON);
int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd)
{
@ -93,3 +95,4 @@ int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd)
return hda_dsp_stream_trigger(sdev, hda->dtrace_stream, cmd);
}
EXPORT_SYMBOL_NS(hda_dsp_trace_trigger, SND_SOC_SOF_INTEL_HDA_COMMON);

605
sound/soc/sof/intel/hda.c
View File

@ -34,10 +34,7 @@
#include "../ops.h"
#include "../ipc4-topology.h"
#include "hda.h"
#include "telemetry.h"
#include "mtl.h"
#define CREATE_TRACE_POINTS
#include <trace/events/sof_intel.h>
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
@ -47,86 +44,6 @@
/* platform specific devices */
#include "shim.h"
#define EXCEPT_MAX_HDR_SIZE 0x400
#define HDA_EXT_ROM_STATUS_SIZE 8
static void hda_get_interfaces(struct snd_sof_dev *sdev, u32 *interface_mask)
{
const struct sof_intel_dsp_desc *chip;
chip = get_chip_info(sdev->pdata);
switch (chip->hw_ip_version) {
case SOF_INTEL_TANGIER:
case SOF_INTEL_BAYTRAIL:
case SOF_INTEL_BROADWELL:
interface_mask[SOF_DAI_DSP_ACCESS] = BIT(SOF_DAI_INTEL_SSP);
break;
case SOF_INTEL_CAVS_1_5:
case SOF_INTEL_CAVS_1_5_PLUS:
interface_mask[SOF_DAI_DSP_ACCESS] =
BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | BIT(SOF_DAI_INTEL_HDA);
interface_mask[SOF_DAI_HOST_ACCESS] = BIT(SOF_DAI_INTEL_HDA);
break;
case SOF_INTEL_CAVS_1_8:
case SOF_INTEL_CAVS_2_0:
case SOF_INTEL_CAVS_2_5:
case SOF_INTEL_ACE_1_0:
interface_mask[SOF_DAI_DSP_ACCESS] =
BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) |
BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH);
interface_mask[SOF_DAI_HOST_ACCESS] = BIT(SOF_DAI_INTEL_HDA);
break;
case SOF_INTEL_ACE_2_0:
interface_mask[SOF_DAI_DSP_ACCESS] =
BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) |
BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH);
/* all interfaces accessible without DSP */
interface_mask[SOF_DAI_HOST_ACCESS] =
interface_mask[SOF_DAI_DSP_ACCESS];
break;
default:
break;
}
}
static u32 hda_get_interface_mask(struct snd_sof_dev *sdev)
{
u32 interface_mask[SOF_DAI_ACCESS_NUM] = { 0 };
hda_get_interfaces(sdev, interface_mask);
return interface_mask[sdev->dspless_mode_selected];
}
bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type)
{
u32 interface_mask[SOF_DAI_ACCESS_NUM] = { 0 };
const struct sof_intel_dsp_desc *chip;
if (sdev->dspless_mode_selected)
return false;
hda_get_interfaces(sdev, interface_mask);
if (!(interface_mask[SOF_DAI_DSP_ACCESS] & BIT(dai_type)))
return false;
if (dai_type == SOF_DAI_INTEL_HDA)
return true;
switch (dai_type) {
case SOF_DAI_INTEL_SSP:
case SOF_DAI_INTEL_DMIC:
case SOF_DAI_INTEL_ALH:
chip = get_chip_info(sdev->pdata);
if (chip->hw_ip_version < SOF_INTEL_ACE_2_0)
return false;
return true;
default:
return false;
}
}
#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
/*
@ -210,33 +127,6 @@ static struct sdw_intel_ops sdw_ace2x_callback = {
.trigger = sdw_ace2x_trigger,
};
void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
{
struct sof_intel_hda_dev *hdev;
hdev = sdev->pdata->hw_pdata;
if (!hdev->sdw)
return;
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2,
HDA_DSP_REG_ADSPIC2_SNDW,
enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0);
}
void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
{
u32 interface_mask = hda_get_interface_mask(sdev);
const struct sof_intel_dsp_desc *chip;
if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
return;
chip = get_chip_info(sdev->pdata);
if (chip && chip->enable_sdw_irq)
chip->enable_sdw_irq(sdev, enable);
}
static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
{
u32 interface_mask = hda_get_interface_mask(sdev);
@ -328,65 +218,6 @@ static int hda_sdw_probe(struct snd_sof_dev *sdev)
return 0;
}
int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev;
struct sdw_intel_ctx *ctx;
u32 caps;
hdev = sdev->pdata->hw_pdata;
ctx = hdev->sdw;
caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP);
caps &= SDW_SHIM_LCAP_LCOUNT_MASK;
/* Check HW supported vs property value */
if (caps < ctx->count) {
dev_err(sdev->dev,
"%s: BIOS master count %d is larger than hardware capabilities %d\n",
__func__, ctx->count, caps);
return -EINVAL;
}
return 0;
}
int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev;
struct sdw_intel_ctx *ctx;
struct hdac_bus *bus;
u32 slcount;
bus = sof_to_bus(sdev);
hdev = sdev->pdata->hw_pdata;
ctx = hdev->sdw;
slcount = hdac_bus_eml_get_count(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
/* Check HW supported vs property value */
if (slcount < ctx->count) {
dev_err(sdev->dev,
"%s: BIOS master count %d is larger than hardware capabilities %d\n",
__func__, ctx->count, slcount);
return -EINVAL;
}
return 0;
}
static int hda_sdw_check_lcount(struct snd_sof_dev *sdev)
{
const struct sof_intel_dsp_desc *chip;
chip = get_chip_info(sdev->pdata);
if (chip && chip->read_sdw_lcount)
return chip->read_sdw_lcount(sdev);
return 0;
}
int hda_sdw_startup(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev;
@ -407,6 +238,7 @@ int hda_sdw_startup(struct snd_sof_dev *sdev)
return sdw_intel_startup(hdev->sdw);
}
EXPORT_SYMBOL_NS(hda_sdw_startup, SND_SOC_SOF_INTEL_HDA_GENERIC);
static int hda_sdw_exit(struct snd_sof_dev *sdev)
{
@ -448,6 +280,7 @@ bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
out:
return ret;
}
EXPORT_SYMBOL_NS(hda_common_check_sdw_irq, SND_SOC_SOF_INTEL_HDA_GENERIC);
static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
{
@ -481,6 +314,7 @@ bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev)
return false;
}
EXPORT_SYMBOL_NS(hda_sdw_check_wakeen_irq_common, SND_SOC_SOF_INTEL_HDA_GENERIC);
static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
{
@ -497,7 +331,7 @@ static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
return false;
}
void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev)
{
u32 interface_mask = hda_get_interface_mask(sdev);
struct sof_intel_hda_dev *hdev;
@ -511,6 +345,7 @@ void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
sdw_intel_process_wakeen_event(hdev->sdw);
}
EXPORT_SYMBOL_NS(hda_sdw_process_wakeen_common, SND_SOC_SOF_INTEL_HDA_GENERIC);
#else /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */
static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
@ -545,15 +380,50 @@ static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
#endif /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */
/* pre fw run operations */
int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
{
/* disable clock gating and power gating */
return hda_dsp_ctrl_clock_power_gating(sdev, false);
}
/* post fw run operations */
int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
{
int ret;
if (sdev->first_boot) {
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
ret = hda_sdw_startup(sdev);
if (ret < 0) {
dev_err(sdev->dev,
"error: could not startup SoundWire links\n");
return ret;
}
/* Check if IMR boot is usable */
if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) &&
(sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT ||
sdev->pdata->ipc_type == SOF_IPC_TYPE_4)) {
hdev->imrboot_supported = true;
debugfs_create_bool("skip_imr_boot",
0644, sdev->debugfs_root,
&hdev->skip_imr_boot);
}
}
hda_sdw_int_enable(sdev, true);
/* re-enable clock gating and power gating */
return hda_dsp_ctrl_clock_power_gating(sdev, true);
}
EXPORT_SYMBOL_NS(hda_dsp_post_fw_run, SND_SOC_SOF_INTEL_HDA_GENERIC);
/*
* Debug
*/
struct hda_dsp_msg_code {
u32 code;
const char *text;
};
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
static bool hda_use_msi = true;
module_param_named(use_msi, hda_use_msi, bool, 0444);
@ -562,10 +432,6 @@ MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode");
#define hda_use_msi (1)
#endif
int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS;
module_param_named(position_quirk, sof_hda_position_quirk, int, 0444);
MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk");
static char *hda_model;
module_param(hda_model, charp, 0444);
MODULE_PARM_DESC(hda_model, "Use the given HDA board model.");
@ -578,380 +444,6 @@ static int mclk_id_override = -1;
module_param_named(mclk_id, mclk_id_override, int, 0444);
MODULE_PARM_DESC(mclk_id, "SOF SSP mclk_id");
static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = {
{HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
{HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
{HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
{HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
{HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
{HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
{HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
{HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
{HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
{HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"},
{HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
{HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
{HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
{HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
{HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
{HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"},
};
#define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state}
static const struct hda_dsp_msg_code cavs_fsr_rom_state_names[] = {
FSR_ROM_STATE_ENTRY(INIT),
FSR_ROM_STATE_ENTRY(INIT_DONE),
FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED),
FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED),
FSR_ROM_STATE_ENTRY(FW_FW_LOADED),
FSR_ROM_STATE_ENTRY(FW_ENTERED),
FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK),
FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET),
FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT),
FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE),
/* CSE states */
FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST),
FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED),
FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST),
FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED),
FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT),
FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1),
FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY),
FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL),
FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN),
};
static const struct hda_dsp_msg_code ace_fsr_rom_state_names[] = {
FSR_ROM_STATE_ENTRY(INIT),
FSR_ROM_STATE_ENTRY(INIT_DONE),
FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED),
FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED),
FSR_ROM_STATE_ENTRY(FW_FW_LOADED),
FSR_ROM_STATE_ENTRY(FW_ENTERED),
FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK),
FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET),
FSR_ROM_STATE_ENTRY(RESET_VECTOR_DONE),
FSR_ROM_STATE_ENTRY(PURGE_BOOT),
FSR_ROM_STATE_ENTRY(RESTORE_BOOT),
FSR_ROM_STATE_ENTRY(FW_ENTRY_POINT),
FSR_ROM_STATE_ENTRY(VALIDATE_PUB_KEY),
FSR_ROM_STATE_ENTRY(POWER_DOWN_HPSRAM),
FSR_ROM_STATE_ENTRY(POWER_DOWN_ULPSRAM),
FSR_ROM_STATE_ENTRY(POWER_UP_ULPSRAM_STACK),
FSR_ROM_STATE_ENTRY(POWER_UP_HPSRAM_DMA),
FSR_ROM_STATE_ENTRY(BEFORE_EP_POINTER_READ),
FSR_ROM_STATE_ENTRY(VALIDATE_MANIFEST),
FSR_ROM_STATE_ENTRY(VALIDATE_FW_MODULE),
FSR_ROM_STATE_ENTRY(PROTECT_IMR_REGION),
FSR_ROM_STATE_ENTRY(PUSH_MODEL_ROUTINE),
FSR_ROM_STATE_ENTRY(PULL_MODEL_ROUTINE),
FSR_ROM_STATE_ENTRY(VALIDATE_PKG_DIR),
FSR_ROM_STATE_ENTRY(VALIDATE_CPD),
FSR_ROM_STATE_ENTRY(VALIDATE_CSS_MAN_HEADER),
FSR_ROM_STATE_ENTRY(VALIDATE_BLOB_SVN),
FSR_ROM_STATE_ENTRY(VERIFY_IFWI_PARTITION),
FSR_ROM_STATE_ENTRY(REMOVE_ACCESS_CONTROL),
FSR_ROM_STATE_ENTRY(AUTH_BYPASS),
FSR_ROM_STATE_ENTRY(AUTH_ENABLED),
FSR_ROM_STATE_ENTRY(INIT_DMA),
FSR_ROM_STATE_ENTRY(PURGE_FW_ENTRY),
FSR_ROM_STATE_ENTRY(PURGE_FW_END),
FSR_ROM_STATE_ENTRY(CLEAN_UP_BSS_DONE),
FSR_ROM_STATE_ENTRY(IMR_RESTORE_ENTRY),
FSR_ROM_STATE_ENTRY(IMR_RESTORE_END),
FSR_ROM_STATE_ENTRY(FW_MANIFEST_IN_DMA_BUFF),
FSR_ROM_STATE_ENTRY(LOAD_CSE_MAN_TO_IMR),
FSR_ROM_STATE_ENTRY(LOAD_FW_MAN_TO_IMR),
FSR_ROM_STATE_ENTRY(LOAD_FW_CODE_TO_IMR),
FSR_ROM_STATE_ENTRY(FW_LOADING_DONE),
FSR_ROM_STATE_ENTRY(FW_CODE_LOADED),
FSR_ROM_STATE_ENTRY(VERIFY_IMAGE_TYPE),
FSR_ROM_STATE_ENTRY(AUTH_API_INIT),
FSR_ROM_STATE_ENTRY(AUTH_API_PROC),
FSR_ROM_STATE_ENTRY(AUTH_API_FIRST_BUSY),
FSR_ROM_STATE_ENTRY(AUTH_API_FIRST_RESULT),
FSR_ROM_STATE_ENTRY(AUTH_API_CLEANUP),
};
#define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state}
static const struct hda_dsp_msg_code fsr_bringup_state_names[] = {
FSR_BRINGUP_STATE_ENTRY(INIT),
FSR_BRINGUP_STATE_ENTRY(INIT_DONE),
FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD),
FSR_BRINGUP_STATE_ENTRY(UNPACK_START),
FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE),
FSR_BRINGUP_STATE_ENTRY(FW_ENTERED),
};
#define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state}
static const struct hda_dsp_msg_code fsr_wait_state_names[] = {
FSR_WAIT_STATE_ENTRY(IPC_BUSY),
FSR_WAIT_STATE_ENTRY(IPC_DONE),
FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION),
FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF),
FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL),
FSR_WAIT_STATE_ENTRY(CSE_CSR),
};
#define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod
static const char * const fsr_module_names[] = {
FSR_MODULE_NAME_ENTRY(ROM),
FSR_MODULE_NAME_ENTRY(ROM_BYP),
FSR_MODULE_NAME_ENTRY(BASE_FW),
FSR_MODULE_NAME_ENTRY(LP_BOOT),
FSR_MODULE_NAME_ENTRY(BRNGUP),
FSR_MODULE_NAME_ENTRY(ROM_EXT),
};
static const char *
hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code,
size_t array_size)
{
int i;
for (i = 0; i < array_size; i++) {
if (code == msg_code[i].code)
return msg_code[i].text;
}
return NULL;
}
void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level)
{
const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata);
const char *state_text, *error_text, *module_text;
u32 fsr, state, wait_state, module, error_code;
fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg);
state = FSR_TO_STATE_CODE(fsr);
wait_state = FSR_TO_WAIT_STATE_CODE(fsr);
module = FSR_TO_MODULE_CODE(fsr);
if (module > FSR_MOD_ROM_EXT)
module_text = "unknown";
else
module_text = fsr_module_names[module];
if (module == FSR_MOD_BRNGUP) {
state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names,
ARRAY_SIZE(fsr_bringup_state_names));
} else {
if (chip->hw_ip_version < SOF_INTEL_ACE_1_0)
state_text = hda_dsp_get_state_text(state,
cavs_fsr_rom_state_names,
ARRAY_SIZE(cavs_fsr_rom_state_names));
else
state_text = hda_dsp_get_state_text(state,
ace_fsr_rom_state_names,
ARRAY_SIZE(ace_fsr_rom_state_names));
}
/* not for us, must be generic sof message */
if (!state_text) {
dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr);
return;
}
if (wait_state) {
const char *wait_state_text;
wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names,
ARRAY_SIZE(fsr_wait_state_names));
if (!wait_state_text)
wait_state_text = "unknown";
dev_printk(level, sdev->dev,
"%#010x: module: %s, state: %s, waiting for: %s, %s\n",
fsr, module_text, state_text, wait_state_text,
fsr & FSR_HALTED ? "not running" : "running");
} else {
dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n",
fsr, module_text, state_text,
fsr & FSR_HALTED ? "not running" : "running");
}
error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4);
if (!error_code)
return;
error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts,
ARRAY_SIZE(hda_dsp_rom_fw_error_texts));
if (!error_text)
error_text = "unknown";
if (state == FSR_STATE_FW_ENTERED)
dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code,
error_text);
else
dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code,
error_text);
}
static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
struct sof_ipc_dsp_oops_xtensa *xoops,
struct sof_ipc_panic_info *panic_info,
u32 *stack, size_t stack_words)
{
u32 offset = sdev->dsp_oops_offset;
/* first read registers */
sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
/* note: variable AR register array is not read */
/* then get panic info */
if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
xoops->arch_hdr.totalsize);
return;
}
offset += xoops->arch_hdr.totalsize;
sof_block_read(sdev, sdev->mmio_bar, offset,
panic_info, sizeof(*panic_info));
/* then get the stack */
offset += sizeof(*panic_info);
sof_block_read(sdev, sdev->mmio_bar, offset, stack,
stack_words * sizeof(u32));
}
/* dump the first 8 dwords representing the extended ROM status */
static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level,
u32 flags)
{
const struct sof_intel_dsp_desc *chip;
char msg[128];
int len = 0;
u32 value;
int i;
chip = get_chip_info(sdev->pdata);
for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) {
value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4);
len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value);
}
dev_printk(level, sdev->dev, "extended rom status: %s", msg);
}
void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
{
char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
struct sof_ipc_dsp_oops_xtensa xoops;
struct sof_ipc_panic_info panic_info;
u32 stack[HDA_DSP_STACK_DUMP_SIZE];
/* print ROM/FW status */
hda_dsp_get_state(sdev, level);
/* The firmware register dump only available with IPC3 */
if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC_TYPE_3) {
u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS);
u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);
hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
HDA_DSP_STACK_DUMP_SIZE);
sof_print_oops_and_stack(sdev, level, status, panic, &xoops,
&panic_info, stack, HDA_DSP_STACK_DUMP_SIZE);
} else {
hda_dsp_dump_ext_rom_status(sdev, level, flags);
}
}
void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
{
char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
/* print ROM/FW status */
hda_dsp_get_state(sdev, level);
if (flags & SOF_DBG_DUMP_REGS)
sof_ipc4_intel_dump_telemetry_state(sdev, flags);
else
hda_dsp_dump_ext_rom_status(sdev, level, flags);
}
static bool hda_check_ipc_irq(struct snd_sof_dev *sdev)
{
const struct sof_intel_dsp_desc *chip;
chip = get_chip_info(sdev->pdata);
if (chip && chip->check_ipc_irq)
return chip->check_ipc_irq(sdev);
return false;
}
void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
{
u32 adspis;
u32 intsts;
u32 intctl;
u32 ppsts;
u8 rirbsts;
/* read key IRQ stats and config registers */
adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS);
dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
intsts, intctl, rirbsts);
dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis);
}
void hda_ipc_dump(struct snd_sof_dev *sdev)
{
u32 hipcie;
u32 hipct;
u32 hipcctl;
hda_ipc_irq_dump(sdev);
/* read IPC status */
hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
/* dump the IPC regs */
/* TODO: parse the raw msg */
dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
hipcie, hipct, hipcctl);
}
void hda_ipc4_dump(struct snd_sof_dev *sdev)
{
u32 hipci, hipcie, hipct, hipcte, hipcctl;
hda_ipc_irq_dump(sdev);
hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI);
hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE);
hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
/* dump the IPC regs */
/* TODO: parse the raw msg */
dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n",
hipci, hipcie, hipct, hipcte, hipcctl);
}
bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
u32 val;
val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req);
return !!(val & chip->ipc_req_mask);
}
static int hda_init(struct snd_sof_dev *sdev)
{
struct hda_bus *hbus;
@ -1315,6 +807,7 @@ int hda_dsp_probe_early(struct snd_sof_dev *sdev)
err:
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_probe_early, SND_SOC_SOF_INTEL_HDA_GENERIC);
int hda_dsp_probe(struct snd_sof_dev *sdev)
{
@ -1471,6 +964,7 @@ hdac_bus_unmap:
return ret;
}
EXPORT_SYMBOL_NS(hda_dsp_probe, SND_SOC_SOF_INTEL_HDA_GENERIC);
void hda_dsp_remove(struct snd_sof_dev *sdev)
{
@ -1524,6 +1018,7 @@ skip_disable_dsp:
if (!sdev->dspless_mode_selected)
iounmap(sdev->bar[HDA_DSP_BAR]);
}
EXPORT_SYMBOL_NS(hda_dsp_remove, SND_SOC_SOF_INTEL_HDA_GENERIC);
void hda_dsp_remove_late(struct snd_sof_dev *sdev)
{
@ -1539,6 +1034,7 @@ int hda_power_down_dsp(struct snd_sof_dev *sdev)
return hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
}
EXPORT_SYMBOL_NS(hda_power_down_dsp, SND_SOC_SOF_INTEL_HDA_GENERIC);
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
static void hda_generic_machine_select(struct snd_sof_dev *sdev,
@ -2013,7 +1509,7 @@ int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
return sof_pci_probe(pci, pci_id);
}
EXPORT_SYMBOL_NS(hda_pci_intel_probe, SND_SOC_SOF_INTEL_HDA_COMMON);
EXPORT_SYMBOL_NS(hda_pci_intel_probe, SND_SOC_SOF_INTEL_HDA_GENERIC);
int hda_register_clients(struct snd_sof_dev *sdev)
{
@ -2034,4 +1530,5 @@ MODULE_IMPORT_NS(SND_INTEL_SOUNDWIRE_ACPI);
MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT);
MODULE_IMPORT_NS(SOUNDWIRE_INTEL);
MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_ACPI_INTEL_MATCH);

15
sound/soc/sof/intel/hda.h
View File

@ -619,6 +619,8 @@ void hda_ipc_dump(struct snd_sof_dev *sdev);
void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
void hda_dsp_d0i3_work(struct work_struct *work);
int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev);
bool hda_check_ipc_irq(struct snd_sof_dev *sdev);
u32 hda_get_interface_mask(struct snd_sof_dev *sdev);
/*
* DSP PCM Operations.
@ -700,6 +702,8 @@ irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level);
void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level,
u32 flags);
/*
* DSP Code loader.
@ -808,10 +812,12 @@ int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev);
int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev);
int hda_sdw_check_lcount(struct snd_sof_dev *sdev);
int hda_sdw_startup(struct snd_sof_dev *sdev);
void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable);
void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev);
void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev);
void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
@ -827,6 +833,11 @@ static inline int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev)
return 0;
}
static inline int hda_sdw_check_lcount(struct snd_sof_dev *sdev)
{
return 0;
}
static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
{
return 0;
@ -845,6 +856,10 @@ static inline bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev)
return false;
}
static inline void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev)
{
}
static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
{
}

4
sound/soc/sof/intel/icl.c
View File

@ -97,7 +97,6 @@ static int icl_dsp_post_fw_run(struct snd_sof_dev *sdev)
/* Icelake ops */
struct snd_sof_dsp_ops sof_icl_ops;
EXPORT_SYMBOL_NS(sof_icl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
int sof_icl_ops_init(struct snd_sof_dev *sdev)
{
@ -166,7 +165,6 @@ int sof_icl_ops_init(struct snd_sof_dev *sdev)
return 0;
};
EXPORT_SYMBOL_NS(sof_icl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc icl_chip_info = {
/* Icelake */
@ -189,10 +187,10 @@ const struct sof_intel_dsp_desc icl_chip_info = {
.enable_sdw_irq = hda_common_enable_sdw_irq,
.check_sdw_irq = hda_common_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.sdw_process_wakeen = hda_sdw_process_wakeen_common,
.check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_0,
};
EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

4
sound/soc/sof/intel/lnl.c
View File

@ -22,7 +22,6 @@
/* LunarLake ops */
struct snd_sof_dsp_ops sof_lnl_ops;
EXPORT_SYMBOL_NS(sof_lnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
static const struct snd_sof_debugfs_map lnl_dsp_debugfs[] = {
{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
@ -182,7 +181,6 @@ int sof_lnl_ops_init(struct snd_sof_dev *sdev)
return 0;
};
EXPORT_SYMBOL_NS(sof_lnl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
/* Check if an SDW IRQ occurred */
static bool lnl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
@ -240,10 +238,10 @@ const struct sof_intel_dsp_desc lnl_chip_info = {
.enable_sdw_irq = lnl_enable_sdw_irq,
.check_sdw_irq = lnl_dsp_check_sdw_irq,
.check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq,
.sdw_process_wakeen = hda_sdw_process_wakeen_common,
.check_ipc_irq = mtl_dsp_check_ipc_irq,
.cl_init = mtl_dsp_cl_init,
.power_down_dsp = mtl_power_down_dsp,
.disable_interrupts = lnl_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_ACE_2_0,
};
EXPORT_SYMBOL_NS(lnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

21
sound/soc/sof/intel/mtl.c
View File

@ -77,6 +77,7 @@ bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
return false;
}
EXPORT_SYMBOL_NS(mtl_dsp_check_ipc_irq, SND_SOC_SOF_INTEL_MTL);
/* Check if an SDW IRQ occurred */
static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
@ -120,6 +121,7 @@ int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
return 0;
}
EXPORT_SYMBOL_NS(mtl_ipc_send_msg, SND_SOC_SOF_INTEL_MTL);
void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev)
{
@ -147,6 +149,7 @@ void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev)
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0);
}
EXPORT_SYMBOL_NS(mtl_disable_ipc_interrupts, SND_SOC_SOF_INTEL_MTL);
static void mtl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
{
@ -231,6 +234,7 @@ int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable)
return ret;
}
EXPORT_SYMBOL_NS(mtl_enable_interrupts, SND_SOC_SOF_INTEL_MTL);
/* pre fw run operations */
int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
@ -281,6 +285,7 @@ int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
return ret;
}
EXPORT_SYMBOL_NS(mtl_dsp_pre_fw_run, SND_SOC_SOF_INTEL_MTL);
int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
{
@ -307,6 +312,7 @@ int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
hda_sdw_int_enable(sdev, true);
return 0;
}
EXPORT_SYMBOL_NS(mtl_dsp_post_fw_run, SND_SOC_SOF_INTEL_MTL);
void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
{
@ -324,6 +330,7 @@ void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
sof_ipc4_intel_dump_telemetry_state(sdev, flags);
}
EXPORT_SYMBOL_NS(mtl_dsp_dump, SND_SOC_SOF_INTEL_MTL);
static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev)
{
@ -434,6 +441,7 @@ int mtl_power_down_dsp(struct snd_sof_dev *sdev)
(dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_RESET_TIMEOUT_US);
}
EXPORT_SYMBOL_NS(mtl_power_down_dsp, SND_SOC_SOF_INTEL_MTL);
int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
{
@ -536,6 +544,7 @@ err:
kfree(dump_msg);
return ret;
}
EXPORT_SYMBOL_NS(mtl_dsp_cl_init, SND_SOC_SOF_INTEL_MTL);
irqreturn_t mtl_ipc_irq_thread(int irq, void *context)
{
@ -619,16 +628,19 @@ irqreturn_t mtl_ipc_irq_thread(int irq, void *context)
return IRQ_HANDLED;
}
EXPORT_SYMBOL_NS(mtl_ipc_irq_thread, SND_SOC_SOF_INTEL_MTL);
int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
{
return MTL_DSP_MBOX_UPLINK_OFFSET;
}
EXPORT_SYMBOL_NS(mtl_dsp_ipc_get_mailbox_offset, SND_SOC_SOF_INTEL_MTL);
int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
{
return MTL_SRAM_WINDOW_OFFSET(id);
}
EXPORT_SYMBOL_NS(mtl_dsp_ipc_get_window_offset, SND_SOC_SOF_INTEL_MTL);
void mtl_ipc_dump(struct snd_sof_dev *sdev)
{
@ -646,6 +658,7 @@ void mtl_ipc_dump(struct snd_sof_dev *sdev)
"Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n",
hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl);
}
EXPORT_SYMBOL_NS(mtl_ipc_dump, SND_SOC_SOF_INTEL_MTL);
static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
{
@ -666,6 +679,7 @@ int mtl_dsp_core_get(struct snd_sof_dev *sdev, int core)
return 0;
}
EXPORT_SYMBOL_NS(mtl_dsp_core_get, SND_SOC_SOF_INTEL_MTL);
int mtl_dsp_core_put(struct snd_sof_dev *sdev, int core)
{
@ -683,10 +697,10 @@ int mtl_dsp_core_put(struct snd_sof_dev *sdev, int core)
return 0;
}
EXPORT_SYMBOL_NS(mtl_dsp_core_put, SND_SOC_SOF_INTEL_MTL);
/* Meteorlake ops */
struct snd_sof_dsp_ops sof_mtl_ops;
EXPORT_SYMBOL_NS(sof_mtl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
int sof_mtl_ops_init(struct snd_sof_dev *sdev)
{
@ -744,7 +758,6 @@ int sof_mtl_ops_init(struct snd_sof_dev *sdev)
return 0;
};
EXPORT_SYMBOL_NS(sof_mtl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc mtl_chip_info = {
.cores_num = 3,
@ -766,13 +779,13 @@ const struct sof_intel_dsp_desc mtl_chip_info = {
.enable_sdw_irq = mtl_enable_sdw_irq,
.check_sdw_irq = mtl_dsp_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.sdw_process_wakeen = hda_sdw_process_wakeen_common,
.check_ipc_irq = mtl_dsp_check_ipc_irq,
.cl_init = mtl_dsp_cl_init,
.power_down_dsp = mtl_power_down_dsp,
.disable_interrupts = mtl_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_ACE_1_0,
};
EXPORT_SYMBOL_NS(mtl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc arl_s_chip_info = {
.cores_num = 2,
@ -794,10 +807,10 @@ const struct sof_intel_dsp_desc arl_s_chip_info = {
.enable_sdw_irq = mtl_enable_sdw_irq,
.check_sdw_irq = mtl_dsp_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.sdw_process_wakeen = hda_sdw_process_wakeen_common,
.check_ipc_irq = mtl_dsp_check_ipc_irq,
.cl_init = mtl_dsp_cl_init,
.power_down_dsp = mtl_power_down_dsp,
.disable_interrupts = mtl_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_ACE_1_0,
};
EXPORT_SYMBOL_NS(arl_s_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

1
sound/soc/sof/intel/pci-apl.c
View File

@ -105,5 +105,6 @@ static struct pci_driver snd_sof_pci_intel_apl_driver = {
module_pci_driver(snd_sof_pci_intel_apl_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_GENERIC);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);

1
sound/soc/sof/intel/pci-cnl.c
View File

@ -143,5 +143,6 @@ static struct pci_driver snd_sof_pci_intel_cnl_driver = {
module_pci_driver(snd_sof_pci_intel_cnl_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_GENERIC);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);

2
sound/soc/sof/intel/pci-icl.c
View File

@ -108,5 +108,7 @@ static struct pci_driver snd_sof_pci_intel_icl_driver = {
module_pci_driver(snd_sof_pci_intel_icl_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_GENERIC);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_CNL);
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);

3
sound/soc/sof/intel/pci-lnl.c
View File

@ -70,5 +70,8 @@ static struct pci_driver snd_sof_pci_intel_lnl_driver = {
module_pci_driver(snd_sof_pci_intel_lnl_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_GENERIC);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_MTL);
MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK);
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);

1
sound/soc/sof/intel/pci-mtl.c
View File

@ -133,5 +133,6 @@ static struct pci_driver snd_sof_pci_intel_mtl_driver = {
module_pci_driver(snd_sof_pci_intel_mtl_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_GENERIC);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);

1
sound/soc/sof/intel/pci-skl.c
View File

@ -89,5 +89,6 @@ static struct pci_driver snd_sof_pci_intel_skl_driver = {
module_pci_driver(snd_sof_pci_intel_skl_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_GENERIC);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);

2
sound/soc/sof/intel/pci-tgl.c
View File

@ -317,5 +317,7 @@ static struct pci_driver snd_sof_pci_intel_tgl_driver = {
module_pci_driver(snd_sof_pci_intel_tgl_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_GENERIC);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_CNL);
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);

1
sound/soc/sof/intel/shim.h
View File

@ -190,6 +190,7 @@ struct sof_intel_dsp_desc {
void (*enable_sdw_irq)(struct snd_sof_dev *sdev, bool enable);
bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
bool (*check_sdw_wakeen_irq)(struct snd_sof_dev *sdev);
void (*sdw_process_wakeen)(struct snd_sof_dev *sdev);
bool (*check_ipc_irq)(struct snd_sof_dev *sdev);
int (*power_down_dsp)(struct snd_sof_dev *sdev);
int (*disable_interrupts)(struct snd_sof_dev *sdev);

1
sound/soc/sof/intel/telemetry.c
View File

@ -93,3 +93,4 @@ free_block:
free_telemetry_data:
kfree(telemetry_data);
}
EXPORT_SYMBOL_NS(sof_ipc4_intel_dump_telemetry_state, SND_SOC_SOF_INTEL_HDA_COMMON);

10
sound/soc/sof/intel/tgl.c
View File

@ -63,7 +63,6 @@ static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
/* Tigerlake ops */
struct snd_sof_dsp_ops sof_tgl_ops;
EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
int sof_tgl_ops_init(struct snd_sof_dev *sdev)
{
@ -135,7 +134,6 @@ int sof_tgl_ops_init(struct snd_sof_dev *sdev)
return 0;
};
EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc tgl_chip_info = {
/* Tigerlake , Alderlake */
@ -158,13 +156,13 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
.enable_sdw_irq = hda_common_enable_sdw_irq,
.check_sdw_irq = hda_common_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.sdw_process_wakeen = hda_sdw_process_wakeen_common,
.check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc tglh_chip_info = {
/* Tigerlake-H */
@ -187,13 +185,13 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
.enable_sdw_irq = hda_common_enable_sdw_irq,
.check_sdw_irq = hda_common_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.sdw_process_wakeen = hda_sdw_process_wakeen_common,
.check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc ehl_chip_info = {
/* Elkhartlake */
@ -216,13 +214,13 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
.enable_sdw_irq = hda_common_enable_sdw_irq,
.check_sdw_irq = hda_common_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.sdw_process_wakeen = hda_sdw_process_wakeen_common,
.check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc adls_chip_info = {
/* Alderlake-S */
@ -245,10 +243,10 @@ const struct sof_intel_dsp_desc adls_chip_info = {
.enable_sdw_irq = hda_common_enable_sdw_irq,
.check_sdw_irq = hda_common_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.sdw_process_wakeen = hda_sdw_process_wakeen_common,
.check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

5
sound/soc/sof/intel/tracepoints.c Normal file
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// SPDX-License-Identifier: GPL-2.0
#define CREATE_TRACE_POINTS
#include <trace/events/sof_intel.h>
EXPORT_TRACEPOINT_SYMBOL(sof_intel_hda_irq);