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mlxsw: reg: Add to SFMR register the fields related to CFF flood mode

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Add the field cff_mid_base, which specifies at which point in PGT the
per-FID flood table is stored. Add cff_prf_id, the profile ID, which
determines on which row of the flood table a flood vector can be found for
a given traffic type.

Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/3ad7ae38cf6534bedcd876f16090d109a814b3e3.1700503644.git.petrm@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Petr Machata 2023-11-20 19:25:25 +01:00 committed by Jakub Kicinski
parent 446bc1e9de
commit 6b10371c38
1 changed files with 20 additions and 0 deletions
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20
drivers/net/ethernet/mellanox/mlxsw/reg.h
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@ -1944,6 +1944,26 @@ MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1);
*/
MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16);
/* reg_sfmr_cff_mid_base
* Pointer to PGT table.
* Range: 0..(cap_max_pgt-1)
* Access: RW
*
* Note: Reserved when SwitchX/-2 and Spectrum-1.
* Supported when CONFIG_PROFILE.flood_mode = CFF.
*/
MLXSW_ITEM32(reg, sfmr, cff_mid_base, 0x20, 0, 16);
/* reg_sfmr_cff_prf_id
* Compressed Fid Flooding profile_id
* Range 0..(max_cap_nve_flood_prf-1)
* Access: RW
*
* Note: Reserved when SwitchX/-2 and Spectrum-1
* Supported only when CONFIG_PROFLE.flood_mode = CFF.
*/
MLXSW_ITEM32(reg, sfmr, cff_prf_id, 0x24, 0, 2);
/* reg_sfmr_smpe_valid
* SMPE is valid.
* Access: RW