dmaengine: sh: rz-dmac: Fix destination and source data size setting
commit c6ec8c83a29fb3aec3efa6fabbf5344498f57c7f upstream. Before setting DDS and SDS values, we need to clear its value first otherwise, we get incorrect results when we change/update the DMA bus width several times due to the 'OR' expression. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Cc: stable@kernel.org Signed-off-by: Hien Huynh <hien.huynh.px@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230706112150.198941-3-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -9,6 +9,7 @@
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* Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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@ -143,8 +144,8 @@ struct rz_dmac {
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#define CHCFG_REQD BIT(3)
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#define CHCFG_SEL(bits) ((bits) & 0x07)
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#define CHCFG_MEM_COPY (0x80400008)
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#define CHCFG_FILL_DDS(a) (((a) << 16) & GENMASK(19, 16))
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#define CHCFG_FILL_SDS(a) (((a) << 12) & GENMASK(15, 12))
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#define CHCFG_FILL_DDS_MASK GENMASK(19, 16)
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#define CHCFG_FILL_SDS_MASK GENMASK(15, 12)
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#define CHCFG_FILL_TM(a) (((a) & BIT(5)) << 22)
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#define CHCFG_FILL_AM(a) (((a) & GENMASK(4, 2)) << 6)
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#define CHCFG_FILL_LVL(a) (((a) & BIT(1)) << 5)
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@ -607,13 +608,15 @@ static int rz_dmac_config(struct dma_chan *chan,
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if (val == CHCFG_DS_INVALID)
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return -EINVAL;
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channel->chcfg |= CHCFG_FILL_DDS(val);
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channel->chcfg &= ~CHCFG_FILL_DDS_MASK;
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channel->chcfg |= FIELD_PREP(CHCFG_FILL_DDS_MASK, val);
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val = rz_dmac_ds_to_val_mapping(config->src_addr_width);
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if (val == CHCFG_DS_INVALID)
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return -EINVAL;
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channel->chcfg |= CHCFG_FILL_SDS(val);
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channel->chcfg &= ~CHCFG_FILL_SDS_MASK;
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channel->chcfg |= FIELD_PREP(CHCFG_FILL_SDS_MASK, val);
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return 0;
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}
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