dt-bindings: remoteproc: mediatek: Support MT8195 dual-core SCP
Extend the SCP binding to describe the MT8195 dual-core SCP. Under different applications, the MT8195 SCP can be used as single-core or dual-core. This change keeps the single-core definitions and adds new definitions for the dual-core use case. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230901080935.14571-4-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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@ -21,6 +21,7 @@ properties:
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- mediatek,mt8188-scp
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- mediatek,mt8192-scp
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- mediatek,mt8195-scp
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- mediatek,mt8195-scp-dual
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reg:
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description:
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@ -31,10 +32,7 @@ properties:
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reg-names:
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minItems: 2
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items:
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- const: sram
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- const: cfg
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- const: l1tcm
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maxItems: 3
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clocks:
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description:
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@ -70,6 +68,81 @@ properties:
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unevaluatedProperties: false
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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ranges:
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description:
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Standard ranges definition providing address translations for
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local SCP SRAM address spaces to bus addresses.
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patternProperties:
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"^scp@[a-f0-9]+$":
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type: object
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description:
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The MediaTek SCP integrated to SoC might be a multi-core version.
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The other cores are represented as child nodes of the boot core.
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There are some integration differences for the IP like the usage of
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address translator for translating SoC bus addresses into address space
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for the processor.
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Each SCP core has own cache memory. The SRAM and L1TCM are shared by
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cores. The power of cache, SRAM and L1TCM power should be enabled
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before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
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on differnt SoCs.
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The SCP cores do not use an MMU, but has a set of registers to
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control the translations between 32-bit CPU addresses into system bus
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addresses. Cache and memory access settings are provided through a
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Memory Protection Unit (MPU), programmable only from the SCP.
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properties:
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compatible:
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enum:
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- mediatek,scp-core
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reg:
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description: The base address and size of SRAM.
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maxItems: 1
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reg-names:
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const: sram
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interrupts:
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maxItems: 1
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firmware-name:
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$ref: /schemas/types.yaml#/definitions/string
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description:
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If present, name (or relative path) of the file within the
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firmware search path containing the firmware image used when
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initializing sub cores of multi-core SCP.
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memory-region:
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maxItems: 1
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cros-ec-rpmsg:
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$ref: /schemas/mfd/google,cros-ec.yaml
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description:
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This subnode represents the rpmsg device. The properties
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of this node are defined by the individual bindings for
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the rpmsg devices.
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required:
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- mediatek,rpmsg-name
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- reg-names
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additionalProperties: false
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required:
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- compatible
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- reg
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@ -99,7 +172,37 @@ allOf:
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: sram
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- const: cfg
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- if:
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properties:
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compatible:
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enum:
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- mediatek,mt8192-scp
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- mediatek,mt8195-scp
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then:
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properties:
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: sram
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- const: cfg
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- const: l1tcm
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- if:
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properties:
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compatible:
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enum:
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- mediatek,mt8195-scp-dual
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then:
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properties:
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: cfg
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- const: l1tcm
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additionalProperties: false
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@ -121,3 +224,37 @@ examples:
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mediatek,rpmsg-name = "cros-ec-rpmsg";
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};
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};
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- |
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scp@10500000 {
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compatible = "mediatek,mt8195-scp-dual";
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reg = <0x10720000 0xe0000>,
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<0x10700000 0x8000>;
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reg-names = "cfg", "l1tcm";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10500000 0x100000>;
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scp@0 {
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compatible = "mediatek,scp-core";
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reg = <0x0 0xa0000>;
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reg-names = "sram";
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cros-ec-rpmsg {
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compatible = "google,cros-ec-rpmsg";
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mediatek,rpmsg-name = "cros-ec-rpmsg";
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};
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};
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scp@a0000 {
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compatible = "mediatek,scp-core";
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reg = <0xa0000 0x20000>;
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reg-names = "sram";
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cros-ec-rpmsg {
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compatible = "google,cros-ec-rpmsg";
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mediatek,rpmsg-name = "cros-ec-rpmsg";
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};
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};
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};
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