hwrng: stm32 - implement STM32MP13x support
The RNG present on STM32MP13x platforms introduces a customizable configuration and the conditional reset. STM32 RNG configuration should best fit the requirements of the platform. Therefore, put a platform-specific RNG configuration field in the platform data. Default RNG configuration for STM32MP13 is the NIST certified configuration [1]. While there, fix and the RNG init sequence to support all RNG versions. [1] https://csrc.nist.gov/projects/cryptographic-module-validation-program/entropy-validations/certificate/53 Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Gatien Chevallier
Herbert Xu
parent
18d9a8262b
commit
6b85a7e141
@ -17,22 +17,43 @@
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#include <linux/reset.h>
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#include <linux/slab.h>
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#define RNG_CR 0x00
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#define RNG_CR_RNGEN BIT(2)
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#define RNG_CR_CED BIT(5)
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#define RNG_CR 0x00
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#define RNG_CR_RNGEN BIT(2)
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#define RNG_CR_CED BIT(5)
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#define RNG_CR_CONFIG1 GENMASK(11, 8)
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#define RNG_CR_NISTC BIT(12)
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#define RNG_CR_CONFIG2 GENMASK(15, 13)
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#define RNG_CR_CONFIG3 GENMASK(25, 20)
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#define RNG_CR_CONDRST BIT(30)
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#define RNG_CR_CONFLOCK BIT(31)
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#define RNG_CR_ENTROPY_SRC_MASK (RNG_CR_CONFIG1 | RNG_CR_NISTC | RNG_CR_CONFIG2 | RNG_CR_CONFIG3)
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#define RNG_CR_CONFIG_MASK (RNG_CR_ENTROPY_SRC_MASK | RNG_CR_CED)
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#define RNG_SR 0x04
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#define RNG_SR_SEIS BIT(6)
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#define RNG_SR_CEIS BIT(5)
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#define RNG_SR_DRDY BIT(0)
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#define RNG_SR 0x04
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#define RNG_SR_SEIS BIT(6)
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#define RNG_SR_CEIS BIT(5)
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#define RNG_SR_DRDY BIT(0)
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#define RNG_DR 0x08
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#define RNG_DR 0x08
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#define RNG_NSCR 0x0C
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#define RNG_NSCR_MASK GENMASK(17, 0)
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#define RNG_HTCR 0x10
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struct stm32_rng_data {
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u32 cr;
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u32 nscr;
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u32 htcr;
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bool has_cond_reset;
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};
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struct stm32_rng_private {
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struct hwrng rng;
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void __iomem *base;
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struct clk *clk;
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struct reset_control *rst;
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const struct stm32_rng_data *data;
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bool ced;
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};
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@ -87,32 +108,145 @@ static int stm32_rng_init(struct hwrng *rng)
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struct stm32_rng_private *priv =
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container_of(rng, struct stm32_rng_private, rng);
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int err;
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u32 reg;
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err = clk_prepare_enable(priv->clk);
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if (err)
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return err;
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if (priv->ced)
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writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);
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else
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writel_relaxed(RNG_CR_RNGEN | RNG_CR_CED,
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priv->base + RNG_CR);
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/* clear error indicators */
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writel_relaxed(0, priv->base + RNG_SR);
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reg = readl_relaxed(priv->base + RNG_CR);
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/*
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* Keep default RNG configuration if none was specified.
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* 0 is an invalid value as it disables all entropy sources.
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*/
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if (priv->data->has_cond_reset && priv->data->cr) {
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reg &= ~RNG_CR_CONFIG_MASK;
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reg |= RNG_CR_CONDRST | (priv->data->cr & RNG_CR_ENTROPY_SRC_MASK);
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if (priv->ced)
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reg &= ~RNG_CR_CED;
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else
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reg |= RNG_CR_CED;
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writel_relaxed(reg, priv->base + RNG_CR);
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/* Health tests and noise control registers */
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writel_relaxed(priv->data->htcr, priv->base + RNG_HTCR);
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writel_relaxed(priv->data->nscr & RNG_NSCR_MASK, priv->base + RNG_NSCR);
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reg &= ~RNG_CR_CONDRST;
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reg |= RNG_CR_RNGEN;
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writel_relaxed(reg, priv->base + RNG_CR);
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err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_CR, reg,
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(!(reg & RNG_CR_CONDRST)),
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10, 50000);
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if (err) {
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dev_err((struct device *)priv->rng.priv,
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"%s: timeout %x!\n", __func__, reg);
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return -EINVAL;
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}
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} else {
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/* Handle all RNG versions by checking if conditional reset should be set */
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if (priv->data->has_cond_reset)
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reg |= RNG_CR_CONDRST;
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if (priv->ced)
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reg &= ~RNG_CR_CED;
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else
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reg |= RNG_CR_CED;
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writel_relaxed(reg, priv->base + RNG_CR);
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if (priv->data->has_cond_reset)
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reg &= ~RNG_CR_CONDRST;
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reg |= RNG_CR_RNGEN;
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writel_relaxed(reg, priv->base + RNG_CR);
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}
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err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_SR, reg,
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reg & RNG_SR_DRDY,
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10, 100000);
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if (err | (reg & ~RNG_SR_DRDY)) {
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clk_disable_unprepare(priv->clk);
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dev_err((struct device *)priv->rng.priv,
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"%s: timeout:%x SR: %x!\n", __func__, err, reg);
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return -EINVAL;
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}
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return 0;
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}
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static void stm32_rng_cleanup(struct hwrng *rng)
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static int stm32_rng_remove(struct platform_device *ofdev)
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{
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struct stm32_rng_private *priv =
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container_of(rng, struct stm32_rng_private, rng);
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pm_runtime_disable(&ofdev->dev);
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writel_relaxed(0, priv->base + RNG_CR);
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clk_disable_unprepare(priv->clk);
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return 0;
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}
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#ifdef CONFIG_PM
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static int stm32_rng_runtime_suspend(struct device *dev)
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{
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u32 reg;
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struct stm32_rng_private *priv = dev_get_drvdata(dev);
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reg = readl_relaxed(priv->base + RNG_CR);
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reg &= ~RNG_CR_RNGEN;
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writel_relaxed(reg, priv->base + RNG_CR);
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clk_disable_unprepare(priv->clk);
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return 0;
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}
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static int stm32_rng_runtime_resume(struct device *dev)
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{
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u32 reg;
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struct stm32_rng_private *priv = dev_get_drvdata(dev);
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clk_prepare_enable(priv->clk);
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reg = readl_relaxed(priv->base + RNG_CR);
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reg |= RNG_CR_RNGEN;
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writel_relaxed(reg, priv->base + RNG_CR);
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return 0;
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}
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#endif
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static const struct dev_pm_ops stm32_rng_pm_ops = {
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SET_RUNTIME_PM_OPS(stm32_rng_runtime_suspend,
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stm32_rng_runtime_resume, NULL)
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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static const struct stm32_rng_data stm32mp13_rng_data = {
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.has_cond_reset = true,
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.cr = 0x00F00D00,
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.nscr = 0x2B5BB,
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.htcr = 0x969D,
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};
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static const struct stm32_rng_data stm32_rng_data = {
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.has_cond_reset = false,
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};
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static const struct of_device_id stm32_rng_match[] = {
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{
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.compatible = "st,stm32mp13-rng",
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.data = &stm32mp13_rng_data,
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},
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{
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.compatible = "st,stm32-rng",
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.data = &stm32_rng_data,
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, stm32_rng_match);
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static int stm32_rng_probe(struct platform_device *ofdev)
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{
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struct device *dev = &ofdev->dev;
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@ -141,13 +275,14 @@ static int stm32_rng_probe(struct platform_device *ofdev)
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priv->ced = of_property_read_bool(np, "clock-error-detect");
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priv->data = of_device_get_match_data(dev);
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if (!priv->data)
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return -ENODEV;
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dev_set_drvdata(dev, priv);
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priv->rng.name = dev_driver_string(dev);
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#ifndef CONFIG_PM
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priv->rng.init = stm32_rng_init;
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priv->rng.cleanup = stm32_rng_cleanup;
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#endif
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priv->rng.read = stm32_rng_read;
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priv->rng.priv = (unsigned long) dev;
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priv->rng.quality = 900;
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@ -159,47 +294,6 @@ static int stm32_rng_probe(struct platform_device *ofdev)
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return devm_hwrng_register(dev, &priv->rng);
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}
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static int stm32_rng_remove(struct platform_device *ofdev)
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{
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pm_runtime_disable(&ofdev->dev);
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return 0;
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}
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#ifdef CONFIG_PM
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static int stm32_rng_runtime_suspend(struct device *dev)
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{
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struct stm32_rng_private *priv = dev_get_drvdata(dev);
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stm32_rng_cleanup(&priv->rng);
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return 0;
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}
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static int stm32_rng_runtime_resume(struct device *dev)
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{
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struct stm32_rng_private *priv = dev_get_drvdata(dev);
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return stm32_rng_init(&priv->rng);
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}
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#endif
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static const struct dev_pm_ops stm32_rng_pm_ops = {
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SET_RUNTIME_PM_OPS(stm32_rng_runtime_suspend,
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stm32_rng_runtime_resume, NULL)
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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static const struct of_device_id stm32_rng_match[] = {
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{
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.compatible = "st,stm32-rng",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, stm32_rng_match);
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static struct platform_driver stm32_rng_driver = {
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.driver = {
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.name = "stm32-rng",
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