dt-bindings: display: amlogic, meson-vpu: convert to yaml
Now that we have the DT validation in place, let's convert the device tree bindings for the Amlogic Display Controller over to YAML schemas. The original example has a leftover "dmc" memory cell, that has been removed in the yaml rewrite. The port connection table has been dropped in favor of a description of each port. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190808085522.21950-3-narmstrong@baylibre.com
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Amlogic Meson Display Controller
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================================
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The Amlogic Meson Display controller is composed of several components
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that are going to be documented below:
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DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
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| vd1 _______ _____________ _________________ | |
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D |-------| |----| | | | | HDMI PLL |
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D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
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R |-------| |----| Processing | | | | |
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| osd2 | | | |---| Enci ----------|----|-----VDAC------|
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R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
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A | osd1 | | | Blenders | | Encl ----------|----|---------------|
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M |-------|______|----|____________| |________________| | |
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___|__________________________________________________________|_______________|
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VIU: Video Input Unit
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---------------------
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The Video Input Unit is in charge of the pixel scanout from the DDR memory.
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It fetches the frames addresses, stride and parameters from the "Canvas" memory.
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This part is also in charge of the CSC (Colorspace Conversion).
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It can handle 2 OSD Planes and 2 Video Planes.
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VPP: Video Post Processing
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--------------------------
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The Video Post Processing is in charge of the scaling and blending of the
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various planes into a single pixel stream.
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There is a special "pre-blending" used by the video planes with a dedicated
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scaler and a "post-blending" to merge with the OSD Planes.
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The OSD planes also have a dedicated scaler for one of the OSD.
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VENC: Video Encoders
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--------------------
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The VENC is composed of the multiple pixel encoders :
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- ENCI : Interlace Video encoder for CVBS and Interlace HDMI
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- ENCP : Progressive Video Encoder for HDMI
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- ENCL : LCD LVDS Encoder
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The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
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tree and provides the scanout clock to the VPP and VIU.
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The ENCI is connected to a single VDAC for Composite Output.
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The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
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Device Tree Bindings:
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---------------------
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VPU: Video Processing Unit
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--------------------------
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Required properties:
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- compatible: value should be different for each SoC family as :
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- GXBB (S905) : "amlogic,meson-gxbb-vpu"
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- GXL (S905X, S905D) : "amlogic,meson-gxl-vpu"
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- GXM (S912) : "amlogic,meson-gxm-vpu"
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followed by the common "amlogic,meson-gx-vpu"
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- G12A (S905X2, S905Y2, S905D2) : "amlogic,meson-g12a-vpu"
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- reg: base address and size of he following memory-mapped regions :
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- vpu
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- hhi
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- reg-names: should contain the names of the previous memory regions
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- interrupts: should contain the VENC Vsync interrupt number
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- amlogic,canvas: phandle to canvas provider node as described in the file
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../soc/amlogic/amlogic,canvas.txt
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Optional properties:
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- power-domains: Optional phandle to associated power domain as described in
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the file ../power/power_domain.txt
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Required nodes:
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The connections to the VPU output video ports are modeled using the OF graph
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bindings specified in Documentation/devicetree/bindings/graph.txt.
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The following table lists for each supported model the port number
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corresponding to each VPU output.
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Port 0 Port 1
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-----------------------------------------
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S905 (GXBB) CVBS VDAC HDMI-TX
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S905X (GXL) CVBS VDAC HDMI-TX
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S905D (GXL) CVBS VDAC HDMI-TX
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S912 (GXM) CVBS VDAC HDMI-TX
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S905X2 (G12A) CVBS VDAC HDMI-TX
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S905Y2 (G12A) CVBS VDAC HDMI-TX
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S905D2 (G12A) CVBS VDAC HDMI-TX
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Example:
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tv-connector {
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compatible = "composite-video-connector";
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port {
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tv_connector_in: endpoint {
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remote-endpoint = <&cvbs_vdac_out>;
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};
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};
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};
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vpu: vpu@d0100000 {
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compatible = "amlogic,meson-gxbb-vpu";
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reg = <0x0 0xd0100000 0x0 0x100000>,
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<0x0 0xc883c000 0x0 0x1000>,
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<0x0 0xc8838000 0x0 0x1000>;
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reg-names = "vpu", "hhi", "dmc";
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* CVBS VDAC output port */
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port@0 {
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reg = <0>;
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cvbs_vdac_out: endpoint {
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remote-endpoint = <&tv_connector_in>;
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};
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};
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};
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137
Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
Normal file
137
Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
Normal file
@ -0,0 +1,137 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2019 BayLibre, SAS
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic Meson Display Controller
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maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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description: |
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The Amlogic Meson Display controller is composed of several components
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that are going to be documented below
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DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
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| vd1 _______ _____________ _________________ | |
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D |-------| |----| | | | | HDMI PLL |
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D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
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R |-------| |----| Processing | | | | |
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| osd2 | | | |---| Enci ----------|----|-----VDAC------|
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R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
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A | osd1 | | | Blenders | | Encl ----------|----|---------------|
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M |-------|______|----|____________| |________________| | |
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___|__________________________________________________________|_______________|
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VIU: Video Input Unit
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---------------------
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The Video Input Unit is in charge of the pixel scanout from the DDR memory.
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It fetches the frames addresses, stride and parameters from the "Canvas" memory.
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This part is also in charge of the CSC (Colorspace Conversion).
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It can handle 2 OSD Planes and 2 Video Planes.
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VPP: Video Post Processing
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--------------------------
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The Video Post Processing is in charge of the scaling and blending of the
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various planes into a single pixel stream.
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There is a special "pre-blending" used by the video planes with a dedicated
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scaler and a "post-blending" to merge with the OSD Planes.
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The OSD planes also have a dedicated scaler for one of the OSD.
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VENC: Video Encoders
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--------------------
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The VENC is composed of the multiple pixel encoders
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- ENCI : Interlace Video encoder for CVBS and Interlace HDMI
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- ENCP : Progressive Video Encoder for HDMI
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- ENCL : LCD LVDS Encoder
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The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
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tree and provides the scanout clock to the VPP and VIU.
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The ENCI is connected to a single VDAC for Composite Output.
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The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- amlogic,meson-gxbb-vpu # GXBB (S905)
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- amlogic,meson-gxl-vpu # GXL (S905X, S905D)
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- amlogic,meson-gxm-vpu # GXM (S912)
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- const: amlogic,meson-gx-vpu
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- enum:
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- amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: vpu
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- const: hhi
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interrupts:
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maxItems: 1
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power-domains:
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maxItems: 1
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description: phandle to the associated power domain
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port@0:
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type: object
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description:
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A port node pointing to the CVBS VDAC port node.
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port@1:
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type: object
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description:
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A port node pointing to the HDMI-TX port node.
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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required:
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- compatible
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- reg
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- interrupts
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- port@0
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- port@1
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- "#address-cells"
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- "#size-cells"
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examples:
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- |
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vpu: vpu@d0100000 {
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compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
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reg = <0xd0100000 0x100000>, <0xc883c000 0x1000>;
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reg-names = "vpu", "hhi";
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interrupts = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* CVBS VDAC output port */
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port@0 {
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reg = <0>;
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cvbs_vdac_out: endpoint {
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remote-endpoint = <&tv_connector_in>;
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};
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};
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/* HDMI TX output port */
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port@1 {
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reg = <1>;
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hdmi_tx_out: endpoint {
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remote-endpoint = <&hdmi_tx_in>;
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};
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};
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};
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