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drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support

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[why & how]

Expose vendor specific DPCD registers for rate controlling the eDP sink
TCON's refresh rate during PSR active. When used in combination with
PSR-SU and Freesync, it is called PSR-SU Rate Contorol, or PSR-SU-RC for
short.

v2: Add all DPCD registers required

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
David Zhang 2022-05-03 17:53:44 -04:00 committed by Alex Deucher
parent 44961f6ebc
commit 6bad4ff84c
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/amd/display/include/ddc_service_types.h
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@ -41,6 +41,10 @@
#define DP_DEVICE_ID_38EC11 0x38EC11
#define DP_FORCE_PSRSU_CAPABILITY 0x40F
#define DP_SINK_PSR_ACTIVE_VTOTAL 0x373
#define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE 0x375
#define DP_SOURCE_PSR_ACTIVE_VTOTAL 0x376
enum ddc_result {
DDC_RESULT_UNKNOWN = 0,
DDC_RESULT_SUCESSFULL,