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drm/amd/display: Change initializer to single brace

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[Why & How]
Change struct initializer from multiple brace to single brace.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aric Cyr 2021-10-02 09:44:08 -04:00 committed by Alex Deucher
parent 2b96b036a6
commit 6bad8e4a0e
3 changed files with 19 additions and 19 deletions
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4
drivers/gpu/drm/amd/display/dc/core/dc_link.c
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@ -1528,7 +1528,7 @@ static bool dc_link_construct_legacy(struct dc_link *link,
const struct link_init_data *init_params)
{
uint8_t i;
struct ddc_service_init_data ddc_service_init_data = { { 0 } };
struct ddc_service_init_data ddc_service_init_data = { 0 };
struct dc_context *dc_ctx = init_params->ctx;
struct encoder_init_data enc_init_data = { 0 };
struct panel_cntl_init_data panel_cntl_init_data = { 0 };
@ -1828,7 +1828,7 @@ create_fail:
static bool dc_link_construct_dpia(struct dc_link *link,
const struct link_init_data *init_params)
{
struct ddc_service_init_data ddc_service_init_data = { { 0 } };
struct ddc_service_init_data ddc_service_init_data = { 0 };
struct dc_context *dc_ctx = init_params->ctx;
DC_LOGGER_INIT(dc_ctx->logger);

6
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View File

@ -638,7 +638,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
uint32_t dpcd_base_lt_offset;
uint8_t dpcd_lt_buffer[5] = {0};
union dpcd_training_pattern dpcd_pattern = { 0 };
union dpcd_training_pattern dpcd_pattern = {0};
uint32_t size_in_bytes;
bool edp_workaround = false; /* TODO link_prop.INTERNAL */
dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
@ -1369,7 +1369,7 @@ static enum link_training_result perform_clock_recovery_sequence(
enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
union lane_align_status_updated dpcd_lane_status_updated;
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
retries_cr = 0;
retry_count = 0;
@ -2164,7 +2164,7 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
enum link_training_result result = LINK_TRAINING_SUCCESS;
union lane_align_status_updated dpcd_lane_status_updated = {0};
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
uint32_t wait_time = 0;
/* initiate CDS done sequence */

28
drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
View File

@ -226,7 +226,7 @@ static enum dc_status dpcd_set_lt_pattern(struct dc_link *link,
enum dc_dp_training_pattern pattern,
uint32_t hop)
{
union dpcd_training_pattern dpcd_pattern = { {0} };
union dpcd_training_pattern dpcd_pattern = {0};
uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;
enum dc_status status;
@ -287,9 +287,9 @@ static enum link_training_result dpia_training_cr_non_transparent(
/* From DP spec, CR read interval is always 100us. */
uint32_t wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
union lane_align_status_updated dpcd_lane_status_updated = { {0} };
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
union lane_align_status_updated dpcd_lane_status_updated = {0};
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
uint8_t set_cfg_data;
enum dpia_set_config_ts ts;
@ -445,9 +445,9 @@ static enum link_training_result dpia_training_cr_transparent(
uint32_t retry_count = 0;
uint32_t wait_time_microsec = lt_settings->cr_pattern_time;
enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
union lane_align_status_updated dpcd_lane_status_updated = { {0} };
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
union lane_align_status_updated dpcd_lane_status_updated = {0};
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
/* Cap of LINK_TRAINING_MAX_CR_RETRY attempts at clock recovery.
* Fix inherited from perform_clock_recovery_sequence() -
@ -599,9 +599,9 @@ static enum link_training_result dpia_training_eq_non_transparent(
enum dc_dp_training_pattern tr_pattern;
uint32_t wait_time_microsec;
enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
union lane_align_status_updated dpcd_lane_status_updated = { {0} };
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
union lane_align_status_updated dpcd_lane_status_updated = {0};
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
uint8_t set_cfg_data;
enum dpia_set_config_ts ts;
@ -738,9 +738,9 @@ static enum link_training_result dpia_training_eq_transparent(
enum dc_dp_training_pattern tr_pattern = lt_settings->pattern_for_eq;
uint32_t wait_time_microsec;
enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
union lane_align_status_updated dpcd_lane_status_updated = { {0} };
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
union lane_align_status_updated dpcd_lane_status_updated = {0};
union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
wait_time_microsec = dpia_get_eq_aux_rd_interval(link, lt_settings, DPRX);
@ -827,7 +827,7 @@ static enum link_training_result dpia_training_eq_phase(
/* End training of specified hop in display path. */
static enum dc_status dpcd_clear_lt_pattern(struct dc_link *link, uint32_t hop)
{
union dpcd_training_pattern dpcd_pattern = { {0} };
union dpcd_training_pattern dpcd_pattern = {0};
uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;
enum dc_status status;