staging: brcm80211: removed static function declarations in dma.c
Reported-by: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: Roland Vossen <rvossen@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Roland Vossen
Greg Kroah-Hartman
parent
0390bf7acc
commit
6bccc65a6a
@ -197,16 +197,34 @@
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#define txd64 dregs.d64_u.txd_64
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#define rxd64 dregs.d64_u.rxd_64
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/*
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* default dma message level (if input msg_level
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* pointer is null in dma_attach())
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*/
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static uint dma_msg_level;
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#define MAXNAMEL 8 /* 8 char names */
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#define DI_INFO(dmah) ((dma_info_t *)dmah)
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/* descriptor bumping macros */
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/* faster than %, but n must be power of 2 */
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#define XXD(x, n) ((x) & ((n) - 1))
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#define TXD(x) XXD((x), di->ntxd)
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#define RXD(x) XXD((x), di->nrxd)
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#define NEXTTXD(i) TXD((i) + 1)
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#define PREVTXD(i) TXD((i) - 1)
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#define NEXTRXD(i) RXD((i) + 1)
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#define PREVRXD(i) RXD((i) - 1)
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#define NTXDACTIVE(h, t) TXD((t) - (h))
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#define NRXDACTIVE(h, t) RXD((t) - (h))
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/* macros to convert between byte offsets and indexes */
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#define B2I(bytes, type) ((bytes) / sizeof(type))
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#define I2B(index, type) ((index) * sizeof(type))
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#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
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#define PCI32ADDR_HIGH_SHIFT 30 /* address[31:30] */
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#define PCI64ADDR_HIGH 0x80000000 /* address[63] */
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#define PCI64ADDR_HIGH_SHIFT 31 /* address[63] */
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/*
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* DMA Descriptor
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* Descriptors are only read by the hardware, never written back.
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@ -298,51 +316,202 @@ struct dma_info {
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bool aligndesc_4k;
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};
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/* descriptor bumping macros */
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/* faster than %, but n must be power of 2 */
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#define XXD(x, n) ((x) & ((n) - 1))
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/*
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* default dma message level (if input msg_level
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* pointer is null in dma_attach())
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*/
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static uint dma_msg_level;
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#define TXD(x) XXD((x), di->ntxd)
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#define RXD(x) XXD((x), di->nrxd)
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#define NEXTTXD(i) TXD((i) + 1)
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#define PREVTXD(i) TXD((i) - 1)
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#define NEXTRXD(i) RXD((i) + 1)
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#define PREVRXD(i) RXD((i) - 1)
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static uint _dma_ctrlflags(struct dma_info *di, uint mask, uint flags)
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{
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uint dmactrlflags = di->dma.dmactrlflags;
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#define NTXDACTIVE(h, t) TXD((t) - (h))
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#define NRXDACTIVE(h, t) RXD((t) - (h))
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if (di == NULL) {
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DMA_ERROR(("%s: _dma_ctrlflags: NULL dma handle\n", di->name));
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return 0;
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}
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/* macros to convert between byte offsets and indexes */
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#define B2I(bytes, type) ((bytes) / sizeof(type))
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#define I2B(index, type) ((index) * sizeof(type))
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dmactrlflags &= ~mask;
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dmactrlflags |= flags;
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#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
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#define PCI32ADDR_HIGH_SHIFT 30 /* address[31:30] */
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/* If trying to enable parity, check if parity is actually supported */
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if (dmactrlflags & DMA_CTRL_PEN) {
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u32 control;
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#define PCI64ADDR_HIGH 0x80000000 /* address[63] */
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#define PCI64ADDR_HIGH_SHIFT 31 /* address[63] */
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control = R_REG(&di->d64txregs->control);
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W_REG(&di->d64txregs->control,
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control | D64_XC_PD);
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if (R_REG(&di->d64txregs->control) & D64_XC_PD)
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/* We *can* disable it so it is supported,
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* restore control register
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*/
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W_REG(&di->d64txregs->control,
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control);
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else
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/* Not supported, don't allow it to be enabled */
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dmactrlflags &= ~DMA_CTRL_PEN;
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}
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/* Common prototypes */
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static bool _dma_isaddrext(struct dma_info *di);
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static bool _dma_descriptor_align(struct dma_info *di);
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static bool _dma_alloc(struct dma_info *di, uint direction);
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static void _dma_ddtable_init(struct dma_info *di, uint direction,
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dma_addr_t pa);
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static void _dma_rxenable(struct dma_info *di);
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static struct sk_buff *_dma_getnextrxp(struct dma_info *di, bool forceall);
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static uint _dma_ctrlflags(struct dma_info *di, uint mask, uint flags);
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static u8 dma_align_sizetobits(uint size);
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di->dma.dmactrlflags = dmactrlflags;
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return dmactrlflags;
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}
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static bool _dma64_addrext(struct dma64regs *dma64regs)
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{
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u32 w;
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OR_REG(&dma64regs->control, D64_XC_AE);
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w = R_REG(&dma64regs->control);
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AND_REG(&dma64regs->control, ~D64_XC_AE);
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return (w & D64_XC_AE) == D64_XC_AE;
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}
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/*
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* return true if this dma engine supports DmaExtendedAddrChanges,
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* otherwise false
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*/
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static bool _dma_isaddrext(struct dma_info *di)
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{
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/* DMA64 supports full 32- or 64-bit operation. AE is always valid */
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/* not all tx or rx channel are available */
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if (di->d64txregs != NULL) {
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if (!_dma64_addrext(di->d64txregs))
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DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have "
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"AE set\n", di->name));
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return true;
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} else if (di->d64rxregs != NULL) {
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if (!_dma64_addrext(di->d64rxregs))
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DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have "
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"AE set\n", di->name));
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return true;
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}
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return false;
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}
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static bool _dma_descriptor_align(struct dma_info *di)
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{
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u32 addrl;
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/* Check to see if the descriptors need to be aligned on 4K/8K or not */
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if (di->d64txregs != NULL) {
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W_REG(&di->d64txregs->addrlow, 0xff0);
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addrl = R_REG(&di->d64txregs->addrlow);
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if (addrl != 0)
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return false;
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} else if (di->d64rxregs != NULL) {
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W_REG(&di->d64rxregs->addrlow, 0xff0);
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addrl = R_REG(&di->d64rxregs->addrlow);
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if (addrl != 0)
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return false;
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}
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return true;
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}
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void *dma_alloc_consistent(struct pci_dev *pdev, uint size, u16 align_bits,
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uint *alloced, dma_addr_t *pap)
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{
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if (align_bits) {
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u16 align = (1 << align_bits);
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if (!IS_ALIGNED(PAGE_SIZE, align))
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size += align;
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*alloced = size;
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}
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return pci_alloc_consistent(pdev, size, pap);
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}
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static
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u8 dma_align_sizetobits(uint size)
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{
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u8 bitpos = 0;
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while (size >>= 1)
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bitpos++;
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return bitpos;
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}
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/* This function ensures that the DMA descriptor ring will not get allocated
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* across Page boundary. If the allocation is done across the page boundary
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* at the first time, then it is freed and the allocation is done at
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* descriptor ring size aligned location. This will ensure that the ring will
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* not cross page boundary
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*/
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static void *dma_ringalloc(struct dma_info *di, u32 boundary, uint size,
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u16 *alignbits, uint *alloced,
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dma_addr_t *descpa);
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dma_addr_t *descpa)
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{
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void *va;
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u32 desc_strtaddr;
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u32 alignbytes = 1 << *alignbits;
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/* Prototypes for 64-bit routines */
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static bool dma64_alloc(struct dma_info *di, uint direction);
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static struct sk_buff *dma64_getnextrxp(struct dma_info *di, bool forceall);
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static bool dma64_rxidle(struct dma_info *di);
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static bool _dma64_addrext(struct dma64regs *dma64regs);
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va = dma_alloc_consistent(di->pbus, size, *alignbits, alloced, descpa);
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static inline u32 parity32(u32 data);
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if (NULL == va)
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return NULL;
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desc_strtaddr = (u32) roundup((unsigned long)va, alignbytes);
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if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr
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& boundary)) {
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*alignbits = dma_align_sizetobits(size);
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pci_free_consistent(di->pbus, size, va, *descpa);
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va = dma_alloc_consistent(di->pbus, size, *alignbits,
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alloced, descpa);
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}
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return va;
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}
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static bool dma64_alloc(struct dma_info *di, uint direction)
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{
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u16 size;
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uint ddlen;
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void *va;
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uint alloced = 0;
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u16 align;
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u16 align_bits;
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ddlen = sizeof(struct dma64desc);
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size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
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align_bits = di->dmadesc_align;
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align = (1 << align_bits);
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if (direction == DMA_TX) {
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va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
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&alloced, &di->txdpaorig);
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if (va == NULL) {
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DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(ntxd)"
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" failed\n", di->name));
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return false;
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}
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align = (1 << align_bits);
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di->txd64 = (struct dma64desc *)
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roundup((unsigned long)va, align);
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di->txdalign = (uint) ((s8 *)di->txd64 - (s8 *) va);
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di->txdpa = di->txdpaorig + di->txdalign;
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di->txdalloc = alloced;
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} else {
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va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
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&alloced, &di->rxdpaorig);
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if (va == NULL) {
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DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(nrxd)"
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" failed\n", di->name));
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return false;
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}
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align = (1 << align_bits);
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di->rxd64 = (struct dma64desc *)
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roundup((unsigned long)va, align);
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di->rxdalign = (uint) ((s8 *)di->rxd64 - (s8 *) va);
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di->rxdpa = di->rxdpaorig + di->rxdalign;
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di->rxdalloc = alloced;
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}
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return true;
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}
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static bool _dma_alloc(struct dma_info *di, uint direction)
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{
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return dma64_alloc(di, direction);
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}
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struct dma_pub *dma_attach(char *name, struct si_pub *sih,
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void *dmaregstx, void *dmaregsrx, uint ntxd,
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@ -551,23 +720,6 @@ dma64_dd_upd(struct dma_info *di, struct dma64desc *ddring,
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}
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}
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static bool _dma_alloc(struct dma_info *di, uint direction)
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{
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return dma64_alloc(di, direction);
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}
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void *dma_alloc_consistent(struct pci_dev *pdev, uint size, u16 align_bits,
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uint *alloced, dma_addr_t *pap)
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{
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if (align_bits) {
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u16 align = (1 << align_bits);
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if (!IS_ALIGNED(PAGE_SIZE, align))
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size += align;
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*alloced = size;
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}
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return pci_alloc_consistent(pdev, size, pap);
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}
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/* !! may be called with core in reset */
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void dma_detach(struct dma_pub *pub)
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{
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@ -594,49 +746,6 @@ void dma_detach(struct dma_pub *pub)
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}
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static bool _dma_descriptor_align(struct dma_info *di)
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{
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u32 addrl;
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/* Check to see if the descriptors need to be aligned on 4K/8K or not */
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if (di->d64txregs != NULL) {
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W_REG(&di->d64txregs->addrlow, 0xff0);
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addrl = R_REG(&di->d64txregs->addrlow);
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if (addrl != 0)
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return false;
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} else if (di->d64rxregs != NULL) {
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W_REG(&di->d64rxregs->addrlow, 0xff0);
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addrl = R_REG(&di->d64rxregs->addrlow);
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if (addrl != 0)
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return false;
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}
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return true;
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}
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/*
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* return true if this dma engine supports DmaExtendedAddrChanges,
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* otherwise false
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*/
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static bool _dma_isaddrext(struct dma_info *di)
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{
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/* DMA64 supports full 32- or 64-bit operation. AE is always valid */
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/* not all tx or rx channel are available */
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if (di->d64txregs != NULL) {
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if (!_dma64_addrext(di->d64txregs))
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DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have "
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"AE set\n", di->name));
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return true;
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} else if (di->d64rxregs != NULL) {
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if (!_dma64_addrext(di->d64rxregs))
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DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have "
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"AE set\n", di->name));
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return true;
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}
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return false;
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}
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/* initialize descriptor table base address */
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static void
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_dma_ddtable_init(struct dma_info *di, uint direction, dma_addr_t pa)
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@ -679,6 +788,27 @@ _dma_ddtable_init(struct dma_info *di, uint direction, dma_addr_t pa)
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}
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}
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static void _dma_rxenable(struct dma_info *di)
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{
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uint dmactrlflags = di->dma.dmactrlflags;
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u32 control;
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DMA_TRACE(("%s: dma_rxenable\n", di->name));
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control =
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(R_REG(&di->d64rxregs->control) & D64_RC_AE) |
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D64_RC_RE;
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if ((dmactrlflags & DMA_CTRL_PEN) == 0)
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control |= D64_RC_PD;
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if (dmactrlflags & DMA_CTRL_ROC)
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control |= D64_RC_OC;
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W_REG(&di->d64rxregs->control,
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((di->rxoffset << D64_RC_RO_SHIFT) | control));
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}
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void dma_rxinit(struct dma_pub *pub)
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{
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struct dma_info *di = (struct dma_info *)pub;
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@ -705,25 +835,49 @@ void dma_rxinit(struct dma_pub *pub)
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_dma_ddtable_init(di, DMA_RX, di->rxdpa);
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}
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static void _dma_rxenable(struct dma_info *di)
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static struct sk_buff *dma64_getnextrxp(struct dma_info *di, bool forceall)
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{
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uint dmactrlflags = di->dma.dmactrlflags;
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u32 control;
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uint i, curr;
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struct sk_buff *rxp;
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dma_addr_t pa;
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DMA_TRACE(("%s: dma_rxenable\n", di->name));
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i = di->rxin;
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control =
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(R_REG(&di->d64rxregs->control) & D64_RC_AE) |
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D64_RC_RE;
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/* return if no packets posted */
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if (i == di->rxout)
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return NULL;
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if ((dmactrlflags & DMA_CTRL_PEN) == 0)
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control |= D64_RC_PD;
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curr =
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B2I(((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) -
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di->rcvptrbase) & D64_RS0_CD_MASK, struct dma64desc);
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if (dmactrlflags & DMA_CTRL_ROC)
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control |= D64_RC_OC;
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/* ignore curr if forceall */
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if (!forceall && (i == curr))
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return NULL;
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W_REG(&di->d64rxregs->control,
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((di->rxoffset << D64_RC_RO_SHIFT) | control));
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/* get the packet pointer that corresponds to the rx descriptor */
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rxp = di->rxp[i];
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di->rxp[i] = NULL;
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pa = cpu_to_le32(di->rxd64[i].addrlow) - di->dataoffsetlow;
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/* clear this packet from the descriptor ring */
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pci_unmap_single(di->pbus, pa, di->rxbufsize, PCI_DMA_FROMDEVICE);
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di->rxd64[i].addrlow = 0xdeadbeef;
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di->rxd64[i].addrhigh = 0xdeadbeef;
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di->rxin = NEXTRXD(i);
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return rxp;
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}
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static struct sk_buff *_dma_getnextrxp(struct dma_info *di, bool forceall)
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{
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if (di->nrxd == 0)
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return NULL;
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return dma64_getnextrxp(di, forceall);
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}
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/*
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||||
@ -795,6 +949,17 @@ struct sk_buff *dma_rx(struct dma_pub *pub)
|
||||
return head;
|
||||
}
|
||||
|
||||
static bool dma64_rxidle(struct dma_info *di)
|
||||
{
|
||||
DMA_TRACE(("%s: dma_rxidle\n", di->name));
|
||||
|
||||
if (di->nrxd == 0)
|
||||
return true;
|
||||
|
||||
return ((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) ==
|
||||
(R_REG(&di->d64rxregs->ptr) & D64_RS0_CD_MASK));
|
||||
}
|
||||
|
||||
/*
|
||||
* post receive buffers
|
||||
* return false is refill failed completely and ring is empty this will stall
|
||||
@ -894,14 +1059,6 @@ void dma_rxreclaim(struct dma_pub *pub)
|
||||
brcmu_pkt_buf_free_skb(p);
|
||||
}
|
||||
|
||||
static struct sk_buff *_dma_getnextrxp(struct dma_info *di, bool forceall)
|
||||
{
|
||||
if (di->nrxd == 0)
|
||||
return NULL;
|
||||
|
||||
return dma64_getnextrxp(di, forceall);
|
||||
}
|
||||
|
||||
void dma_counterreset(struct dma_pub *pub)
|
||||
{
|
||||
/* reset all software counters */
|
||||
@ -910,41 +1067,6 @@ void dma_counterreset(struct dma_pub *pub)
|
||||
pub->txnobuf = 0;
|
||||
}
|
||||
|
||||
static uint _dma_ctrlflags(struct dma_info *di, uint mask, uint flags)
|
||||
{
|
||||
uint dmactrlflags = di->dma.dmactrlflags;
|
||||
|
||||
if (di == NULL) {
|
||||
DMA_ERROR(("%s: _dma_ctrlflags: NULL dma handle\n", di->name));
|
||||
return 0;
|
||||
}
|
||||
|
||||
dmactrlflags &= ~mask;
|
||||
dmactrlflags |= flags;
|
||||
|
||||
/* If trying to enable parity, check if parity is actually supported */
|
||||
if (dmactrlflags & DMA_CTRL_PEN) {
|
||||
u32 control;
|
||||
|
||||
control = R_REG(&di->d64txregs->control);
|
||||
W_REG(&di->d64txregs->control,
|
||||
control | D64_XC_PD);
|
||||
if (R_REG(&di->d64txregs->control) & D64_XC_PD)
|
||||
/* We *can* disable it so it is supported,
|
||||
* restore control register
|
||||
*/
|
||||
W_REG(&di->d64txregs->control,
|
||||
control);
|
||||
else
|
||||
/* Not supported, don't allow it to be enabled */
|
||||
dmactrlflags &= ~DMA_CTRL_PEN;
|
||||
}
|
||||
|
||||
di->dma.dmactrlflags = dmactrlflags;
|
||||
|
||||
return dmactrlflags;
|
||||
}
|
||||
|
||||
/* get the address of the var in order to change later */
|
||||
unsigned long dma_getvar(struct dma_pub *pub, const char *name)
|
||||
{
|
||||
@ -955,45 +1077,6 @@ unsigned long dma_getvar(struct dma_pub *pub, const char *name)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static
|
||||
u8 dma_align_sizetobits(uint size)
|
||||
{
|
||||
u8 bitpos = 0;
|
||||
while (size >>= 1)
|
||||
bitpos++;
|
||||
return bitpos;
|
||||
}
|
||||
|
||||
/* This function ensures that the DMA descriptor ring will not get allocated
|
||||
* across Page boundary. If the allocation is done across the page boundary
|
||||
* at the first time, then it is freed and the allocation is done at
|
||||
* descriptor ring size aligned location. This will ensure that the ring will
|
||||
* not cross page boundary
|
||||
*/
|
||||
static void *dma_ringalloc(struct dma_info *di, u32 boundary, uint size,
|
||||
u16 *alignbits, uint *alloced,
|
||||
dma_addr_t *descpa)
|
||||
{
|
||||
void *va;
|
||||
u32 desc_strtaddr;
|
||||
u32 alignbytes = 1 << *alignbits;
|
||||
|
||||
va = dma_alloc_consistent(di->pbus, size, *alignbits, alloced, descpa);
|
||||
|
||||
if (NULL == va)
|
||||
return NULL;
|
||||
|
||||
desc_strtaddr = (u32) roundup((unsigned long)va, alignbytes);
|
||||
if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr
|
||||
& boundary)) {
|
||||
*alignbits = dma_align_sizetobits(size);
|
||||
pci_free_consistent(di->pbus, size, va, *descpa);
|
||||
va = dma_alloc_consistent(di->pbus, size, *alignbits,
|
||||
alloced, descpa);
|
||||
}
|
||||
return va;
|
||||
}
|
||||
|
||||
/* 64-bit DMA functions */
|
||||
|
||||
void dma_txinit(struct dma_pub *pub)
|
||||
@ -1083,54 +1166,6 @@ void dma_txreclaim(struct dma_pub *pub, enum txd_range range)
|
||||
}
|
||||
}
|
||||
|
||||
static bool dma64_alloc(struct dma_info *di, uint direction)
|
||||
{
|
||||
u16 size;
|
||||
uint ddlen;
|
||||
void *va;
|
||||
uint alloced = 0;
|
||||
u16 align;
|
||||
u16 align_bits;
|
||||
|
||||
ddlen = sizeof(struct dma64desc);
|
||||
|
||||
size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
|
||||
align_bits = di->dmadesc_align;
|
||||
align = (1 << align_bits);
|
||||
|
||||
if (direction == DMA_TX) {
|
||||
va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
|
||||
&alloced, &di->txdpaorig);
|
||||
if (va == NULL) {
|
||||
DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(ntxd)"
|
||||
" failed\n", di->name));
|
||||
return false;
|
||||
}
|
||||
align = (1 << align_bits);
|
||||
di->txd64 = (struct dma64desc *)
|
||||
roundup((unsigned long)va, align);
|
||||
di->txdalign = (uint) ((s8 *)di->txd64 - (s8 *) va);
|
||||
di->txdpa = di->txdpaorig + di->txdalign;
|
||||
di->txdalloc = alloced;
|
||||
} else {
|
||||
va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
|
||||
&alloced, &di->rxdpaorig);
|
||||
if (va == NULL) {
|
||||
DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(nrxd)"
|
||||
" failed\n", di->name));
|
||||
return false;
|
||||
}
|
||||
align = (1 << align_bits);
|
||||
di->rxd64 = (struct dma64desc *)
|
||||
roundup((unsigned long)va, align);
|
||||
di->rxdalign = (uint) ((s8 *)di->rxd64 - (s8 *) va);
|
||||
di->rxdpa = di->rxdpaorig + di->rxdalign;
|
||||
di->rxdalloc = alloced;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool dma_txreset(struct dma_pub *pub)
|
||||
{
|
||||
struct dma_info *di = (struct dma_info *)pub;
|
||||
@ -1157,17 +1192,6 @@ bool dma_txreset(struct dma_pub *pub)
|
||||
return status == D64_XS0_XS_DISABLED;
|
||||
}
|
||||
|
||||
static bool dma64_rxidle(struct dma_info *di)
|
||||
{
|
||||
DMA_TRACE(("%s: dma_rxidle\n", di->name));
|
||||
|
||||
if (di->nrxd == 0)
|
||||
return true;
|
||||
|
||||
return ((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) ==
|
||||
(R_REG(&di->d64rxregs->ptr) & D64_RS0_CD_MASK));
|
||||
}
|
||||
|
||||
bool dma_rxreset(struct dma_pub *pub)
|
||||
{
|
||||
struct dma_info *di = (struct dma_info *)pub;
|
||||
@ -1357,52 +1381,6 @@ struct sk_buff *dma_getnexttxp(struct dma_pub *pub, enum txd_range range)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct sk_buff *dma64_getnextrxp(struct dma_info *di, bool forceall)
|
||||
{
|
||||
uint i, curr;
|
||||
struct sk_buff *rxp;
|
||||
dma_addr_t pa;
|
||||
|
||||
i = di->rxin;
|
||||
|
||||
/* return if no packets posted */
|
||||
if (i == di->rxout)
|
||||
return NULL;
|
||||
|
||||
curr =
|
||||
B2I(((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) -
|
||||
di->rcvptrbase) & D64_RS0_CD_MASK, struct dma64desc);
|
||||
|
||||
/* ignore curr if forceall */
|
||||
if (!forceall && (i == curr))
|
||||
return NULL;
|
||||
|
||||
/* get the packet pointer that corresponds to the rx descriptor */
|
||||
rxp = di->rxp[i];
|
||||
di->rxp[i] = NULL;
|
||||
|
||||
pa = cpu_to_le32(di->rxd64[i].addrlow) - di->dataoffsetlow;
|
||||
|
||||
/* clear this packet from the descriptor ring */
|
||||
pci_unmap_single(di->pbus, pa, di->rxbufsize, PCI_DMA_FROMDEVICE);
|
||||
|
||||
di->rxd64[i].addrlow = 0xdeadbeef;
|
||||
di->rxd64[i].addrhigh = 0xdeadbeef;
|
||||
|
||||
di->rxin = NEXTRXD(i);
|
||||
|
||||
return rxp;
|
||||
}
|
||||
|
||||
static bool _dma64_addrext(struct dma64regs *dma64regs)
|
||||
{
|
||||
u32 w;
|
||||
OR_REG(&dma64regs->control, D64_XC_AE);
|
||||
w = R_REG(&dma64regs->control);
|
||||
AND_REG(&dma64regs->control, ~D64_XC_AE);
|
||||
return (w & D64_XC_AE) == D64_XC_AE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Mac80211 initiated actions sometimes require packets in the DMA queue to be
|
||||
* modified. The modified portion of the packet is not under control of the DMA
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user