ALSA: hda/realtek - Restore default value for ALC283
Restore the registers to prevent the abnormal digital power supply rising ratio/sequence to the codec and causing the incorrect default codec register restoration during initialization. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=71861 Signed-off-by: Kailang Yang <kailang@realtek.com> Cc: <stable@vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -2786,6 +2786,89 @@ static void alc269_shutup(struct hda_codec *codec)
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snd_hda_shutup_pins(codec);
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snd_hda_shutup_pins(codec);
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}
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}
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static void alc283_restore_default_value(struct hda_codec *codec)
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{
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int val;
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/* Power Down Control */
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alc_write_coef_idx(codec, 0x03, 0x0002);
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/* FIFO and filter clock */
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alc_write_coef_idx(codec, 0x05, 0x0700);
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/* DMIC control */
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alc_write_coef_idx(codec, 0x07, 0x0200);
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/* Analog clock */
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val = alc_read_coef_idx(codec, 0x06);
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alc_write_coef_idx(codec, 0x06, (val & ~0x00f0) | 0x0);
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/* JD */
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val = alc_read_coef_idx(codec, 0x08);
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alc_write_coef_idx(codec, 0x08, (val & ~0xfffc) | 0x0c2c);
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/* JD offset1 */
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alc_write_coef_idx(codec, 0x0a, 0xcccc);
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/* JD offset2 */
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alc_write_coef_idx(codec, 0x0b, 0xcccc);
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/* LDO1/2/3, DAC/ADC */
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alc_write_coef_idx(codec, 0x0e, 0x6fc0);
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/* JD */
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val = alc_read_coef_idx(codec, 0x0f);
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alc_write_coef_idx(codec, 0x0f, (val & ~0xf800) | 0x1000);
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/* Capless */
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val = alc_read_coef_idx(codec, 0x10);
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alc_write_coef_idx(codec, 0x10, (val & ~0xfc00) | 0x0c00);
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/* Class D test 4 */
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alc_write_coef_idx(codec, 0x3a, 0x0);
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/* IO power down directly */
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val = alc_read_coef_idx(codec, 0x0c);
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alc_write_coef_idx(codec, 0x0c, (val & ~0xfe00) | 0x0);
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/* ANC */
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alc_write_coef_idx(codec, 0x22, 0xa0c0);
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/* AGC MUX */
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val = alc_read_coefex_idx(codec, 0x53, 0x01);
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alc_write_coefex_idx(codec, 0x53, 0x01, (val & ~0x000f) | 0x0008);
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/* DAC simple content protection */
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val = alc_read_coef_idx(codec, 0x1d);
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alc_write_coef_idx(codec, 0x1d, (val & ~0x00e0) | 0x0);
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/* ADC simple content protection */
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val = alc_read_coef_idx(codec, 0x1f);
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alc_write_coef_idx(codec, 0x1f, (val & ~0x00e0) | 0x0);
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/* DAC ADC Zero Detection */
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alc_write_coef_idx(codec, 0x21, 0x8804);
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/* PLL */
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alc_write_coef_idx(codec, 0x2e, 0x2902);
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/* capless control 2 */
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alc_write_coef_idx(codec, 0x33, 0xa080);
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/* capless control 3 */
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alc_write_coef_idx(codec, 0x34, 0x3400);
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/* capless control 4 */
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alc_write_coef_idx(codec, 0x35, 0x2f3e);
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/* capless control 5 */
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alc_write_coef_idx(codec, 0x36, 0x0);
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/* class D test 2 */
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val = alc_read_coef_idx(codec, 0x38);
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alc_write_coef_idx(codec, 0x38, (val & ~0x0fff) | 0x0900);
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/* class D test 3 */
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alc_write_coef_idx(codec, 0x39, 0x110a);
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/* class D test 5 */
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val = alc_read_coef_idx(codec, 0x3b);
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alc_write_coef_idx(codec, 0x3b, (val & ~0x00f8) | 0x00d8);
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/* class D test 6 */
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alc_write_coef_idx(codec, 0x3c, 0x0014);
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/* classD OCP */
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alc_write_coef_idx(codec, 0x3d, 0xc2ba);
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/* classD pure DC test */
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val = alc_read_coef_idx(codec, 0x42);
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alc_write_coef_idx(codec, 0x42, (val & ~0x0f80) | 0x0);
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/* test mode */
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alc_write_coef_idx(codec, 0x49, 0x0);
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/* Class D DC enable */
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val = alc_read_coef_idx(codec, 0x40);
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alc_write_coef_idx(codec, 0x40, (val & ~0xf800) | 0x9800);
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/* DC offset */
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val = alc_read_coef_idx(codec, 0x42);
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alc_write_coef_idx(codec, 0x42, (val & ~0xf000) | 0x2000);
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/* Class D amp control */
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alc_write_coef_idx(codec, 0x37, 0xfc06);
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}
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static void alc283_init(struct hda_codec *codec)
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static void alc283_init(struct hda_codec *codec)
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{
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{
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struct alc_spec *spec = codec->spec;
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struct alc_spec *spec = codec->spec;
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@ -2793,6 +2876,8 @@ static void alc283_init(struct hda_codec *codec)
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bool hp_pin_sense;
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bool hp_pin_sense;
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int val;
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int val;
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alc283_restore_default_value(codec);
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if (!hp_pin)
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if (!hp_pin)
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return;
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return;
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hp_pin_sense = snd_hda_jack_detect(codec, hp_pin);
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hp_pin_sense = snd_hda_jack_detect(codec, hp_pin);
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