sh: Remove unused SH4-202 support
This early prototype of the SH4 CPU was only used in the "microdev" board that is now removed, so all of the SH4-202 supoprt can also be removed. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Link: https://lore.kernel.org/r/20230914155523.3839811-2-arnd@kernel.org Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
This commit is contained in:
Arnd Bergmann
John Paul Adrian Glaubitz
parent
3ca64d0669
commit
6c329558c1
@ -383,10 +383,6 @@ config CPU_SUBTYPE_SH7760
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bool "Support SH7760 processor"
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select CPU_SH4
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config CPU_SUBTYPE_SH4_202
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bool "Support SH4-202 processor"
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select CPU_SH4
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# SH-4A Processor Support
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config CPU_SUBTYPE_SH7723
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@ -517,7 +513,6 @@ config SH_PCLK_FREQ
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CPU_SUBTYPE_SH7263 || \
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CPU_SUBTYPE_MXG
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default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
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default "66000000" if CPU_SUBTYPE_SH4_202
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default "50000000"
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help
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This option is used to specify the peripheral clock frequency.
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@ -23,15 +23,11 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7091) += setup-sh7750.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7751) += setup-sh7750.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += setup-sh7750.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7760) += setup-sh7760.o
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obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += setup-sh4-202.o
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# Primary on-chip clocks (common)
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ifndef CONFIG_CPU_SH4A
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clock-$(CONFIG_CPU_SH4) := clock-sh4.o
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endif
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# Additional clocks by subtype
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clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o
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obj-y += $(clock-y)
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obj-$(CONFIG_PERF_EVENTS) += $(perf-y)
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@ -1,174 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* arch/sh/kernel/cpu/sh4/clock-sh4-202.c
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*
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* Additional SH4-202 support for the clock framework
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*
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* Copyright (C) 2005 Paul Mundt
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#define CPG2_FRQCR3 0xfe0a0018
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static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 };
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static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 };
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static unsigned long emi_clk_recalc(struct clk *clk)
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{
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int idx = __raw_readl(CPG2_FRQCR3) & 0x0007;
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return clk->parent->rate / frqcr3_divisors[idx];
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}
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static inline int frqcr3_lookup(struct clk *clk, unsigned long rate)
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{
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int divisor = clk->parent->rate / rate;
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int i;
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for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++)
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if (frqcr3_divisors[i] == divisor)
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return frqcr3_values[i];
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/* Safe fallback */
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return 5;
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}
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static struct sh_clk_ops sh4202_emi_clk_ops = {
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.recalc = emi_clk_recalc,
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};
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static struct clk sh4202_emi_clk = {
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh4202_emi_clk_ops,
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};
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static unsigned long femi_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readl(CPG2_FRQCR3) >> 3) & 0x0007;
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return clk->parent->rate / frqcr3_divisors[idx];
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}
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static struct sh_clk_ops sh4202_femi_clk_ops = {
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.recalc = femi_clk_recalc,
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};
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static struct clk sh4202_femi_clk = {
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh4202_femi_clk_ops,
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};
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static void shoc_clk_init(struct clk *clk)
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{
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int i;
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/*
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* For some reason, the shoc_clk seems to be set to some really
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* insane value at boot (values outside of the allowable frequency
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* range for instance). We deal with this by scaling it back down
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* to something sensible just in case.
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*
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* Start scaling from the high end down until we find something
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* that passes rate verification..
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*/
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for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) {
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int divisor = frqcr3_divisors[i];
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if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0)
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break;
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}
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WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */
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}
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static unsigned long shoc_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readl(CPG2_FRQCR3) >> 6) & 0x0007;
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return clk->parent->rate / frqcr3_divisors[idx];
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}
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static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
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{
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struct clk *bclk = clk_get(NULL, "bus_clk");
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unsigned long bclk_rate = clk_get_rate(bclk);
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clk_put(bclk);
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if (rate > bclk_rate)
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return 1;
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if (rate > 66000000)
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return 1;
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return 0;
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}
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static int shoc_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long frqcr3;
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unsigned int tmp;
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/* Make sure we have something sensible to switch to */
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if (shoc_clk_verify_rate(clk, rate) != 0)
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return -EINVAL;
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tmp = frqcr3_lookup(clk, rate);
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frqcr3 = __raw_readl(CPG2_FRQCR3);
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frqcr3 &= ~(0x0007 << 6);
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frqcr3 |= tmp << 6;
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__raw_writel(frqcr3, CPG2_FRQCR3);
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clk->rate = clk->parent->rate / frqcr3_divisors[tmp];
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return 0;
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}
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static struct sh_clk_ops sh4202_shoc_clk_ops = {
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.init = shoc_clk_init,
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.recalc = shoc_clk_recalc,
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.set_rate = shoc_clk_set_rate,
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};
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static struct clk sh4202_shoc_clk = {
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh4202_shoc_clk_ops,
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};
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static struct clk *sh4202_onchip_clocks[] = {
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&sh4202_emi_clk,
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&sh4202_femi_clk,
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&sh4202_shoc_clk,
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk),
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CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk),
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CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk),
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};
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int __init arch_clk_init(void)
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{
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) {
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struct clk *clkp = sh4202_onchip_clocks[i];
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clkp->parent = clk;
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ret |= clk_register(clkp);
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}
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clk_put(clk);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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return ret;
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}
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@ -1,139 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* SH4-202 Setup
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*
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* Copyright (C) 2006 Paul Mundt
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* Copyright (C) 2009 Magnus Damm
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <linux/sh_intc.h>
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#include <linux/io.h>
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#include <asm/platform_early.h>
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static struct plat_sci_port scif0_platform_data = {
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.scscr = SCSCR_REIE,
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.type = PORT_SCIF,
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};
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static struct resource scif0_resources[] = {
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DEFINE_RES_MEM(0xffe80000, 0x100),
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DEFINE_RES_IRQ(evt2irq(0x700)),
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DEFINE_RES_IRQ(evt2irq(0x720)),
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DEFINE_RES_IRQ(evt2irq(0x760)),
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DEFINE_RES_IRQ(evt2irq(0x740)),
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.resource = scif0_resources,
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.num_resources = ARRAY_SIZE(scif0_resources),
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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static struct sh_timer_config tmu0_platform_data = {
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.channels_mask = 7,
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};
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static struct resource tmu0_resources[] = {
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DEFINE_RES_MEM(0xffd80000, 0x30),
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DEFINE_RES_IRQ(evt2irq(0x400)),
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DEFINE_RES_IRQ(evt2irq(0x420)),
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DEFINE_RES_IRQ(evt2irq(0x440)),
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};
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static struct platform_device tmu0_device = {
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.name = "sh-tmu",
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.id = 0,
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.dev = {
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.platform_data = &tmu0_platform_data,
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},
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.resource = tmu0_resources,
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.num_resources = ARRAY_SIZE(tmu0_resources),
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};
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static struct platform_device *sh4202_devices[] __initdata = {
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&scif0_device,
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&tmu0_device,
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};
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static int __init sh4202_devices_setup(void)
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{
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return platform_add_devices(sh4202_devices,
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ARRAY_SIZE(sh4202_devices));
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}
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arch_initcall(sh4202_devices_setup);
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static struct platform_device *sh4202_early_devices[] __initdata = {
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&scif0_device,
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&tmu0_device,
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};
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void __init plat_early_device_setup(void)
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{
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sh_early_platform_add_devices(sh4202_early_devices,
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ARRAY_SIZE(sh4202_early_devices));
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}
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
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HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(HUDI, 0x600),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
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INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
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INTC_VECT(RTC, 0x4c0),
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INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
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INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
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INTC_VECT(WDT, 0x560),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
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{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
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{ 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } },
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{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL,
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NULL, prio_registers, NULL);
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static struct intc_vect vectors_irlm[] __initdata = {
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INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
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INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
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};
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static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL,
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NULL, prio_registers, NULL);
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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}
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#define INTC_ICR 0xffd00000UL
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#define INTC_ICR_IRLM (1<<7)
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void __init plat_irq_setup_pins(int mode)
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{
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switch (mode) {
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case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
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__raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
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register_intc_controller(&intc_desc_irlm);
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break;
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default:
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BUG();
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}
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}
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