arm64: dts: ls1028a-rdb: sort nodes alphabetically by label
In preparation for this board's device tree synchronization with U-Boot, we must find a common node ordering pattern. Alphabetical sounds about right. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -102,6 +102,48 @@
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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&enetc_mdio_pf3 {
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sgmii_phy0: ethernet-phy@2 {
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reg = <0x2>;
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};
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/* VSC8514 QSGMII quad PHY */
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qsgmii_phy0: ethernet-phy@10 {
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reg = <0x10>;
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};
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qsgmii_phy1: ethernet-phy@11 {
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reg = <0x11>;
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};
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qsgmii_phy2: ethernet-phy@12 {
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reg = <0x12>;
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};
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qsgmii_phy3: ethernet-phy@13 {
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reg = <0x13>;
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};
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};
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&enetc_port0 {
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phy-handle = <&sgmii_phy0>;
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phy-mode = "sgmii";
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managed = "in-band-status";
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status = "okay";
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};
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&enetc_port2 {
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status = "okay";
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};
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&esdhc {
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sd-uhs-sdr104;
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sd-uhs-sdr50;
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@ -188,48 +230,6 @@
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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&enetc_mdio_pf3 {
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sgmii_phy0: ethernet-phy@2 {
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reg = <0x2>;
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};
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/* VSC8514 QSGMII quad PHY */
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qsgmii_phy0: ethernet-phy@10 {
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reg = <0x10>;
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};
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qsgmii_phy1: ethernet-phy@11 {
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reg = <0x11>;
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};
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qsgmii_phy2: ethernet-phy@12 {
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reg = <0x12>;
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};
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qsgmii_phy3: ethernet-phy@13 {
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reg = <0x13>;
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};
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};
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&enetc_port0 {
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phy-handle = <&sgmii_phy0>;
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phy-mode = "sgmii";
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managed = "in-band-status";
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status = "okay";
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};
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&enetc_port2 {
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status = "okay";
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};
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&mscc_felix {
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status = "okay";
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};
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