drm/radeon/pm: move pm handling into the asic specific code
We need more control over the ordering of dpm init with respect to the rest of the asic. Specifically, the SMC has to be initialized before the rlc and cg/pg. The pm code currently initializes late in the driver, but we need it to happen much earlier so move pm handling into the asic specific callbacks. This makes dpm more reliable and makes clockgating work properly on CIK parts and should help on SI parts as well. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -325,6 +325,8 @@ int r420_resume(struct radeon_device *rdev)
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/* Initialize surface registers */
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radeon_surface_init(rdev);
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radeon_pm_resume(rdev);
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rdev->accel_working = true;
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r = r420_startup(rdev);
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if (r) {
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@ -335,6 +337,7 @@ int r420_resume(struct radeon_device *rdev)
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int r420_suspend(struct radeon_device *rdev)
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{
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radeon_pm_suspend(rdev);
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r420_cp_errata_fini(rdev);
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r100_cp_disable(rdev);
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radeon_wb_disable(rdev);
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@ -348,6 +351,7 @@ int r420_suspend(struct radeon_device *rdev)
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void r420_fini(struct radeon_device *rdev)
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{
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radeon_pm_fini(rdev);
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r100_cp_fini(rdev);
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radeon_wb_fini(rdev);
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radeon_ib_pool_fini(rdev);
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@ -444,6 +448,9 @@ int r420_init(struct radeon_device *rdev)
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}
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r420_set_reg_safe(rdev);
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/* Initialize power management */
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radeon_pm_init(rdev);
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rdev->accel_working = true;
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r = r420_startup(rdev);
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if (r) {
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