EDAC/amd64: Use new AMD Address Translation Library
Remove old address translation code and use the new AMD Address Translation Library. Use "imply" in Kconfig so that the "AMD_ATL" config option takes the value of "EDAC_AMD64" as its default. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20240123041401.79812-3-yazen.ghannam@amd.com
This commit is contained in:
Yazen Ghannam
Borislav Petkov (AMD)
parent
3f3174996b
commit
6c9058f490
@ -78,6 +78,7 @@ config EDAC_GHES
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config EDAC_AMD64
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tristate "AMD64 (Opteron, Athlon64)"
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depends on AMD_NB && EDAC_DECODE_MCE
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imply AMD_ATL
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help
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Support for error detection and correction of DRAM ECC errors on
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the AMD64 families (>= K8) of memory controllers.
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@ -1,4 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/ras.h>
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#include "amd64_edac.h"
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#include <asm/amd_nb.h>
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@ -1051,281 +1052,6 @@ static int fixup_node_id(int node_id, struct mce *m)
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return nid - gpu_node_map.base_node_id + 1;
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}
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/* Protect the PCI config register pairs used for DF indirect access. */
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static DEFINE_MUTEX(df_indirect_mutex);
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/*
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* Data Fabric Indirect Access uses FICAA/FICAD.
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*
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* Fabric Indirect Configuration Access Address (FICAA): Constructed based
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* on the device's Instance Id and the PCI function and register offset of
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* the desired register.
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*
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* Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
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* and FICAD HI registers but so far we only need the LO register.
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*
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* Use Instance Id 0xFF to indicate a broadcast read.
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*/
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#define DF_BROADCAST 0xFF
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static int __df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
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{
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struct pci_dev *F4;
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u32 ficaa;
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int err = -ENODEV;
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if (node >= amd_nb_num())
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goto out;
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F4 = node_to_amd_nb(node)->link;
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if (!F4)
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goto out;
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ficaa = (instance_id == DF_BROADCAST) ? 0 : 1;
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ficaa |= reg & 0x3FC;
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ficaa |= (func & 0x7) << 11;
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ficaa |= instance_id << 16;
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mutex_lock(&df_indirect_mutex);
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err = pci_write_config_dword(F4, 0x5C, ficaa);
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if (err) {
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pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
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goto out_unlock;
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}
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err = pci_read_config_dword(F4, 0x98, lo);
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if (err)
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pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);
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out_unlock:
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mutex_unlock(&df_indirect_mutex);
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out:
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return err;
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}
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static int df_indirect_read_instance(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
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{
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return __df_indirect_read(node, func, reg, instance_id, lo);
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}
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static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo)
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{
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return __df_indirect_read(node, func, reg, DF_BROADCAST, lo);
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}
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struct addr_ctx {
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u64 ret_addr;
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u32 tmp;
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u16 nid;
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u8 inst_id;
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};
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static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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{
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u64 dram_base_addr, dram_limit_addr, dram_hole_base;
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u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
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u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
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u8 intlv_addr_sel, intlv_addr_bit;
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u8 num_intlv_bits, hashed_bit;
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u8 lgcy_mmio_hole_en, base = 0;
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u8 cs_mask, cs_id = 0;
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bool hash_enabled = false;
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struct addr_ctx ctx;
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memset(&ctx, 0, sizeof(ctx));
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/* Start from the normalized address */
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ctx.ret_addr = norm_addr;
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ctx.nid = nid;
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ctx.inst_id = umc;
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/* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
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if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp))
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goto out_err;
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/* Remove HiAddrOffset from normalized address, if enabled: */
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if (ctx.tmp & BIT(0)) {
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u64 hi_addr_offset = (ctx.tmp & GENMASK_ULL(31, 20)) << 8;
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if (norm_addr >= hi_addr_offset) {
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ctx.ret_addr -= hi_addr_offset;
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base = 1;
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}
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}
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/* Read D18F0x110 (DramBaseAddress). */
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if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &ctx.tmp))
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goto out_err;
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/* Check if address range is valid. */
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if (!(ctx.tmp & BIT(0))) {
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pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
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__func__, ctx.tmp);
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goto out_err;
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}
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lgcy_mmio_hole_en = ctx.tmp & BIT(1);
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intlv_num_chan = (ctx.tmp >> 4) & 0xF;
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intlv_addr_sel = (ctx.tmp >> 8) & 0x7;
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dram_base_addr = (ctx.tmp & GENMASK_ULL(31, 12)) << 16;
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/* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
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if (intlv_addr_sel > 3) {
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pr_err("%s: Invalid interleave address select %d.\n",
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__func__, intlv_addr_sel);
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goto out_err;
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}
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/* Read D18F0x114 (DramLimitAddress). */
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if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp))
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goto out_err;
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intlv_num_sockets = (ctx.tmp >> 8) & 0x1;
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intlv_num_dies = (ctx.tmp >> 10) & 0x3;
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dram_limit_addr = ((ctx.tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
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intlv_addr_bit = intlv_addr_sel + 8;
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/* Re-use intlv_num_chan by setting it equal to log2(#channels) */
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switch (intlv_num_chan) {
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case 0: intlv_num_chan = 0; break;
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case 1: intlv_num_chan = 1; break;
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case 3: intlv_num_chan = 2; break;
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case 5: intlv_num_chan = 3; break;
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case 7: intlv_num_chan = 4; break;
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case 8: intlv_num_chan = 1;
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hash_enabled = true;
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break;
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default:
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pr_err("%s: Invalid number of interleaved channels %d.\n",
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__func__, intlv_num_chan);
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goto out_err;
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}
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num_intlv_bits = intlv_num_chan;
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if (intlv_num_dies > 2) {
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pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
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__func__, intlv_num_dies);
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goto out_err;
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}
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num_intlv_bits += intlv_num_dies;
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/* Add a bit if sockets are interleaved. */
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num_intlv_bits += intlv_num_sockets;
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/* Assert num_intlv_bits <= 4 */
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if (num_intlv_bits > 4) {
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pr_err("%s: Invalid interleave bits %d.\n",
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__func__, num_intlv_bits);
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goto out_err;
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}
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if (num_intlv_bits > 0) {
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u64 temp_addr_x, temp_addr_i, temp_addr_y;
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u8 die_id_bit, sock_id_bit, cs_fabric_id;
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/*
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* Read FabricBlockInstanceInformation3_CS[BlockFabricID].
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* This is the fabric id for this coherent slave. Use
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* umc/channel# as instance id of the coherent slave
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* for FICAA.
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*/
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if (df_indirect_read_instance(nid, 0, 0x50, umc, &ctx.tmp))
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goto out_err;
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cs_fabric_id = (ctx.tmp >> 8) & 0xFF;
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die_id_bit = 0;
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/* If interleaved over more than 1 channel: */
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if (intlv_num_chan) {
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die_id_bit = intlv_num_chan;
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cs_mask = (1 << die_id_bit) - 1;
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cs_id = cs_fabric_id & cs_mask;
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}
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sock_id_bit = die_id_bit;
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/* Read D18F1x208 (SystemFabricIdMask). */
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if (intlv_num_dies || intlv_num_sockets)
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if (df_indirect_read_broadcast(nid, 1, 0x208, &ctx.tmp))
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goto out_err;
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/* If interleaved over more than 1 die. */
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if (intlv_num_dies) {
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sock_id_bit = die_id_bit + intlv_num_dies;
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die_id_shift = (ctx.tmp >> 24) & 0xF;
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die_id_mask = (ctx.tmp >> 8) & 0xFF;
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cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
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}
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/* If interleaved over more than 1 socket. */
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if (intlv_num_sockets) {
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socket_id_shift = (ctx.tmp >> 28) & 0xF;
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socket_id_mask = (ctx.tmp >> 16) & 0xFF;
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cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
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}
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/*
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* The pre-interleaved address consists of XXXXXXIIIYYYYY
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* where III is the ID for this CS, and XXXXXXYYYYY are the
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* address bits from the post-interleaved address.
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* "num_intlv_bits" has been calculated to tell us how many "I"
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* bits there are. "intlv_addr_bit" tells us how many "Y" bits
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* there are (where "I" starts).
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*/
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temp_addr_y = ctx.ret_addr & GENMASK_ULL(intlv_addr_bit - 1, 0);
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temp_addr_i = (cs_id << intlv_addr_bit);
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temp_addr_x = (ctx.ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
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ctx.ret_addr = temp_addr_x | temp_addr_i | temp_addr_y;
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}
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/* Add dram base address */
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ctx.ret_addr += dram_base_addr;
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/* If legacy MMIO hole enabled */
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if (lgcy_mmio_hole_en) {
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if (df_indirect_read_broadcast(nid, 0, 0x104, &ctx.tmp))
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goto out_err;
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dram_hole_base = ctx.tmp & GENMASK(31, 24);
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if (ctx.ret_addr >= dram_hole_base)
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ctx.ret_addr += (BIT_ULL(32) - dram_hole_base);
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}
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if (hash_enabled) {
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/* Save some parentheses and grab ls-bit at the end. */
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hashed_bit = (ctx.ret_addr >> 12) ^
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(ctx.ret_addr >> 18) ^
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(ctx.ret_addr >> 21) ^
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(ctx.ret_addr >> 30) ^
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cs_id;
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hashed_bit &= BIT(0);
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if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0)))
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ctx.ret_addr ^= BIT(intlv_addr_bit);
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}
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/* Is calculated system address is above DRAM limit address? */
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if (ctx.ret_addr > dram_limit_addr)
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goto out_err;
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*sys_addr = ctx.ret_addr;
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return 0;
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out_err:
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return -EINVAL;
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}
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static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
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/*
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@ -3073,9 +2799,10 @@ static void decode_umc_error(int node_id, struct mce *m)
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{
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u8 ecc_type = (m->status >> 45) & 0x3;
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struct mem_ctl_info *mci;
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unsigned long sys_addr;
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struct amd64_pvt *pvt;
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struct atl_err a_err;
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struct err_info err;
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u64 sys_addr;
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node_id = fixup_node_id(node_id, m);
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@ -3106,7 +2833,12 @@ static void decode_umc_error(int node_id, struct mce *m)
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pvt->ops->get_err_info(m, &err);
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if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) {
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a_err.addr = m->addr;
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a_err.ipid = m->ipid;
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a_err.cpu = m->extcpu;
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sys_addr = amd_convert_umc_mca_addr_to_sys_addr(&a_err);
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if (IS_ERR_VALUE(sys_addr)) {
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err.err_code = ERR_NORM_ADDR;
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goto log_error;
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}
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