media: ov5640: Rework CSI-2 clock tree
Re-work the ov5640_set_mipi_pclk() function to calculate the PLL configuration using the pixel_rate and link_freq values set at s_fmt time. Rework the DVP clock mode settings to calculate the pixel clock internally and remove the assumption on the 16bpp format. Tested in MIPI CSI-2 mode with 1 and 2 data lanes with: - all the sensor supported resolutions in UYVY, RGB565 and MJPEG formats. - resolutions >= 1280x720 in RAW Bayer format. - resolutions < 1280x720 in RGB888 format. [Rework pclk_period and link_freq computation] Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hugues Fruchet <hugues.fruchet@st.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Jacopo Mondi
Mauro Carvalho Chehab
parent
3c28588f35
commit
6c957ed73e
@ -90,6 +90,7 @@
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#define OV5640_REG_POLARITY_CTRL00 0x4740
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#define OV5640_REG_MIPI_CTRL00 0x4800
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#define OV5640_REG_DEBUG_MODE 0x4814
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#define OV5640_REG_PCLK_PERIOD 0x4837
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#define OV5640_REG_ISP_FORMAT_MUX_CTRL 0x501f
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#define OV5640_REG_PRE_ISP_TEST_SET1 0x503d
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#define OV5640_REG_SDE_CTRL0 0x5580
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@ -926,20 +927,10 @@ static int ov5640_mod_reg(struct ov5640_dev *sensor, u16 reg,
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* +-----+-----+
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* +------------> PCLK
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*
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* This is deviating from the datasheet at least for the register
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* 0x3108, since it's said here that the PCLK would be clocked from
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* the PLL.
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*
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* There seems to be also (unverified) constraints:
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* There seems to be also constraints:
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* - the PLL pre-divider output rate should be in the 4-27MHz range
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* - the PLL multiplier output rate should be in the 500-1000MHz range
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* - PCLK >= SCLK * 2 in YUV, >= SCLK in Raw or JPEG
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*
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* In the two latter cases, these constraints are met since our
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* factors are hardcoded. If we were to change that, we would need to
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* take this into account. The only varying parts are the PLL
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* multiplier and the system clock divider, which are shared between
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* all these clocks so won't cause any issue.
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*/
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/*
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@ -958,13 +949,6 @@ static int ov5640_mod_reg(struct ov5640_dev *sensor, u16 reg,
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#define OV5640_SYSDIV_MIN 1
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#define OV5640_SYSDIV_MAX 16
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/*
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* Hardcode these values for scaler and non-scaler modes.
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* FIXME: to be re-calcualted for 1 data lanes setups
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*/
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#define OV5640_MIPI_DIV_PCLK 2
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#define OV5640_MIPI_DIV_SCLK 1
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/*
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* This is supposed to be ranging from 1 to 2, but the value is always
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* set to 2 in the vendor kernels.
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@ -1074,70 +1058,83 @@ out:
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/*
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* ov5640_set_mipi_pclk() - Calculate the clock tree configuration values
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* for the MIPI CSI-2 output.
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*
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* @rate: The requested bandwidth per lane in bytes per second.
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* 'Bandwidth Per Lane' is calculated as:
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* bpl = HTOT * VTOT * FPS * bpp / num_lanes;
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*
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* This function use the requested bandwidth to calculate:
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* - sample_rate = bpl / (bpp / num_lanes);
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* = bpl / (PLL_RDIV * BIT_DIV * PCLK_DIV * MIPI_DIV / num_lanes);
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*
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* - mipi_sclk = bpl / MIPI_DIV / 2; ( / 2 is for CSI-2 DDR)
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*
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* with these fixed parameters:
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* PLL_RDIV = 2;
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* BIT_DIVIDER = 2; (MIPI_BIT_MODE == 8 ? 2 : 2,5);
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* PCLK_DIV = 1;
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*
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* The MIPI clock generation differs for modes that use the scaler and modes
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* that do not. In case the scaler is in use, the MIPI_SCLK generates the MIPI
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* BIT CLk, and thus:
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*
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* - mipi_sclk = bpl / MIPI_DIV / 2;
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* MIPI_DIV = 1;
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*
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* For modes that do not go through the scaler, the MIPI BIT CLOCK is generated
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* from the pixel clock, and thus:
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*
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* - sample_rate = bpl / (bpp / num_lanes);
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* = bpl / (2 * 2 * 1 * MIPI_DIV / num_lanes);
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* = bpl / (4 * MIPI_DIV / num_lanes);
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* - MIPI_DIV = bpp / (4 * num_lanes);
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*
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* FIXME: this have been tested with 16bpp and 2 lanes setup only.
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* MIPI_DIV is fixed to value 2, but it -might- be changed according to the
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* above formula for setups with 1 lane or image formats with different bpp.
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*
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* FIXME: this deviates from the sensor manual documentation which is quite
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* thin on the MIPI clock tree generation part.
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*/
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static int ov5640_set_mipi_pclk(struct ov5640_dev *sensor,
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unsigned long rate)
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static int ov5640_set_mipi_pclk(struct ov5640_dev *sensor)
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{
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const struct ov5640_mode_info *mode = sensor->current_mode;
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u8 bit_div, mipi_div, pclk_div, sclk_div, sclk2x_div, root_div;
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u8 prediv, mult, sysdiv;
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u8 mipi_div;
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unsigned long link_freq;
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unsigned long sysclk;
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u8 pclk_period;
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u32 sample_rate;
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u32 num_lanes;
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int ret;
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/* Use the link freq computed at ov5640_update_pixel_rate() time. */
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link_freq = sensor->current_link_freq;
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/*
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* 1280x720 is reported to use 'SUBSAMPLING' only,
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* but according to the sensor manual it goes through the
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* scaler before subsampling.
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* - mipi_div - Additional divider for the MIPI lane clock.
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*
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* Higher link frequencies would make sysclk > 1GHz.
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* Keep the sysclk low and do not divide in the MIPI domain.
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*/
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if (mode->dn_mode == SCALING ||
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(mode->id == OV5640_MODE_720P_1280_720))
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mipi_div = OV5640_MIPI_DIV_SCLK;
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if (link_freq > OV5640_LINK_RATE_MAX)
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mipi_div = 1;
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else
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mipi_div = OV5640_MIPI_DIV_PCLK;
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mipi_div = 2;
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ov5640_calc_sys_clk(sensor, rate, &prediv, &mult, &sysdiv);
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sysclk = link_freq * mipi_div;
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ov5640_calc_sys_clk(sensor, sysclk, &prediv, &mult, &sysdiv);
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ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL0,
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0x0f, OV5640_PLL_CTRL0_MIPI_MODE_8BIT);
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/*
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* Adjust PLL parameters to maintain the MIPI_SCLK-to-PCLK ratio.
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*
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* - root_div = 2 (fixed)
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* - bit_div : MIPI 8-bit = 2; MIPI 10-bit = 2.5
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* - pclk_div = 1 (fixed)
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* - p_div = (2 lanes ? mipi_div : 2 * mipi_div)
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*
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* This results in the following MIPI_SCLK depending on the number
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* of lanes:
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*
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* - 2 lanes: MIPI_SCLK = (4 or 5) * PCLK
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* - 1 lanes: MIPI_SCLK = (8 or 10) * PCLK
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*/
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root_div = OV5640_PLL_CTRL3_PLL_ROOT_DIV_2;
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bit_div = OV5640_PLL_CTRL0_MIPI_MODE_8BIT;
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pclk_div = ilog2(OV5640_PCLK_ROOT_DIV);
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ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1,
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0xff, sysdiv << 4 | mipi_div);
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/*
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* Scaler clock:
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* - YUV: PCLK >= 2 * SCLK
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* - RAW or JPEG: PCLK >= SCLK
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* - sclk2x_div = sclk_div / 2
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*/
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sclk_div = ilog2(OV5640_SCLK_ROOT_DIV);
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sclk2x_div = ilog2(OV5640_SCLK2X_ROOT_DIV);
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/*
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* Set the pixel clock period expressed in ns with 1-bit decimal
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* (0x01=0.5ns).
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*
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* The register is very briefly documented. In the OV5645 datasheet it
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* is described as (2 * pclk period), and from testing it seems the
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* actual definition is 2 * 8-bit sample period.
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*
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* 2 * sample_period = (mipi_clk * 2 * num_lanes / bpp) * (bpp / 8) / 2
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*/
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num_lanes = sensor->ep.bus.mipi_csi2.num_data_lanes;
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sample_rate = (link_freq * mipi_div * num_lanes * 2) / 16;
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pclk_period = 2000000000UL / sample_rate;
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/* Program the clock tree registers. */
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ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL0, 0x0f, bit_div);
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if (ret)
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return ret;
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ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1, 0xff,
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(sysdiv << 4) | mipi_div);
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if (ret)
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return ret;
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@ -1145,13 +1142,27 @@ static int ov5640_set_mipi_pclk(struct ov5640_dev *sensor,
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if (ret)
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return ret;
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ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL3,
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0x1f, OV5640_PLL_CTRL3_PLL_ROOT_DIV_2 | prediv);
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ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL3, 0x1f,
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root_div | prediv);
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if (ret)
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return ret;
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return ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER,
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0x30, OV5640_PLL_SYS_ROOT_DIVIDER_BYPASS);
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ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, 0x3f,
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(pclk_div << 4) | (sclk2x_div << 2) | sclk_div);
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if (ret)
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return ret;
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return ov5640_write_reg(sensor, OV5640_REG_PCLK_PERIOD, pclk_period);
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}
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static u32 ov5640_calc_pixel_rate(struct ov5640_dev *sensor)
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{
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u32 rate;
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rate = sensor->current_mode->vtot * sensor->current_mode->htot;
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rate *= ov5640_framerates[sensor->current_fr];
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return rate;
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}
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static unsigned long ov5640_calc_pclk(struct ov5640_dev *sensor,
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@ -1171,11 +1182,16 @@ static unsigned long ov5640_calc_pclk(struct ov5640_dev *sensor,
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return _rate / *pll_rdiv / *bit_div / *pclk_div;
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}
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static int ov5640_set_dvp_pclk(struct ov5640_dev *sensor, unsigned long rate)
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static int ov5640_set_dvp_pclk(struct ov5640_dev *sensor)
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{
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u8 prediv, mult, sysdiv, pll_rdiv, bit_div, pclk_div;
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u32 rate;
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int ret;
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rate = ov5640_calc_pixel_rate(sensor);
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rate *= ov5640_code_to_bpp(sensor->fmt.code);
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rate /= sensor->ep.bus.parallel.bus_width;
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ov5640_calc_pclk(sensor, rate, &prediv, &mult, &sysdiv, &pll_rdiv,
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&bit_div, &pclk_div);
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@ -1700,16 +1716,6 @@ ov5640_find_mode(struct ov5640_dev *sensor, enum ov5640_frame_rate fr,
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return mode;
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}
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static u64 ov5640_calc_pixel_rate(struct ov5640_dev *sensor)
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{
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u64 rate;
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rate = sensor->current_mode->vtot * sensor->current_mode->htot;
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rate *= ov5640_framerates[sensor->current_fr];
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return rate;
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}
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/*
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* sensor changes between scaling and subsampling, go through
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* exposure calculation
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@ -1891,7 +1897,6 @@ static int ov5640_set_mode(struct ov5640_dev *sensor)
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enum ov5640_downsize_mode dn_mode, orig_dn_mode;
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bool auto_gain = sensor->ctrls.auto_gain->val == 1;
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bool auto_exp = sensor->ctrls.auto_exp->val == V4L2_EXPOSURE_AUTO;
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unsigned long rate;
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int ret;
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dn_mode = mode->dn_mode;
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@ -1910,19 +1915,10 @@ static int ov5640_set_mode(struct ov5640_dev *sensor)
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goto restore_auto_gain;
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}
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/*
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* All the formats we support have 16 bits per pixel, seems to require
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* the same rate than YUV, so we can just use 16 bpp all the time.
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*/
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rate = ov5640_calc_pixel_rate(sensor) * 16;
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if (ov5640_is_csi2(sensor)) {
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rate = rate / sensor->ep.bus.mipi_csi2.num_data_lanes;
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ret = ov5640_set_mipi_pclk(sensor, rate);
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} else {
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rate = rate / sensor->ep.bus.parallel.bus_width;
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ret = ov5640_set_dvp_pclk(sensor, rate);
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}
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if (ov5640_is_csi2(sensor))
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ret = ov5640_set_mipi_pclk(sensor);
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else
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ret = ov5640_set_dvp_pclk(sensor);
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if (ret < 0)
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return 0;
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