drm/i915: Remove I915_READ64 and I915_READ64_32x2
Now that all their users are gone we can remove the macros and accompanying duplicated comment. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Suggested-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190610120608.15477-6-tvrtko.ursulin@linux.intel.com
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@ -2851,24 +2851,6 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
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#define I915_READ_NOTRACE(reg__) __I915_REG_OP(read_notrace, dev_priv, (reg__))
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#define I915_WRITE_NOTRACE(reg__, val__) __I915_REG_OP(write_notrace, dev_priv, (reg__), (val__))
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/* Be very careful with read/write 64-bit values. On 32-bit machines, they
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* will be implemented using 2 32-bit writes in an arbitrary order with
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* an arbitrary delay between them. This can cause the hardware to
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* act upon the intermediate value, possibly leading to corruption and
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* machine death. For this reason we do not support I915_WRITE64, or
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* dev_priv->uncore.funcs.mmio_writeq.
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*
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* When reading a 64-bit value as two 32-bit values, the delay may cause
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* the two reads to mismatch, e.g. a timestamp overflowing. Also note that
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* occasionally a 64-bit register does not actualy support a full readq
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* and must be read using two 32-bit reads.
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*
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* You have been warned.
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*/
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#define I915_READ64(reg__) __I915_REG_OP(read64, dev_priv, (reg__))
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#define I915_READ64_2x32(lower_reg__, upper_reg__) \
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__I915_REG_OP(read64_2x32, dev_priv, (lower_reg__), (upper_reg__))
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#define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
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#define POSTING_READ16(reg__) __I915_REG_OP(posting_read16, dev_priv, (reg__))
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