ARM: ixp4xx: Delete Coyote and IXDPG425 boardfiles
These boards are replaced with the corresponding device trees. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
73d04ca5f4
commit
6dc9b80c2a
@ -17,14 +17,6 @@ config MACH_IXP4XX_OF
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help
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Say 'Y' here to support Device Tree-based IXP4xx platforms.
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config ARCH_ADI_COYOTE
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bool "Coyote"
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depends on IXP4XX_PCI_LEGACY
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help
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Say 'Y' here if you want your kernel to support the ADI
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Engineering Coyote Gateway Reference Platform. For more
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information on this platform, see <file:Documentation/arm/ixp4xx.rst>.
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config MACH_GATEWAY7001
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bool "Gateway 7001"
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depends on IXP4XX_PCI_LEGACY
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@ -33,14 +25,6 @@ config MACH_GATEWAY7001
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7001 Access Point. For more information on this platform,
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see http://openwrt.org
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config MACH_IXDPG425
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bool "IXDPG425"
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depends on IXP4XX_PCI_LEGACY
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help
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Say 'Y' here if you want your kernel to support Intel's
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IXDPG425 Development Platform (Also known as Montajade).
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For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>.
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config MACH_GORAMO_MLR
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bool "GORAMO Multi Link Router"
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help
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@ -9,16 +9,12 @@ obj-pci-n :=
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# Device tree platform
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obj-pci-$(CONFIG_MACH_IXP4XX_OF) += ixp4xx-of.o
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obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
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obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
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obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
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obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
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obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
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obj-y += common.o
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obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
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obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
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obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
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obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
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obj-$(CONFIG_MACH_FSG) += fsg-setup.o
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@ -1,62 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arm/mach-ixp4xx/coyote-pci.c
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*
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* PCI setup routines for ADI Engineering Coyote platform
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*
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* Copyright (C) 2002 Jungo Software Technologies.
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* Copyright (C) 2003 MontaVista Softwrae, Inc.
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*
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* Maintainer: Deepak Saxena <dsaxena@mvista.com>
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/mach-types.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/pci.h>
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#include "irqs.h"
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#define SLOT0_DEVID 14
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#define SLOT1_DEVID 15
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/* PCI controller GPIO to IRQ pin mappings */
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#define SLOT0_INTA 6
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#define SLOT1_INTA 11
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void __init coyote_pci_preinit(void)
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{
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irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
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ixp4xx_pci_preinit();
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}
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static int __init coyote_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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if (slot == SLOT0_DEVID)
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return IXP4XX_GPIO_IRQ(SLOT0_INTA);
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else if (slot == SLOT1_DEVID)
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return IXP4XX_GPIO_IRQ(SLOT1_INTA);
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else return -1;
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}
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struct hw_pci coyote_pci __initdata = {
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.nr_controllers = 1,
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.ops = &ixp4xx_ops,
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.preinit = coyote_pci_preinit,
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.setup = ixp4xx_setup,
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.map_irq = coyote_map_irq,
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};
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int __init coyote_pci_init(void)
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{
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if (machine_is_adi_coyote())
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pci_common_init(&coyote_pci);
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return 0;
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}
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subsys_initcall(coyote_pci_init);
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@ -1,144 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* arch/arm/mach-ixp4xx/coyote-setup.c
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*
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* Board setup for ADI Engineering and IXDGP425 boards
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*
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* Copyright (C) 2003-2005 MontaVista Software, Inc.
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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#include <linux/serial_8250.h>
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#include <asm/types.h>
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#include <asm/setup.h>
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#include <asm/memory.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include "irqs.h"
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#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
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#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
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#define COYOTE_IDE_REGION_SIZE 0x1000
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#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
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#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
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#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2
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#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
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static struct flash_platform_data coyote_flash_data = {
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.map_name = "cfi_probe",
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.width = 2,
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};
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static struct resource coyote_flash_resource = {
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device coyote_flash = {
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.name = "IXP4XX-Flash",
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.id = 0,
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.dev = {
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.platform_data = &coyote_flash_data,
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},
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.num_resources = 1,
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.resource = &coyote_flash_resource,
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};
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static struct resource coyote_uart_resource = {
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.start = IXP4XX_UART2_BASE_PHYS,
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.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
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.flags = IORESOURCE_MEM,
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};
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static struct plat_serial8250_port coyote_uart_data[] = {
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{
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.mapbase = IXP4XX_UART2_BASE_PHYS,
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.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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.irq = IRQ_IXP4XX_UART2,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = IXP4XX_UART_XTAL,
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},
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{ },
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};
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static struct platform_device coyote_uart = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = coyote_uart_data,
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},
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.num_resources = 1,
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.resource = &coyote_uart_resource,
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};
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static struct platform_device *coyote_devices[] __initdata = {
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&coyote_flash,
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&coyote_uart
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};
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static void __init coyote_init(void)
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{
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ixp4xx_sys_init();
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coyote_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
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coyote_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
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*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
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*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
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if (machine_is_ixdpg425()) {
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coyote_uart_data[0].membase =
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(char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET);
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coyote_uart_data[0].mapbase = IXP4XX_UART1_BASE_PHYS;
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coyote_uart_data[0].irq = IRQ_IXP4XX_UART1;
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}
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platform_add_devices(coyote_devices, ARRAY_SIZE(coyote_devices));
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}
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#ifdef CONFIG_ARCH_ADI_COYOTE
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MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
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/* Maintainer: MontaVista Software, Inc. */
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.map_io = ixp4xx_map_io,
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.init_early = ixp4xx_init_early,
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.init_irq = ixp4xx_init_irq,
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.init_time = ixp4xx_timer_init,
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.atag_offset = 0x100,
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.init_machine = coyote_init,
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#if defined(CONFIG_PCI)
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.dma_zone_size = SZ_64M,
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#endif
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.restart = ixp4xx_restart,
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MACHINE_END
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#endif
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/*
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* IXDPG425 is identical to Coyote except for which serial port
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* is connected.
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*/
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#ifdef CONFIG_MACH_IXDPG425
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MACHINE_START(IXDPG425, "Intel IXDPG425")
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/* Maintainer: MontaVista Software, Inc. */
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.map_io = ixp4xx_map_io,
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.init_early = ixp4xx_init_early,
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.init_irq = ixp4xx_init_irq,
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.init_time = ixp4xx_timer_init,
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.atag_offset = 0x100,
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.init_machine = coyote_init,
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.restart = ixp4xx_restart,
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MACHINE_END
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#endif
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@ -1,56 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arm/mach-ixp4xx/ixdpg425-pci.c
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*
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* PCI setup routines for Intel IXDPG425 Platform
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*
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* Copyright (C) 2004 MontaVista Softwrae, Inc.
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*
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* Maintainer: Deepak Saxena <dsaxena@plexity.net>
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/mach-types.h>
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#include <mach/hardware.h>
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#include <asm/mach/pci.h>
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#include "irqs.h"
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void __init ixdpg425_pci_preinit(void)
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{
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irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
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ixp4xx_pci_preinit();
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}
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static int __init ixdpg425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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if (slot == 12 || slot == 13)
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return IRQ_IXP4XX_GPIO7;
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else if (slot == 14)
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return IRQ_IXP4XX_GPIO6;
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else return -1;
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}
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struct hw_pci ixdpg425_pci __initdata = {
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.nr_controllers = 1,
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.ops = &ixp4xx_ops,
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.preinit = ixdpg425_pci_preinit,
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.setup = ixp4xx_setup,
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.map_irq = ixdpg425_map_irq,
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};
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int __init ixdpg425_pci_init(void)
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{
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if (machine_is_ixdpg425())
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pci_common_init(&ixdpg425_pci);
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return 0;
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}
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subsys_initcall(ixdpg425_pci_init);
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