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pinctrl: ocelot: Add support for Serval platforms

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This patch adds support for Serval pinctrl, using the ocelot driver as
basis. It adds pinconfig support as well, as supported by the
platform.

gclement: Split from a larger patch adding support all platforms in
the same time.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Link: https://lore.kernel.org/r/20201106093118.965152-5-gregory.clement@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Lars Povlsen 2020-11-06 10:31:18 +01:00 committed by Linus Walleij
parent 8f27440dec
commit 6e6347e2da
1 changed files with 92 additions and 0 deletions
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92
drivers/pinctrl/pinctrl-ocelot.c
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@ -240,6 +240,88 @@ static const struct pinctrl_pin_desc luton_pins[] = {
LUTON_PIN(31),
};
#define SERVAL_P(p, f0, f1, f2) \
static struct ocelot_pin_caps serval_pin_##p = { \
.pin = p, \
.functions = { \
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
}, \
}
SERVAL_P(0, SG0, NONE, NONE);
SERVAL_P(1, SG0, NONE, NONE);
SERVAL_P(2, SG0, NONE, NONE);
SERVAL_P(3, SG0, NONE, NONE);
SERVAL_P(4, TACHO, NONE, NONE);
SERVAL_P(5, PWM, NONE, NONE);
SERVAL_P(6, TWI, NONE, NONE);
SERVAL_P(7, TWI, NONE, NONE);
SERVAL_P(8, SI, NONE, NONE);
SERVAL_P(9, SI, MD, NONE);
SERVAL_P(10, SI, MD, NONE);
SERVAL_P(11, SFP, MD, TWI_SCL_M);
SERVAL_P(12, SFP, MD, TWI_SCL_M);
SERVAL_P(13, SFP, UART2, TWI_SCL_M);
SERVAL_P(14, SFP, UART2, TWI_SCL_M);
SERVAL_P(15, SFP, PTP0, TWI_SCL_M);
SERVAL_P(16, SFP, PTP0, TWI_SCL_M);
SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M);
SERVAL_P(18, SFP, NONE, TWI_SCL_M);
SERVAL_P(19, SFP, NONE, TWI_SCL_M);
SERVAL_P(20, SFP, NONE, TWI_SCL_M);
SERVAL_P(21, SFP, NONE, TWI_SCL_M);
SERVAL_P(22, NONE, NONE, NONE);
SERVAL_P(23, NONE, NONE, NONE);
SERVAL_P(24, NONE, NONE, NONE);
SERVAL_P(25, NONE, NONE, NONE);
SERVAL_P(26, UART, NONE, NONE);
SERVAL_P(27, UART, NONE, NONE);
SERVAL_P(28, IRQ0, NONE, NONE);
SERVAL_P(29, IRQ1, NONE, NONE);
SERVAL_P(30, PTP0, NONE, NONE);
SERVAL_P(31, PTP0, NONE, NONE);
#define SERVAL_PIN(n) { \
.number = n, \
.name = "GPIO_"#n, \
.drv_data = &serval_pin_##n \
}
static const struct pinctrl_pin_desc serval_pins[] = {
SERVAL_PIN(0),
SERVAL_PIN(1),
SERVAL_PIN(2),
SERVAL_PIN(3),
SERVAL_PIN(4),
SERVAL_PIN(5),
SERVAL_PIN(6),
SERVAL_PIN(7),
SERVAL_PIN(8),
SERVAL_PIN(9),
SERVAL_PIN(10),
SERVAL_PIN(11),
SERVAL_PIN(12),
SERVAL_PIN(13),
SERVAL_PIN(14),
SERVAL_PIN(15),
SERVAL_PIN(16),
SERVAL_PIN(17),
SERVAL_PIN(18),
SERVAL_PIN(19),
SERVAL_PIN(20),
SERVAL_PIN(21),
SERVAL_PIN(22),
SERVAL_PIN(23),
SERVAL_PIN(24),
SERVAL_PIN(25),
SERVAL_PIN(26),
SERVAL_PIN(27),
SERVAL_PIN(28),
SERVAL_PIN(29),
SERVAL_PIN(30),
SERVAL_PIN(31),
};
#define OCELOT_P(p, f0, f1, f2) \
static struct ocelot_pin_caps ocelot_pin_##p = { \
.pin = p, \
@ -959,6 +1041,15 @@ static struct pinctrl_desc luton_desc = {
.owner = THIS_MODULE,
};
static struct pinctrl_desc serval_desc = {
.name = "serval-pinctrl",
.pins = serval_pins,
.npins = ARRAY_SIZE(serval_pins),
.pctlops = &ocelot_pctl_ops,
.pmxops = &ocelot_pmx_ops,
.owner = THIS_MODULE,
};
static struct pinctrl_desc ocelot_desc = {
.name = "ocelot-pinctrl",
.pins = ocelot_pins,
@ -1243,6 +1334,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev,
static const struct of_device_id ocelot_pinctrl_of_match[] = {
{ .compatible = "mscc,luton-pinctrl", .data = &luton_desc },
{ .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
{ .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },