staging: sm750fb: change definition of CURRENT_GATE multi-bit fields
Use more straight-forward definitions for multi-bit fields of CURRENT_GATE register and use open-coded implementation for register manipulation. Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -95,20 +95,20 @@ static void setMemoryClock(unsigned int frequency)
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divisor = roundedDiv(get_mxclk_freq(), frequency);
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/* Set the corresponding divisor in the register. */
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reg = PEEK32(CURRENT_GATE);
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reg = PEEK32(CURRENT_GATE) & ~CURRENT_GATE_M2XCLK_MASK;
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switch (divisor) {
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default:
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case 1:
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reg = FIELD_SET(reg, CURRENT_GATE, M2XCLK, DIV_1);
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reg |= CURRENT_GATE_M2XCLK_DIV_1;
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break;
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case 2:
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reg = FIELD_SET(reg, CURRENT_GATE, M2XCLK, DIV_2);
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reg |= CURRENT_GATE_M2XCLK_DIV_2;
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break;
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case 3:
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reg = FIELD_SET(reg, CURRENT_GATE, M2XCLK, DIV_3);
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reg |= CURRENT_GATE_M2XCLK_DIV_3;
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break;
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case 4:
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reg = FIELD_SET(reg, CURRENT_GATE, M2XCLK, DIV_4);
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reg |= CURRENT_GATE_M2XCLK_DIV_4;
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break;
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}
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@ -142,20 +142,20 @@ static void setMasterClock(unsigned int frequency)
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divisor = roundedDiv(get_mxclk_freq(), frequency);
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/* Set the corresponding divisor in the register. */
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reg = PEEK32(CURRENT_GATE);
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reg = PEEK32(CURRENT_GATE) & ~CURRENT_GATE_MCLK_MASK;
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switch (divisor) {
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default:
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case 3:
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reg = FIELD_SET(reg, CURRENT_GATE, MCLK, DIV_3);
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reg |= CURRENT_GATE_MCLK_DIV_3;
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break;
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case 4:
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reg = FIELD_SET(reg, CURRENT_GATE, MCLK, DIV_4);
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reg |= CURRENT_GATE_MCLK_DIV_4;
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break;
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case 6:
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reg = FIELD_SET(reg, CURRENT_GATE, MCLK, DIV_6);
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reg |= CURRENT_GATE_MCLK_DIV_6;
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break;
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case 8:
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reg = FIELD_SET(reg, CURRENT_GATE, MCLK, DIV_8);
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reg |= CURRENT_GATE_MCLK_DIV_8;
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break;
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}
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@ -391,29 +391,29 @@
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#define INT_MASK_VGA_VSYNC_ENABLE 1
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#define CURRENT_GATE 0x000040
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#define CURRENT_GATE_MCLK 15:14
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#define CURRENT_GATE_MCLK_MASK (0x3 << 14)
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#ifdef VALIDATION_CHIP
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#define CURRENT_GATE_MCLK_112MHZ 0
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#define CURRENT_GATE_MCLK_84MHZ 1
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#define CURRENT_GATE_MCLK_56MHZ 2
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#define CURRENT_GATE_MCLK_42MHZ 3
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#define CURRENT_GATE_MCLK_112MHZ (0x0 << 14)
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#define CURRENT_GATE_MCLK_84MHZ (0x1 << 14)
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#define CURRENT_GATE_MCLK_56MHZ (0x2 << 14)
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#define CURRENT_GATE_MCLK_42MHZ (0x3 << 14)
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#else
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#define CURRENT_GATE_MCLK_DIV_3 0
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#define CURRENT_GATE_MCLK_DIV_4 1
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#define CURRENT_GATE_MCLK_DIV_6 2
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#define CURRENT_GATE_MCLK_DIV_8 3
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#define CURRENT_GATE_MCLK_DIV_3 (0x0 << 14)
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#define CURRENT_GATE_MCLK_DIV_4 (0x1 << 14)
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#define CURRENT_GATE_MCLK_DIV_6 (0x2 << 14)
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#define CURRENT_GATE_MCLK_DIV_8 (0x3 << 14)
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#endif
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#define CURRENT_GATE_M2XCLK 13:12
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#define CURRENT_GATE_M2XCLK_MASK (0x3 << 12)
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#ifdef VALIDATION_CHIP
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#define CURRENT_GATE_M2XCLK_336MHZ 0
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#define CURRENT_GATE_M2XCLK_168MHZ 1
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#define CURRENT_GATE_M2XCLK_112MHZ 2
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#define CURRENT_GATE_M2XCLK_84MHZ 3
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#define CURRENT_GATE_M2XCLK_336MHZ (0x0 << 12)
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#define CURRENT_GATE_M2XCLK_168MHZ (0x1 << 12)
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#define CURRENT_GATE_M2XCLK_112MHZ (0x2 << 12)
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#define CURRENT_GATE_M2XCLK_84MHZ (0x3 << 12)
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#else
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#define CURRENT_GATE_M2XCLK_DIV_1 0
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#define CURRENT_GATE_M2XCLK_DIV_2 1
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#define CURRENT_GATE_M2XCLK_DIV_3 2
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#define CURRENT_GATE_M2XCLK_DIV_4 3
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#define CURRENT_GATE_M2XCLK_DIV_1 (0x0 << 12)
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#define CURRENT_GATE_M2XCLK_DIV_2 (0x1 << 12)
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#define CURRENT_GATE_M2XCLK_DIV_3 (0x2 << 12)
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#define CURRENT_GATE_M2XCLK_DIV_4 (0x3 << 12)
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#endif
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#define CURRENT_GATE_VGA BIT(10)
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#define CURRENT_GATE_PWM BIT(9)
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