platform/mellanox: mlxbf-tmfifo: Fix a memory barrier issue
[ Upstream commit 1c0e5701c5e792c090aef0e5b9b8923c334d9324 ] The virtio framework uses wmb() when updating avail->idx. It guarantees the write order, but not necessarily loading order for the code accessing the memory. This commit adds a load barrier after reading the avail->idx to make sure all the data in the descriptor is visible. It also adds a barrier when returning the packet to virtio framework to make sure read/writes are visible to the virtio code. Fixes: 1357dfd7261f ("platform/mellanox: Add TmFifo driver for Mellanox BlueField Soc") Signed-off-by: Liming Sun <limings@nvidia.com> Reviewed-by: Vadim Pasternak <vadimp@nvidia.com> Link: https://lore.kernel.org/r/1620433812-17911-1-git-send-email-limings@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -294,6 +294,9 @@ mlxbf_tmfifo_get_next_desc(struct mlxbf_tmfifo_vring *vring)
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if (vring->next_avail == virtio16_to_cpu(vdev, vr->avail->idx))
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return NULL;
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/* Make sure 'avail->idx' is visible already. */
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virtio_rmb(false);
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idx = vring->next_avail % vr->num;
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head = virtio16_to_cpu(vdev, vr->avail->ring[idx]);
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if (WARN_ON(head >= vr->num))
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@ -322,7 +325,7 @@ static void mlxbf_tmfifo_release_desc(struct mlxbf_tmfifo_vring *vring,
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* done or not. Add a memory barrier here to make sure the update above
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* completes before updating the idx.
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*/
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mb();
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virtio_mb(false);
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vr->used->idx = cpu_to_virtio16(vdev, vr_idx + 1);
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}
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@ -730,6 +733,12 @@ static bool mlxbf_tmfifo_rxtx_one_desc(struct mlxbf_tmfifo_vring *vring,
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desc = NULL;
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fifo->vring[is_rx] = NULL;
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/*
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* Make sure the load/store are in order before
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* returning back to virtio.
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*/
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virtio_mb(false);
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/* Notify upper layer that packet is done. */
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spin_lock_irqsave(&fifo->spin_lock[is_rx], flags);
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vring_interrupt(0, vring->vq);
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