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mlxsw: core: Define latency TLV fields

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The next patch will add support for latency TLV as part of EMAD (Ethernet
Management Datagrams) packets. As preparation, add the relevant fields.

Signed-off-by: Danielle Ratson <danieller@nvidia.com>
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Amit Cohen 2023-01-19 11:32:31 +01:00 committed by Jakub Kicinski
parent 695f7306d9
commit 6ee0d3a9dc
1 changed files with 16 additions and 0 deletions
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16
drivers/net/ethernet/mellanox/mlxsw/core.c
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@ -378,6 +378,22 @@ MLXSW_ITEM32(emad, string_tlv, len, 0x00, 16, 11);
MLXSW_ITEM_BUF(emad, string_tlv, string, 0x04,
MLXSW_EMAD_STRING_TLV_STRING_LEN);
/* emad_latency_tlv_type
* Type of the TLV.
* Must be set to 0x4 (latency TLV).
*/
MLXSW_ITEM32(emad, latency_tlv, type, 0x00, 27, 5);
/* emad_latency_tlv_len
* Length of the latency TLV in u32.
*/
MLXSW_ITEM32(emad, latency_tlv, len, 0x00, 16, 11);
/* emad_latency_tlv_latency_time
* EMAD latency time in units of uSec.
*/
MLXSW_ITEM32(emad, latency_tlv, latency_time, 0x04, 0, 32);
/* emad_reg_tlv_type
* Type of the TLV.
* Must be set to 0x3 (register TLV).